3d integration & packaging challenges with through-silicon...

IBM Research © 2012 IBM Corporation

Dr John U. Knickerbocker

IBM - T.J. Watson Research, New York, USA

NSF Workshop – 2/02/2012

3D Integration & Packaging Challengeswith through-silicon-vias (TSV)

Substrate

© 2012 IBM Corporation2 IBM Research

Acknowledgements

IBM Research & S&TG

- P. Andry

- E. Colgan

- B. Dang

- T. Dickson

- M. Farooq

- C. Jahnes

- J. Maria

- R. Polastre

- C. Tsang

- C. Tyberg

- B. Webb

- S. Wright


Applications

Low Cost

Pocket Size / Small Form Factor

Increasing Function @ Same orSmaller Size

Lower Power

Local transactions

Wireless

High Bandwidth / High Data Rate

Security

High Volume / Time to Market

System Trends & 3D Technology Integration Benefits

Applications

Power Efficiency

Performance

- Multi-core

- Multi-thread

- High Bandwidth

- HeterogeneousIntegration

Cost

Security

Reliability

Consumer / Network Appliances / Sensors Computers / Servers / Cloud / HPC

Power – Efficiency

Scalability / Modularity

Heterogeneous Integration

Increasing BW / Function

Lower Cost

3DTechnology

Applications

Low Cost

Pocket Size / Small Form Factor

Increasing Function @ Same orSmaller Size

Lower Power

Local transactions

Wireless

High Bandwidth / High Data Rate

Security

High Volume / Time to Market

System Trends & 3D Technology Integration Benefits

Applications

Power Efficiency

Performance

- Multi-core

- Multi-thread

- High Bandwidth

- HeterogeneousIntegration

Cost

Security

Reliability

Consumer / Network Appliances / Sensors Computers / Servers / Cloud / HPC

Power – Efficiency

Scalability / Modularity

Heterogeneous Integration

Increasing BW / Function

Lower Cost

3DTechnology


Packaging Integration Density In

tegr

atio

n D

ensi

ty

(I/O

per

squ

are

cm)

I/O: 150 um pitch4,400 I/O / sq. cmWiring pitch: 40 to 150 μm

I/O: 6 μm pitch2,500,000 I/O / sq. cmWiring pitch: 90 nm

I/O: 50 μm pitch40,000 I/O / sq. cmWiring pitch: 2 μm

Organic & Ceramic Pkg(SCM & MCM)

Si on Si Package & Chip Stacking w / TSV

3D ICIntegration

Time

I/O: 200 μm pitch2,500 I/O / sq. cmWiring pitch: 50 to 200 μm

Packaging Integration Density In

tegr

atio

n D

ensi

ty

(I/O

per

squ

are

cm)

I/O: 150 um pitch4,400 I/O / sq. cmWiring pitch: 40 to 150 μm

I/O: 6 μm pitch2,500,000 I/O / sq. cmWiring pitch: 90 nm

I/O: 50 μm pitch40,000 I/O / sq. cmWiring pitch: 2 μm

Organic & Ceramic Pkg(SCM & MCM)

Si on Si Package & Chip Stacking w / TSV

3D ICIntegration

Time

I/O: 200 μm pitch2,500 I/O / sq. cmWiring pitch: 50 to 200 μm


3D IntegrationAdvantages:

Short vertical interconnectsMiniaturizationHigher Bandwidth / lower latencyNew Function in small form factorLower power / energy savingsImproved performance / streaming Lower Cost

Challenges:Architecture / Design to leverage 3D technologyPower Delivery / Thermal Mgt – Application DependentIndustry Compatibility & Standards MFG Equipment, Process, Assembly & Fine pitch Wafer Test

3D IntegrationAdvantages:

Short vertical interconnectsMiniaturizationHigher Bandwidth / lower latencyNew Function in small form factorLower power / energy savingsImproved performance / streaming Lower Cost

Challenges:Architecture / Design to leverage 3D technologyPower Delivery / Thermal Mgt – Application DependentIndustry Compatibility & Standards MFG Equipment, Process, Assembly & Fine pitch Wafer Test


3D Challenges 3D Readiness1. 3D Architecture. Circuits, Timing, EDA Tools, Modeling Data Library / Fabrication Rules

2. 3D Technology & Integration Elements Material, Structure, Processes

- Thinned Si

- Through – Silicon - Via (TSV)

- Silicon - Silicon Interconnection (SSI)

- Module Integration

- Assembly - Test (WLT for KGD)

- Power delivery - Cooling

3. Introduction of New Function or New Competitive Product Value Add

- Industry Infrastructure, 3D Standards - Miniaturization- 3D Products Volume Lower Costs - Function

Design / Architecture for lower costs (Perf., Power, Het. Integ.)

Power Efficiency, Performance - Standards

New Applications / Size / Function

3D-Technology Challenges & Readiness

Chip Stack

Substrate

3D Challenges 3D Readiness1. 3D Architecture. Circuits, Timing, EDA Tools, Modeling Data Library / Fabrication Rules

2. 3D Technology & Integration Elements Material, Structure, Processes

- Thinned Si

- Through – Silicon - Via (TSV)

- Silicon - Silicon Interconnection (SSI)

- Module Integration

- Assembly - Test (WLT for KGD)

- Power delivery - Cooling

3. Introduction of New Function or New Competitive Product Value Add

- Industry Infrastructure, 3D Standards - Miniaturization- 3D Products Volume Lower Costs - Function

Design / Architecture for lower costs (Perf., Power, Het. Integ.)

Power Efficiency, Performance - Standards

New Applications / Size / Function

3D-Technology Challenges & Readiness

Chip Stack

Substrate

Chip Stack

Substrate Substrate

Low power link -


VLSI Design for Stacked Die with TSV’s

Design considerations for 3D stacked die with TSV’s

- Design tools, know-how, micro-architecture- EDA tools- Physical floor planning & partitioning- Electrical design and models- Checking and verification- Power & thermal models

- Chip Infrastructure- Power & ground delivery and distribution - Clock distribution

- IP Blocks- Custom and random logic- SRAM, eDRAM and other memory- FPGA- Analog, special functions- In die-stack link- Off die-stack I/O

Substrate

Processor

Memory

Substrate

ProcessorMemoryMemory


3D Silicon Integration

3D Die Stack & Si Pkg Integration

3D Silicon Pkg Integration

Substrate

Circuits , Trench Capacitors

Cooling

Silicon Package

Cu Wiring

TSV

SSI

Base Substrate

TSV

SSI

Die Stack

Si Package

3D Silicon Integration

3D Die Stack & Si Pkg Integration

3D Silicon Pkg Integration

Substrate

Circuits , Trench Capacitors

Cooling

Silicon Package

Cu Wiring

TSV

SSI

Base Substrate

TSV

SSI

Die Stack

Si Package


Architecture - Design - Build - Characterization

Few Examples of 3D Test Vehicles- TV’s silicon through via development- TV’s high density wiring, signal integrity

& cross talk (Si Carrier & Die Stack (TSV, Link & uC-4)- TV’s high I/O interconnection & chip stacking- TV’s active circuit die stacks (Funct., EDA, etc)- TV’s optical, thermal, module assessments - TV’s for reliability

TSV

18-bump chain.

SiSi

OE

CMOS IC

Organic Chip Package waveguide

SiliconThru-via

Substrate Decoupling Capacitors

CoolingChipChip

CoolerChip 1Chip 2

*ECTC 2008 – Doany et al.


High Bandwidth Wiring & Link characterizationWiring - Signal & Ground Test Vehicle

TSV Characterization (Example) Micro-joint solder ( 25 um dia & 50 um pitch)- Inductance - DC resistance- DC resistance - DTC

- EMBEOL Characterization Decoupling Capacitors

- Signal integrity vs Distance & Data rate - 10 - 14 uF/cm2 demonstrated / with TSV- Far end X-talk: Design dependent

Chip To Chip & Chip Stack Link Characterization Modeling and Data Library- Signal integrity, Data rate, X-Talk, …. - Frequency & Time Domain


High Bandwidth, Link Characterization & Energy Efficiency

Dickson et al. VLSI


Si carrier

Si

Si

Si

Thin die & Multi-high uC-4 Die Stack Assembly

Si Die

Top Chip

Ceramic or Organic Substrate

TSV = Cu or W

TSV pitch = 50 um

uC-4 = Solder

uC-4 pitch = 50 um

Si carrier

Si

Si

Si

Si carrier

Si

SiSi

Si

Thin die & Multi-high uC-4 Die Stack Assembly

Si Die

Top Chip


Si Die

Top Chip


TSV = Cu or W

TSV pitch = 50 um

uC-4 = Solder

uC-4 pitch = 50 um


3D-Technology Research & Manufacturing Summary3D

Int

egra

tion

Research

Dev / Mfg / Products

Time

3D Stack& Si Pkg

3D Chip

Si Pkg

- Architecture / Design - Assembly (C2C, C2W, W2W)

- Design Tools / Circuits - IP Library & Models

- TSV Dia, Pitch / Si Thickness - Electrical, Mechanical, Thermal

- CMOS Wafer Integration & Finishing - Test & Reliability

- Stack Interconnection size, pitch: - Modeling Performance, Power, Cost

-- Architecture - Design / Structure / Size

-- Application Sizing - Wafers 200 mm / 300mm

- - Cost Sizing - Design Kits

- - Technology Qualifications - Technology Platforms

- - Product Qualifications

3D-Technology Research & Manufacturing Summary3D

Int

egra

tion

Research

Dev / Mfg / Products

Time

3D Stack& Si Pkg

3D Chip

Si PkgSi Pkg

- Architecture / Design - Assembly (C2C, C2W, W2W)

- Design Tools / Circuits - IP Library & Models & Low power links

- TSV Dia, Pitch / Si Thickness - Electrical, Mechanical, Thermal

- CMOS Wafer Integration & Finishing - Test & Reliability

- Stack Interconnection size, pitch: - Modeling Performance, Power, Cost

-- Architecture - Design / Structure / Size

-- Application Sizing - Wafers 200 mm / 300mm

- - Cost Sizing - Design Kits

- - Technology Qualifications - Technology Platforms

- - Product Qualifications


SummaryOpportunity to Improve our Quality of Life

Sensors Data Management Energy efficiency / GreenPersonal Handheld Servers & High Performance Computers

IBM 3D Technology Advancements / Mfg3D Technology ElementsTSVDie Stack Integration platformsSilicon Package Integration platforms

System / Hardware Demonstrations Application Dependent on 3D Architecture & DesignEfficient Integration & Optimization over timeCost Benefits, Power Efficiency, Performance, Size, …3D Silicon Integration Demonstrations Si Pkg

SummaryOpportunity to Improve our Quality of Life

Sensors Data Management Energy efficiency / GreenPersonal Handheld Servers & High Performance Computers

IBM 3D Technology Advancements / Mfg3D Technology ElementsTSV Higher density Die Stack Integration platformsSilicon Package Integration platforms

System / Hardware Demonstrations Application Dependent on 3D Architecture & DesignEfficient Integration & Optimization over timeCost Benefits, Power Efficiency, Performance, Size, …3D Silicon Integration Demonstrations Si PkgSi Pkg

Low power electrical interconnects 3D Stack & 2.5D Pkg

3d integration & packaging challenges with through-silicon...

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