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The Pennsylvania State University The Graduate School Department of Computer Science and Engineering

A TIQ BASED CMOS FLASH A/D CONVERTER FOR SYSTEM-ON-CHIP APPLICATIONS

A Thesis in Computer Science and Engineering by Jincheol Yoo c 2003 Jincheol Yoo

Submitted in Partial Fulllment of the Requirements for the Degree of

Doctor of Philosophy May 2003

We approve the thesis of Jincheol Yoo.

Date of Signature

Kyusun Choi Assistant Professor of Computer Science and Engineering Thesis Adviser Chair of Committee

Mary Jane Irwin Distinguished Professor of Computer Science and Engineering

Vijaykrishnan Narayanan Assistant Professor of Computer Science and Engineering

Charles L. Croskey Professor of Electrical Engineering

Raj Acharya Professor of Computer Science and Engineering Head of the Department of Computer Science and Engineering

iii

Abstract

The analog-to-digital converter (ADC) is an essential part of system-on-chip (SoC) products because it bridges the gap between the analog physical world and the digital logical world. In the digital domain, low power and low voltage requirements are becoming more important issues as the channel length of MOSFET shrinks below 0.25 sub-micron values. Moreover, SoC trends force ADCs to be integrated on the chip with other digital circuits. These trends present new challenges in ADC circuit design. Thus, this thesis is to investigate high speed, low power, and low voltage CMOS ash ADCs for SoC applications. The proposed ADC utilizes the Threshold Inverter Quantization (TIQ) technique that uses two cascaded CMOS inverters as a comparator. The TIQ technique has been introduced in [53]. The TIQ technique proposed here has been developed for better implementation in SoC applications. Four issues are addressed to achieve high speed, low power consumption, and low voltage operation in the TIQ ash ADC. First, the high speed and low power TIQ ash ADC architecture is presented along with an optimal design method - called the systematic size variation (SSV) technique - for reducing the impacts of the process variation. Second, a new digital encoder called the fat tree encoder is introduced. The fat tree encoder replaces the ROM type encoder that is the speed bottleneck. Next, for low power applications, a power and resolution adaptive ash ADC (PRA-ADC) and a power management method in the TIQ ash ADC are presented to reduce/manage power consumption. Finally, a new voltage comparator, called the

iv Quantum Voltage (QV) comparator, for next generation deep sub-micron low voltage CMOS ash ADC is proposed. In addition to the above four issues, simulation results and fabrication results of the TIQ ash ADC are discussed. The preliminary results show that the TIQ ash ADC achieves high speed, small size, low power consumption, and low voltage operation compared to other ADCs.

v

Table of Contents

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ix

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xi

Acknowledgments

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xiv

Chapter 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 1.2 1.3 Challenges in Designing ADCs for SoC . . . . . . . . . . . . . . . . . Solid-State Technology . . . . . . . . . . . . . . . . . . . . . . . . . . Thesis Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1 1 3 4

Chapter 2. A/D Converter Background . . . . . . . . . . . . . . . . . . . . . . . 2.1 ADC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 Static Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1.1 2.1.1.2 2.1.1.3 2.1.2 Oset and Gain Error . . . . . . . . . . . . . . . . . Dierential Non-Linearity Error (DNL) . . . . . . . Integral Non-Linearity Error (INL) . . . . . . . . . .

6 6 7 8 9 11 12 12 13 13 14

Dynamic Parameters . . . . . . . . . . . . . . . . . . . . . . . 2.1.2.1 2.1.2.2 2.1.2.3 2.1.2.4 Signal-to-Noise Ratio (SNR) . . . . . . . . . . . . . Signal-to-Noise and Distortion Ratio (SINAD) . . . Total Harmonic Distortion (THD) . . . . . . . . . . Eective Number of Bits (ENOB) . . . . . . . . . .

vi 2.1.2.5 2.2 Spurious-Free Dynamic Range (SFDR) . . . . . . . 14 14 16 19 20 22 23

ADC Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 Flash ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pipelined ADC . . . . . . . . . . . . . . . . . . . . . . . . . . Successive Approximation ADC . . . . . . . . . . . . . . . . . ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary of ADC Architectures . . . . . . . . . . . . . . . .

Chapter 3. TIQ Flash ADC 3.1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

25 27 27 29 30 31 31 33 33 37 38 39 41

TIQ Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1 CMOS Inverter as a Comparator . . . . . . . . . . . . . . . . 3.1.1.1 3.1.1.2 3.1.1.3 3.1.2 Sensitivity to Process . . . . . . . . . . . . . . . . . Sensitivity to Temperature . . . . . . . . . . . . . . Sensitivity to Power Supply Voltage . . . . . . . . .

Comparator Generation and Selection Method . . . . . . . . 3.1.2.1 3.1.2.2 Random Size Variation (RSV) Technique . . . . . . Systematic Size Variation (SSV) Technique . . . . .

3.2 3.3

Gain Booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TC-to-BC Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 3.3.2 ROM Type Encoder . . . . . . . . . . . . . . . . . . . . . . . Fat Tree Encoder . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 4. Experimental Results and Evaluations . . . . . . . . . . . . . . . . . 4.1 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . .

43 43

vii 4.1.1 TIQ Flash ADC Performance . . . . . . . . . . . . . . . . . . 4.1.1.1 4.1.1.2 4.1.1.3 4.1.2 4.1.3 4.2 Simulation Results of 0.25 m technology . . . . . . Simulation Results of 0.18 m technology . . . . . . Simulation Results of 0.50 m technology . . . . . . 45 49 56 60 64 68 70 71 76 78 81 83

Variation Eects on the RSV and SSV Techniques . . . . . . Fat Tree Encoder vs. ROM Type Encoders . . . . . . . . . .

Fabrication Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 4.2.2 Test Results of 0.25 m TIQ ash ADC Chips . . . . . . . . Test Results of 0.18 m TIQ ash ADC Chips . . . . . . . . 4.2.2.1 4.2.2.2 4.2.3 Noise eects on the ADCs . . . . . . . . . . . . . . . Fast Fourier Transform (FFT) Test Results . . . . .

Test Results of 0.50 m TIQ ash ADC Chips . . . . . . . .

Chapter 5. Low Power Applications with TIQ Comparator . . . . . . . . . . . . 5.1 The Power and Resolution Adaptive Flash ADC (PRA-ADC) . . . . 5.1.1 5.1.2 5.1.3 5.2 PRA-ADC Design and Layout . . . . . . . . . . . . . . . . . PRA-ADC Simulation Results . . . . . . . . . . . . . . . . .

84 84 85 90 93 93 95 97 99

Summary of the PRA-ADC . . . . . . . . . . . . . . . . . . .

A Power Management Method in the TIQ Flash ADC . . . . . . . . 5.2.1 5.2.2 5.2.3 Power Management Method . . . . . . . . . . . . . . . . . . . Power Simulation Results . . . . . . . . . . . . . . . . . . . . Summary of the Power Management Method . . . . . . . . .

Chapter 6. Low Voltage Operation in ADCs . . . . . . . . . . . . . . . . . . . .

101

viii 6.1 Low Voltage Operation with the TIQ ash ADC . . . . . . . . . . . 6.1.1 6.1.2 6.2 Power Analysis of the TIQ ash ADC . . . . . . . . . . . . . Voltage and Temperature Variations in 0.07 m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 103 106 108 109 110 112 114 116

Quantum Voltage Comparator 6.2.1 6.2.2

Simple Transconductance Amplier . . . . . . . . . . . . . . . Flash ADC with QV comparator . . . . . . . . . . . . . . . . 6.2.2.1 6.2.2.2 The QV Comparator . . . . . . . . . . . . . . . . .

ADC Design with QV comparator . . . . . . . . . .

6.2.3

Simulation Results and Comparisons with TIQ Comparator . 6.2.3.1 Power Consumption Comparison with TIQ Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.3.2 Noise Comparisons with TIQ Comparator . . . . . .

118 119 119

6.2.4

Summary of the QV Comparator . . . . . . . . . . . . . . . .

Chapter 7. Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

122

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

127

Appendix A. DNL and INL Calculating Program . . . . . . . . . . . . . . . . .

137

Appendix B. MOSIS Parametric Test Results for TSMC 0.25 m CMOS Run .

139

Appendix C. MOSIS Parametric Test Results for TSMC 0.18 m CMOS Run .

143

Appendix D. MOSIS Parametric Test Results for AMI C5 (0.50 m) Run . . . .

147

ix

List of Tables

2.1 4.1 4.2 4.3 4.4

Summary of ADC architectures . . . . . . . . . . . . . . . . . . . . . . . Comparator transistor sizes used in 0.25 m design . . . . . . . . . . . . Simulation results of 0.25 m TIQ ash ADCs . . . . . . . . . . . . . . Process variation result in an 8-bit TIQ ash ADC . . . . . . . . . . . . Temperature and power supply voltage variation results in the 8-bit TIQ ash ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

24 49 50 52

53 56 58 59 62 63 66

4.5 4.6 4.7 4.8 4.9

Simulation results of 0.18 m TIQ ash ADCs . . . . . . . . . . . . . . Variation results in a