unit ii and iii comb ckt

8/9/2019 Unit II and III Comb Ckt

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UNIT II and III-

COMBINATIONAL

CIRCUITS

Logic gates have one or more inputs and only one output. The

active only for certain input combinations. Logic gates are thblocks of any digital circuit. Logic gates are also called switchesadvent of integrated circuits, switches have been replaced(Transistor Transistor Logic) circuits and C!" circuits. #ee%ample circuits on how to construct simples gates.

"ymbolic Logic

&oolean algebra derives its name from the mathematician 'eo"ymbolic Logic uses values, variables and operations.

Inversion

small circle on an input or an output indicates inversion. "ee

* and !+ gates given below for e%amples.


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Multiple Input Gates

'iven commutative and associative laws, many logic gates can be iwith more than two inputs, and for reasons of space in circuits, usually multiple inpgates are made. ou will encounter such gates in real world (maybe you could anal

lib to find this).

*

!+

!T

&/

*

!+

0!+

0!+

AND GateThe * gate performs logical multiplication, commonly known as The * gate has two or more inputs and single output. The output of#$'# only when all its inputs are #$'# (i.e. even if one input is L!Wbe L!W).

$f 0 and are two inputs, then output / can be represented mathemat0., #ere dot (.) denotes the * operation. Truth table and symbogate is shown in the figure below.


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Symbol

Truth Table

X Y F=(X.Y

2 2 2

2 3 2

3 2 2

3 3 3

Two input * gate using 4diode5resistor4 logic is shown in figure belo are inputs and / is the output.

!ir"uit

$f 0 1 2 and 1 2, then both diodes *3 and *6 are forward biased adiodes conduct and pull / low.

$f 0 1 2 and 1 3, *6 is reverse biased, thus does not conduct. &ut *biased, thus conducts and thus pulls / low.


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$f 0 1 3 and 1 2, *3 is reverse biased, thus does not conduct. &ut *biased, thus conducts and thus pulls / low.

$f 0 1 3 and 1 3, then both diodes *3 and *6 are reverse biased a

the diodes are in cut5off and thus there is no drop in voltage at /. Thus

S#it"h $epresentation o% AND Gate

$n the figure below, 0 and are two switches which have been connec(or 7ust cascaded) with the load L8* and source battery. When both closed, current flows to L8*.

Three Input AND &ate

"ince we have already seen how a * gate works and $ will 7ust table of a 9 input * gate. The figure below shows its symbol and tru

!ir"uit

Truth Table

X Y ' F=X.Y.'

2 2 2 2

2 2 3 2

2 3 2 2

2 3 3 2

3 2 2 2


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3 2 3 2

3 3 2 2

3 3 3 3

$ Gate

The !+ gate performs logical addition, commonly known as !+ functgate has two or more inputs and single output. The output of !+ gate when any one of its inputs are #$'# (i.e. even if one input is #$'#, !#$'#).

$f 0 and are two inputs, then output / can be represented mathemat0:. #ere plus sign (:) denotes the !+ operation. Truth table and s!+ gate is shown in the figure below.

Symbol

Truth Table

X Y F=(X)Y

2 2 2

2 3 3

3 2 3

3 3 3

Two input !+ gate using 4diode5resistor4 logic is shown in figure beloware inputs and / is the output.

!ir"uit


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$f 0 1 2 and 1 2, then both diodes *3 and *6 are reverse biased athe diodes are in cut5off and thus / is low.

$f 0 1 2 and 1 3, *3 is reverse biased, thus does not conduct. &ut *

biased, thus conducts and thus pulling / to #$'#.

$f 0 1 3 and 1 2, *6 is reverse biased, thus does not conduct. &u*3 is forward biased, thus conducts and thus pulling / to #$'#.

$f 0 1 3 and 1 3, then both diodes *3 and *6 are forward biased andthus both the diodes conduct and thus / is #$'#.

S#it"h $epresentation o% $ Gate

$n the figure, 0 and are two switches which have been connected in

parallel, and this is connected in series with the load L8* and sourcebattery. When both switches are open, current does not flow to L8*but when any switch is closed then current flows.

Three Input $ &ate

"ince we have already seen how an !+ gate works, $ will 7ust list thetruth table of a 95input !+ gate. The figure below shows its circuit andtruth table.


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!ir"uit

Truth Table

X Y ' F=X)Y)'

2 2 2 2

2 2 3 3

2 3 2 3

2 3 3 3

3 2 2 3

3 2 3 3

3 3 2 3

3 3 3 3

Y2 = I4 + I5 + I6 +I7

Based on the above equations, we can draw the circuit as shown below

Circuit


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Example - Decimal-to-Binary Encoder

DecimaltoBinar! ta"e #$ in%uts and %rovides 4 out%uts, thus doin& the

o%%osite o' what the 4to#$ decoder does( )t an! one time, onl! one in%utline has a value o' #( *he 'i&ure below shows the truth table o' a Decimalto

binar! encoder(

Trut Ta!le

I" I# I$ I% I& I' I( I) I* I+ ,% ,$ ,# ,"

# $ $ $ $ $ $ $ $ $ $ $ $ $

$ # $ $ $ $ $ $ $ $ $ $ $ #

$ $ # $ $ $ $ $ $ $ $ $ # $

$ $ $ # $ $ $ $ $ $ $ $ # #

$ $ $ $ # $ $ $ $ $ $ # $ $

$ $ $ $ $ # $ $ $ $ $ # $ #

$ $ $ $ $ $ # $ $ $ $ # # $$ $ $ $ $ $ $ # $ $ $ # # #

$ $ $ $ $ $ $ $ # $ # $ $ $

$ $ $ $ $ $ $ $ $ # # $ $ #

rom the above truth table , we can derive the 'unctions Y, Y2, Y# and Y$ a

&iven below(

Y = I- + I.

Y2 = I4 + I5 + I6 + I7

Y# = I2 + I + I6 + I7

Y$ = I# + I + I5 + I7 + I.

riority Encoder

I' we loo" care'ull! at the /ncoder circuits that we &ot, we see the 'ollowin&limitations( I' more then two in%uts are active simultaneousl!, the out%ut is

un%redictable or rather it is not what we e0%ect it to be(

*his ambi&uit! is resolved i' %riorit! is established so that onl! one in%ut is

encoded, no matter how man! in%uts are active at a &iven %oint o' time(

*he %riorit! encoder includes a %riorit! 'unction( *he o%eration o' the %riorit!

encoder is such that i' two or more in%uts are active at the same time, the in%u

havin& the hi&hest %riorit! will ta"e %recedence(


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Example - &to% riority Encoder

*he truth table o' a 4in%ut %riorit! encoder is as shown below( *he in%ut D

has the hi&hest %riorit!, D2 has ne0t hi&hest %riorit!, D$ has the lowest%riorit!( *his means out%ut Y2 and Y# are $ onl! when none o' the in%uts D#

D2, D are hi&h and onl! D$ is hi&h(

) 4 to encoder consists o' 'our in%uts and three out%uts, truth table and

s!mbols o' which is shown below(

Trut Ta!le

D% D$ D# D" ,$ ,# ,"

$ $ $ $ $ $ $

$ $ $ # $ $ #

$ $ # 0 $ # $

$ # 0 0 $ # ## 0 0 0 # $ $

1ow that we have the truth table, we can draw the ma%s as shown b

.map/

rom the ma% we can draw the circuit as shown below( or Y2, we


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3e can a%%l! the same lo&ic to &et hi&her order %riorit! encoders(

Multiplexer

) multi%le0er 8 is a di&ital switch which connec

out%ut( ) number o' select in%uts determine which dat*he bloc" dia&ram o' with n data sources o' b b

shown in below 'i&ure(

acts li"e a di&itall! controlled multi%osition sw

the select in%uts controls the in%ut source that will be the 'i&ure below( )t an! &iven %oint o' time onl! one i

out%ut, based on the select in%ut si&nal(

Mecanical E0ui1alent o2 a Multiplexer

*he o%eration o' a multi%le0er can be better e0%lainedin the 'i&ure below( *his rotar! switch can touch an! o

out%ut( )s !ou can see at an! &iven %oint o' time onl!


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Example - $x# MU3

) 2 to # line multi%le0er is shown in 'i&ure below, eacin%ut o' an )1D &ate( 9election lines 9 are decoded to

truth table 'or the 2:# mu0 is &iven in the table below(

Sym!ol

Trut Ta!le

S ,

$ )

# B

De/i4n o2 a $5# Mux

*o derive the &ate level im%lementation o' 2:# mu0 w

'i&ure( )nd once we have the truth table, we can draw

the cases when Y is equal to ;#;(


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Y = )(9; + B(9

Trut Ta!leB A S

$ $ $

$ $ #

$ # $

$ # #

# $ $

# $ #

# # $

# # #

.map

Circuit

Example 5 &5# MU3


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) 4 to # line multi%le0er is shown in 'i&ure below, eac

one in%ut o' an )1D &ate( 9election lines 9$ and 9# a

&ate( *he truth table 'or the 4:# mu0 is &iven in the tab

Sym!ol

Trut Ta!le

S# S"

$ $

$ #

# $

# #

Circuit


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Lar4er Multiplexer/

ar&er multi%le0ers can be constructed 'rom smaller o

constructed 'rom smaller multi%le0ers as shown below

Example - *-to-# multiplexer 2rom Smaller MU3

Trut Ta!le

S$ S# S"

$ $ $

$ $ #

$ # $

$ # #

# $ $

# $ #

# # $# # #

Circuit

Example - #(-to-# multiplexer 2rom &5# mux


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De-multiplexer/

*he! are di&ital switches which c

one o' n out%uts(

suall! im%lemented b! usin& ntdecoder enable line is used 'or da

*he 'i&ure below shows a demulsbitswide select in%ut, one bbit

out%uts(


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Mecanical E0ui1alent o2 a De-

*he o%eration o' a demulti%le0er

mechanical switch as shown in thtouch an! o' the out%uts, which is

see at an! &iven %oint o' time onl!

#bit 4out%ut demulti%le0er usin

Example5 #-to-& De-multiplexer

Sym!ol


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Trut Ta!le

S# S" 6"

$ $ D

$ # $

# $ $

# # $

Boolean 6unction Implementation

/arlier we had seen that it is %ossible to im%lement Boolean 'unc

decoders( In the same wa! it is also %ossible to im%lement Booleusin& mu0ers and demu0ers(

Implementin4 6unction/ Multiplexer/

)n! nvariable lo&ic 'unction can be im%lemented usin& a smalle

inverter e(& 4to# mu0 to im%lement variable 'unctions8 as 'o

/0%ress 'unction in canonical sumo'minterms 'orm(


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Im%lement the 'unction ,Y,>8 = 9#,,5,68 usin& an -to# mu

in%ut variables , Y, > to mu0 select lines( u0 data in%ut lines #

corres%ond to the 'unction minterms are connected to #( *he rem

in%ut lines $, 2, 4, 7 are connected to $(

Example5 %-1aria!le 6unction U/in4 &-to-# mux

Im%lement the 'unction ,Y,>8 = 9$,#,,68 usin& a sin&le 4to

inverter( 3e choose the two most si&ni'icant in%uts , Y as mu0

and the 'unction 'or the corres%ondin& selection line


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when Y=$$ the 'unction is # 'or both >=$, >=#8 thu

when Y=$# the 'unction is > thus mu0 in%ut# = >

when Y=#$ the 'unction is $ 'or both >=$, >=#8 thu

when Y=## the 'unction is >; thus mu0 in%ut = >;

Example5 $ to & Decoder u/in4 Demux

Mux-Demux Application Example

*his enables sharin& a sin&le communication line amon& a numb

source and one destination can use the communication line(

Introduction

)rithmetic circuits are the ones which %er

addition, subtraction, multi%lication, divis

time, desi&nin& these circuits is the same

decoders(

In the ne0t 'ew %a&es we will see 'ew o' t

Adder/


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)dders are the basic buildin& bloc"s o' al

binar! numbers and &ive out sum and carr

t!%es o' adders(

@al' )dder(

ull )dder(

8al2 Adder

)ddin& two sin&lebit binar! values , Y


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9 = ;Y;> + Y;>; + ;Y>;

9 = Y >

.map-CARR,

+ Y>

6ull Adder u/in4 AND-OR

*he below im%lementation shows im%lem

&ates, instead o' usin& C &ates( *he ba

above ma%(

Circuit-SUM


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Circuit-CARR,

6ull Adder u/in4 AND-OR

Circuit-SUM

Circuit-CARR,


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n-!it Carry Ripple Adder

)n nbit adder used to add two nbit binar! numbers can be built b! conne

adder re%resents a bit %osition 'rom $ to n#8(

/ach carr! out


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Lar4er Adder

/0am%le: #6bit adder usin& 4 4bit adders( )dds two #6bit in%uts bits%roducin& a #6bit 9um 9 bits 9$ to 9#58 and a carr! out


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calculates all the carr! bits involved( Cnce these bits are available to the r

threebit addition i+Yi+carr!ini8 is im%lemented b! a sim%le in%ut

carr! &enerator involves two Boolean 'unctions named Generate and Ero%

'unctions are de'ined as:

Gi = i( Yi

Ei = i+ Yi

*he carr! bit couti8 &enerated when addin& two bits i and Yi is ;#; i' the

'unction Gi is ;#; or i' the couti#8=;#; and the 'unction Ei = ;#; simultane

case, the carr! bit is activated b! the local conditions the values o' i andthe carr! bit is received 'rom the less si&ni'icant elementar! addition and

to the more si&ni'icant elementar! addition( *here'ore, the carr!Hout bit c

o' bits i and Yi is calculated accordin& to the equation:

carr!Houti8 = Gi + Ei(carr!Hini#8

or a 'ourbit adder the carr!outs are calculated as 'ollows

carr!Hout$ = G$+ E$( carr!Hin$

carr!Hout# = G#+ E#( carr!Hout$= G#+ E#G$+ E#E$( carr!Hin$

carr!Hout2 = G2+ E2G#+ E2E#G$+ E2E#E$( carr!Hin$

carr!Hout = G+ EG2+ EE2G#+ EE2E#G$+ EE2E#( carr!Hin$

*he set o' equations above are im%lemented b! the circuit below and a com

&enerator is ne0t( *he in%ut si&nals need to %ro%a&ate throu&h a ma0imum

o%%osed to - and #2 lo&ic &ates in its counter%arts illustrated earlier(


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9ums can be calculated 'rom the 'ollowin& equations, where carr!Hout is t

above circuit(

sumHout$= $ Y$ carr!Hout$

sumHout#= # Y# carr!Hout#

sumHout2= 2 Y2 carr!Hout2

sumHout= Y carr!Hout

BCD Adder

B


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not a valid B


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rom the above table we can draw the ma% as shown below 'or Fdi

e0%ression 'or the di''erence and Borrow can be written(

rom the equation we can draw the hal'subtracter as shown in the 'i

6ull Su!tracter

) 'ull subtracter is a combinational circuit that %er'orms subtraction

subtrahend, and borrowin( *he lo&ic s!mbol and truth table are show

Sym!ol


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Trut Ta!le

3 , Bin D

$ $ $ $

$ $ # #

$ # $ #$ # # $

# $ $ #

# $ # $

# # $ $

# # # #

rom above table we can draw the ma% as shown below 'or Fdi''er

e0%ression 'or di''erence and borrow can be written(

D = ;Y;Bin + ;YBin; + Y;Bin; + YBin

= ;Y; + Y8Bin + ;Y + Y;8Bin;

= Y8;Bin + Y8Bin;

= Y Bin

Bout = ;(Y + ;(Bin + Y(Bin


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rom the equation we can draw the hal'subtracter as shown in 'i&ur

rom the above e0%ression, we can draw the circuit below( I' !ou loo

subtracter circuit is more or less same as a 'ulladder with sli&ht mod

arallel Binary Su!tracter

Earallel binar! subtracter can be im%lemented b! cascadin& several '

associated %roblems are those o' a %arallel binar! adder, seen be'ore

Below is the bloc" level re%resentation o' a 4bit %arallel binar! subt

YY2Y#Y$ 'rom 4bit 2#$( It has 4bit di''erence out%ut D


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Serial Binary Su!tracter

) serial subtracter can be obtained b! convertin& the serial adder usi

subtrahend is stored in the Y re&ister and must be 2;s com%lemented

in the re&ister(

*he circuit 'or a 4bit serial subtracter usin& 'ulladder is shown in th

Comparator/


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)1D &ate as bit #(

I' the least si&ni'icant bits o' the constant are all ;#; then the corres%oincluded in the hardware im%lementation( )ll other relations between

equivalent ones that use the o%erator ;; and the 1C* lo&ic o%erator

Initial relation/ip to !e te/ted E0ui1alent rel

Klt?< 1C*


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Static Random Acce// Memory @SRAM

) sin&le 9) memor! cell is shown in i&( 5( *wo 1C9 and two EC9 transistors #to 48 'orms

the sim%le latch to store the data and two %ass 1C9 transistors 5and 68 are controlled b! 3ord ine

to %ass Bit ine and into the cell(

) >rite o%eration is %er'ormed b! 'irst char&in& the Bit ine and with values that are desired to

be stored in the memor! cell( 9ettin& the 3ord ine hi&h %er'orms the actual write o%eration, and the new

data is latched into the circuit(

) Read o%eration is initiated b! %rechar&in& both Bit ine and to lo&ic #(

3ord ine is set hi&h to close 1C9 %ass transistors to %ut the contents stored in the cell on the Bit ine

and (

*ransistors #to 4constitute the latch and are constantl! to&&lin& bac" and 'orth( Durin& these switchin&the %ower consum%tion in


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NON-?OLATILE MEMORIES

Based on the %ro&rammabilit! o' the devices nonvolatile memories are cate&oriAed as 'ollows( 3ritin& data

into Cs is %ossible onl! at the time o' manu'acturin& the devices and used onl! 'or readin& the data

stored( /ven thou&h these devices are less in cost the constraint that the! are to be %ro&rammed at the time

o' manu'acturin& is an inconvenience( EC devices are one time %ro&rammable C( )t the time o'

device manu'acturin& ever! cell is stored with F#F and can be %ro&rammed b! customer once( But, sin&lewrite %hase ma"es them unattractive( or instance, a sin&le error in the %ro&rammin& %rocess or a%%lication

ma"es the device unusable(

/EC is /rasable EC( ulti%le times %ro&rammin& 'eature is added in /EC( In this case, 'irstwhole memor! is to be erased b! shinin& ultraviolet li&ht( *he erase %rocess is slow and can ta"e 'rom

seconds to several minutes, de%endin& on the intensit! o' the P source( Ero&rammin& ta"es several 5#$8

Mword( /EC cell is e0tremel! sim%le and dense, ma"in& it %ossible to 'abricate lar&e memories at a

low cost( /ECs were there'ore attractive in a%%lications that not require 'requent %ro&rammin&(/lectricall!/rasable EC //EC8 can be erased without removin& 'rom board, unli"e in P erasable

where memor! must be removed 'rom the board( *he volta&e a%%ro0imatel! a%%lied 'or %ro&rammin& is

#-P( In addition, it is a reverse %rocess? means b! a%%l!in& hi&h ne&ative volta&e at &ate can erase the cell()nother advanta&e over /EC is that //EC can be %ro&rammed 'or #$5c!cles( <

unit ii and iii comb ckt

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