touch i/o flash mcu - 首頁 - holtek€¦ · rev. 1.71 6 april 11, 2017 rev. 1.71 7 april 11, 2017...

Touch I/O Flash MCU

BS83A02A-4/BS83A04A-3/BS83A04A-4

Revision: V1.71 Date: April 11, 2017

Rev. 1.71 2 April 11, 2017 Rev. 1.71 3 April 11, 2017

BS83A02A-4/BS83A04A-3/BS83A04A-4Touch I/O Flash MCU


Table of Contents

Features ............................................................................................................ 5CPU Features ......................................................................................................................... 5Peripheral Features ................................................................................................................. 5

General Description ........................................................................................ 6Selection Table ................................................................................................. 6Block Diagram .................................................................................................. 7Pin Assignment ................................................................................................ 7Pin Description ................................................................................................ 8Absolute Maximum Ratings ............................................................................ 9D.C. Characteristics ....................................................................................... 10A.C. Characteristics ........................................................................................11Power-on Reset Characteristics ....................................................................11System Architecture ...................................................................................... 12

Clocking and Pipelining ......................................................................................................... 12Program Counter – PC .......................................................................................................... 13Stack ..................................................................................................................................... 14Arithmetic and Logic Unit – ALU ........................................................................................... 14

Flash Progam Memory .................................................................................. 15Structure ................................................................................................................................ 15Special Vectors ..................................................................................................................... 15Look-up Table ........................................................................................................................ 15Table Program Example ........................................................................................................ 16In Circuit Programming ......................................................................................................... 17On-chip Debug Support – OCDS .......................................................................................... 18

RAM Data Memory ......................................................................................... 19Structure ................................................................................................................................ 19

Special Function Register ............................................................................. 21Indirect Addressing Registers – IAR0, IAR1 ......................................................................... 21Memory Pointers – MP0, MP1 .............................................................................................. 21Accumulator – ACC ............................................................................................................... 22Program Counter Low Register – PCL .................................................................................. 22Look-up Table Registers – TBLP, TBHP, TBLH ..................................................................... 22Status Register – STATUS .................................................................................................... 22Systen Control Register – CTRL ........................................................................................... 24

Oscillators ...................................................................................................... 25Oscillator Overview ............................................................................................................... 25System Clock Configuratios .................................................................................................. 25Internal RC Oscillator – HIRC ............................................................................................... 25Internal 32kHZ Oscillator – LIRC .......................................................................................... 25




Operating Modes and System Clocks ......................................................... 26System Clocks ...................................................................................................................... 26Control Register .................................................................................................................... 27System Operation Modes ...................................................................................................... 28Operating Mode Switching .................................................................................................... 29Standby Current Considerations ........................................................................................... 32Wake-up ................................................................................................................................ 33Programming Considerations ................................................................................................ 33

Watchdog Timer ............................................................................................. 34Watchdog Timer Clock Source .............................................................................................. 34Watchdog Timer Control Register ......................................................................................... 34Watchdog Timer Operation ................................................................................................... 35

Reset and Initialisation .................................................................................. 36Reset Functions .................................................................................................................... 36Reset Initial Conditions ......................................................................................................... 38

Input/Output Ports ......................................................................................... 40Pull-high Resistors ................................................................................................................ 40Port A Wake-up ..................................................................................................................... 41I/O Port Control Registers ..................................................................................................... 41I/O Pin Structures .................................................................................................................. 42Programming Considerations ................................................................................................ 42

Timer/Event Counter ..................................................................................... 43Configuring the Timer/Event Counter Input Clock Source .................................................... 43Timer Register – TMR ........................................................................................................... 43Timer Control Register – TMRC ............................................................................................ 44Timer/Event Counter Operation ........................................................................................... 44Prescaler ............................................................................................................................... 45Programming Consideration ................................................................................................. 45

Touch Key Function ...................................................................................... 46Touch Key Structure .............................................................................................................. 46Touch Key Register Definition ............................................................................................... 46Touch Key Operation ............................................................................................................. 51Touch Key Interrupt ............................................................................................................... 53Programming Considerations ................................................................................................ 53

Interrupts ........................................................................................................ 54Interrupt Registers ................................................................................................................. 54Interrupt Operation ................................................................................................................ 56External Interrupt ................................................................................................................... 57Touch Key Interrupt ............................................................................................................... 57Timer/Event Counter Interrupt ............................................................................................... 57Time Base Interrupt ............................................................................................................... 57Interrupt Wake-up Function ................................................................................................... 58Programming Considerations ................................................................................................ 59




Application Circuits ....................................................................................... 60Instruction Set ................................................................................................ 62

Introduction ........................................................................................................................... 62Instruction Timing .................................................................................................................. 62Moving and Transferring Data ............................................................................................... 62Arithmetic Operations ............................................................................................................ 62Logical and Rotate Operation ............................................................................................... 63Branches and Control Transfer ............................................................................................. 63Bit Operations ....................................................................................................................... 63Table Read Operations ......................................................................................................... 63Other Operations ................................................................................................................... 63

Instruction Set Summary .............................................................................. 64Table Conventions ................................................................................................................. 64

Instruction Definition ..................................................................................... 66Package Information ..................................................................................... 75

6-pin DFN (2mm×2mm) Outline Dimensions ........................................................................ 766-pn SOT23-6 Outline Dimensions ....................................................................................... 778-pin SOP (150mil) Outline Dimensions ............................................................................... 7810-pin MSOP Outline Dimensions ........................................................................................ 7916-pin NSOP (150mil) Outline Dimensions ........................................................................... 80




Features

CPU Features• Operatingvoltage:

♦ fSYS=8MHz:2.7V~5.5V(BS83A04A-3)♦ fSYS=8MHz:2.2V~5.5V(BS83A02A-4/BS83A04A-4)

• Upto0.5μsinstructioncyclewith8MHzsystemclockatVDD=5V

• Powerdownandwake-upfunctionstoreducepowerconsumption

• Fullyintegratedlowandhighspeedinternaloscillators♦ LowSpeed--32kHz♦ Highspeed--8MHz

• Multi-modeoperation:NORMAL,SLOW,IDLEandSLEEP

• Fullyintegratedinternal8MHzoscillatorrequiresnoexternalcomponents

• Allinstructionsexecutedinoneortwoinstructioncycles

• Tablereadinstruction

• 63powerfulinstructions

• 4-levelsubroutinenesting

• Bitmanipulationinstruction

Peripheral Features• FlashProgramMemory:1K×16

• RAMDataMemory:96×8

• WatchdogTimerfunction

• Upto8bidirectionalI/Olines

• OneexternalinterruptpinsharedwithI/Opin

• Single8-bitprogrammableTimer/EventCounter

• SingleTime-Basefunctionforgenerationoffixedtimeinterruptsignals

• Lowvoltageresetfunction

• Upto4touchkeyfunctions

• Packagetypes:6-pinDFN,SOT23-6,8-pinSOPand10-pinMSOP




General Description This series of devicesare FlashMemory type 8-bit high performanceRISC architecturemicrocontrollerswithfully integrated touchkeyfunction.With the touchkeyfunctionprovidedinternallyandwiththeconvenienceofFlashMemorymulti-programmingfeatures, thesedeviceshaveall thefeatures toofferdesignersareliableandeasymeansof implementingTouchKeyeswithintheirproductsapplications.

The touchkeyfunction is integratedcompletelyeliminating theneedforexternalcomponents.Inadditiontotheflashprogrammemory,othermemoryincludesanareaofRAMDataMemory.ProtectivefeaturessuchasaninternalWatchdogTimerandLowVoltageResetfunctionscoupledwithexcellentnoiseimmunityandESDprotectionensurethatreliableoperationismaintainedinhostileelectricalenvironments.

Thedevices include fully integrated lowandhighspeedoscillatorswhich requirenoexternalcomponentsfortheirimplementation.Theabilitytooperateandswitchdynamicallybetweenarangeofoperatingmodesusingdifferentclocksourcesgivesuserstheabilitytooptimisemicrocontrolleroperationandminimisepowerconsumption.Easycommunicationwith theoutsideworld isprovidedusingtheinclusionofflexibleI/Oprogrammingfeatures,Timer/EventCountersandmanyotherfeaturesfurtherenhancedevicefunctionalityandflexibility.

These touchkeydeviceswill findexcellentuse inahugerangeofmodernTouchKeyproductapplicationssuchasinstrumentation,householdappliances,electronicallycontrolledtoolstonamebutafew.

Selection TableMostfeaturesarecommontoalldevices, themaindistinguishingfeatureis theoperatingvoltagerange,I/Ocount,TouchKeycount,LVRvalueandpackagetype.Thefollowingtablesummarisesthemainfeaturesofeachdevice.

Part No. InternalClock VDD

SystemClock

ProgramMemory

DataMemory I/O 8-bit

TimerTouchKey LVR Stack Package Marking

BS83A02A-4

8MHz

2.2V~ 5.5V

8MHz 1K×16 96×8

4

1

2 2.10V

4

6DFN SOT23-6

8SOP

BS83A02A-4A2A4 (for 6DFN)02A-4 (for SOT23-6)BS83A02A-4 (for 8SOP)

BS83A04A-3 2.7V~ 5.5V

8 4

2.55V8SOP

10MSOP

BS83A04A-383A04A-3 (for 8SOP)8304A-3 (for 10MSOP)

BS83A04A-4 2.2V~ 5.5V 2.10V

BS83A04A-483A04A-4 (for 8SOP)8304A-4 (for 10MSOP)




Block Diagram

8-bitRISCMCUCore

Flash Program Memory

Flash Programming

Circuitry

TimeBase

Low Voltage Reset

InterruptController

InternalHigh SpeedOscillator

8-bitTimer

WatchdogTimer

InternalLow SpeedOscillator

RAMData

Memory

TouchKeysI/O

Pin Assignment

BS83A02A-46 DFN-A

VDDPA2/ICPCK

PA0/INT/ICPDA

VSSPA3/KEY2PA1/KEY1

123

654

Top View

SOT23-6

02A-4

6 5 4

321

VDD

VSS

PA

0/IN

T/IC

PDA

PA2/

ICP

CK

PA1/

KEY

1

PA3/

KEY

2

BS83A04A-3/BS83A04A-48 SOP-A

PA5/KEY1PA1/KEY2PA3/KEY3PA4/KEY4

PA2/ICPCK

VDDVSS

PA0/INT/ICPDA

1234

8765

BS83A04A-3/BS83A04A-410 MSOP-A


PA2/ICPCKVSS

PA0/INT/ICPDA

109876

12345

VDD

PA6PA7

BS83A02A-48 SOP-A

PA0/INT0/ICPDAPA2/ICPCKPA3/KEY2PA1/KEY1

VDDVSSNCNC

1234

8765




BS83AV02A16 NSOP-A

VDD

PA0/INT/ICPDA

OCDSDANC

OCDSCK

PA2/ICPCK

PA3/KEY2PA1/KEY1

NC

161514131211109

12345678

VSS

NCNCNC

NCNCNC

BS83V04A16 NSOP-A

NCVDD


OCDSDANC

OCDSCK

PA2/ICPCK

NCVSS

PA7

PA0/INT/ICPDAPA6

NC

161514131211109

12345678

Note:The16NSOPpackagetypeisonlyforOCDSEVchips.

Pin DescriptionThefunctionofeachpinislistedinthefollowingtable,howeverthedetailsofeachpiniscontainedinothersectionsofthedatasheet.

AsthePinDescriptiontableshowsthesituationforthepackagewiththemostpins,notallpinsinthetablewillbeavailableonsmallerpackagesizes.

BS83A02A-4

Pin Name Function OPT I/T O/T Description

PA0/INT/ICPDA

PA0 PAWUPAPU ST CMOS General purpose I/O. Register enabled pull-up and

wake-up.INT INTEG ST — External interrupt

ICPDA — ST CMOS In-circuit programming data/address pin

PA1/KEY1PA1 PAWU

PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up.

KEY1 TKM0C1 NSI — Touch key input

PA2/ICPCKPA2 PAWU


ICPCK — ST — In-circuit programming clock pin

PA3/KEY2PA3 PAWU


KEY2 TKM0C1 NSI — Touch key inputOCDSCK OCDSCK — ST — On-chip debug clock pin, for EV chip only OCDSDA OCDSDA — ST CMOS On-chip debug data/address pin, for EV chip onlyVDD VDD — PWR — Power voltageVSS VSS — PWR — Ground

Legend:I/T:Inputtype; O/T:Outputtype OPT:Optionalbyregisterselection PWR:Power; ST:SchmittTriggerinput CMOS:CMOSoutput NSI:Non-standardinput




BS83A04A-3/BS83A04A-4

Pin Name Function OPT I/T O/T Description

PA0/INT/ICPDA

PA0 PAWUPAPU ST CMOS General purpose I/O. Register enabled pull-up and

wake-up.INT INTEG ST — External interrupt

ICPDA — ST CMOS In-circuit programming data/address pin

PA1/KEY2PA1 PAWU



PA2/ICPCKPA2 PAWU


ICPCK — ST — In-circuit programming clock pin

PA3/KEY3PA3 PAWU



PA4/KEY4PA4 PAWU



PA5/KEY1PA5 PAWU



PA6 PA6 PAWUPAPU ST CMOS General purpose I/O. Register enabled pull-up and

wake-up.

PA7 PA7 PAWUPAPU ST CMOS General purpose I/O. Register enabled pull-up and

wake-up.OCDSCK OCDSCK — ST — On-chip debug clock pin, for EV chip only OCDSDA OCDSDA — ST CMOS On-chip debug data/address pin, for EV chip onlyVDD VDD — PWR — Power voltageVSS VSS — PWR — Ground

Legend:I/T:Inputtype; O/T:Outputtype OPT:Optionalbyregisterselection PWR:Power; ST:SchmittTriggerinput CMOS:CMOSoutput NSI:Non-standardinput For the8-pinpackage type, theI/OpinPA7isnotbonded toanexternalpinbut internallybondedtogetherwithPA4,so it is recommended that thePA7shouldbeconfiguredas inputwithpull-highresistordisabled.

Absolute Maximum RatingsSupplyVoltage................................................................................................VSS−0.3VtoVSS+6.0VInputVoltage..................................................................................................VSS−0.3VtoVDD+0.3VStorageTemperature....................................................................................................-50˚Cto125˚COperatingTemperature..................................................................................................-40˚Cto85˚CIOLTotal..................................................................................................................................... 80mAIOHTotal....................................................................................................................................-80mATotalPowerDissipation......................................................................................................... 500mW

Note:Thesearestressratingsonly.Stressesexceeding therangespecifiedunder"AbsoluteMaximumRatings"maycausesubstantialdamagetothesedevices.Functionaloperationofthesedevicesatotherconditionsbeyondthoselistedinthespecificationisnotimpliedandprolongedexposuretoextremeconditionsmayaffectdevicesreliability.




D.C. CharacteristicsTa = 25°C

Symbol ParameterTest Conditions

Min. Typ. Max. UnitVDD Conditions

VDD

Operating Voltage (HIRC)(BS83A04A-3) — fSYS = 8MHz 2.7 — 5.5 V

Operating Voltage (HIRC)(BS83A02A-4/BS83A04A-4) — fSYS = 8MHz 2.2 — 5.5 V

IDD

Operating Current (HIRC)(fSYS=fH, fS=fSUB= fLIRC)

3V No load, fH = 8MHz,WDT enable

— 0.8 1.5 mA5V — 1.5 3.0 mA

Operating Current (LIRC)(fSYS=fL=fLIRC, fS=fSUB= fLIRC)

3V No load, WDT enable,LVR disable

— 10 20 μA

5V — 20 35 μA

ISTB

IDLE Mode Stanby Current (HIRC)(fSYS=off, fS=fSUB=fLIRC)

3V No load, WDT enable,fSYS = 8MHz

— 1.5 3.0 μA

5V — 2.5 5.0 μA

IDLE Mode Stanby Current (LIRC)(fSYS=off, fS=fSUB=fLIRC)

3V No load, WDT enable,fSYS = 32KHz

— 1.5 3.0 μA

5V — 2.5 5.0 μA

VILInput Low Voltage for I/O Ports orInput Pins

5V—

0 — 1.5 V

— 0 — 0.2VDD V

VIHInput High Voltage for I/O Ports or Input Pins

5V—

3.5 — 5.0 V

— 0.8VDD — VDD V

VLVR

Low Voltage Reset Voltage(BS83A04A-3) — LVR enable, VLVR =2.55V -5% 2.55 +5% V

Low Voltage Reset Voltage(BS83A02A-4/BS83A04A-4) — LVR enable, VLVR =2.10V -5% 2.10 +5% V

ILVRAdditional Power Consumption if LVR is used

3VLVR disble→LVR enable

— 15 25 μA

5V — 20 30 μA

IOL

I/O Ports Sink Current(BS83A02A-4)

3V VOL=0.1VDD 8 16 — mA

5V VOL=0.1VDD 16 32 — mA

I/O Ports Sink Current(BS83A04A-3/BS83A04A-4)

3V VOL=0.1VDD 4 8 — mA

5V VOL=0.1VDD 10 20 — mA

IOH

I/O Ports Source Current(BS83A02A-4)

3V VOH = 0.9VDD -3.75 -7.5 — mA

5V VOH = 0.9VDD -7.5 -15 — mA

I/O Ports Source Current(BS83A04A-3/BS83A04A-4)

3V VOH = 0.9VDD -2 -4 — mA

5V VOH = 0.9VDD -5 -10 — mA

RPH Pull-high Resistance for I/O Ports3V — 20 60 100 kΩ

5V — 10 30 50 kΩ




A.C. CharacteristicsTa=25°C



fSYS

Operating Clock(BS83A04A-3) — 2.7V ~ 5.5V DC — 8 MHz

Operating Clock(BS83A02A-4/BS83A04A-4) — 2.2V ~ 5.5V DC — 8 MHz

fHIRC System Clock (HIRC) 3V/5V Ta=25°C -2% 8 +2% MHz

fLIRC System clock (LIRC)5V — -10% 32 +10% kHz

2.2V~5.5V Ta=-40°C ~85°C -50% 32 +60% kHz

tINT Interrupt pulse width — — 10 — — μs

tLVR Low Voltage Width to Reset — — 120 240 480 μs

tSSTSystem start-up timer period (wake-up from HALT) —

fSYS=HIRC — 1024 1025tSYS

fSYS=LIRC — 1~2 3

Note:1.tSYS=1/fSYS

2.TomaintaintheaccuracyoftheinternalHIRCoscillatorfrequency,a0.1μFdecouplingcapacitorshouldbeconnectedbetweenVDDandVSSandlocatedasclosetothedeviceaspossible.

Power-on Reset CharacteristicsTa=25°C



VPOR VDD Start Voltage — — — — 100 mV

RRVDD VDD Raising Rate — — 0.035 — — V/ms

tPORMinimum Time for VDD Stays at VPOR to Ensure Power-on Reset — — 1 — — ms

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System ArchitectureAkeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributedtotheirinternalsystemarchitecture.TherangeofdevicestakeadvantageoftheusualfeaturesfoundwithinRISCmicrocontrollersprovidingincreasedspeedofoperationandenhancedperformance.Thepipeliningscheme is implemented insuchaway that instruction fetchingand instructionexecutionareoverlapped,hence instructionsareeffectivelyexecuted inonecycle,with theexceptionofbranchorcallinstructions.An8-bitwideALUisusedinpracticallyallinstructionsetoperations,whichcarriesoutarithmeticoperations,logicoperations,rotation,increment,decrement,branchdecisions,etc.TheinternaldatapathissimplifiedbymovingdatathroughtheAccumulatorandtheALU.CertaininternalregistersareimplementedintheDataMemoryandcanbedirectlyor indirectlyaddressed.Thesimpleaddressingmethodsof theseregistersalongwithadditionalarchitectural featuresensure thataminimumofexternalcomponents is required toprovideafunctionalI/Owithmaximumreliabilityandflexibility.Thismakesthedevicesuitableforlow-cost,high-volumeproductionforcontrollerapplications.

Clocking and PipeliningThemiansystemclock,derivedfromHIRCorLIRCoscillator issubdividedintofourinternallygeneratednon-overlappingclocks,T1~T4.TheProgramCounter is incrementedat thebeginningoftheT1clockduringwhichtimeanewinstructionisfetched.TheremainingT2~T4clockscarryoutthedecodingandexecutionfunctions.Inthisway,oneT1~T4clockcycleformsoneinstructioncycle.Althoughthefetchingandexecutionof instructionstakesplaceinconsecutiveinstructioncycles, thepipeliningstructureof themicrocontrollerensures that instructionsareeffectivelyexecutedinoneinstructioncycle.TheexceptiontothisareinstructionswherethecontentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhichcasetheinstructionwilltakeonemoreinstructioncycletoexecute.

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System Clocking and Pipelining

Forinstructionsinvolvingbranches,suchas jumporcall instructions, twoinstructioncyclesarerequired tocomplete instructionexecution.Anextracycle is requiredas theprogramtakesonecycletofirstlyobtaintheactualjumporcalladdressandthenanothercycletoactuallyexecutethebranch.Therequirementforthisextracycleshouldbetakenintoaccountbyprogrammersintimingsensitiveapplications.




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Instruction Fetching

Program Counter – PCDuringprogramexecution, theProgramCounter isused tokeep trackof theaddressof thenext instruction tobeexecuted. It isautomatically incrementedbyoneeach timean instructionisexecutedexcept for instructions, suchas"JMP"or"CALL" thatdemanda jump toanon-consecutiveProgramMemoryaddress.Itmustbenotedthatonlythelower8bits,knownastheProgramCounterLowRegister,aredirectlyaddressablebyuser.

Whenexecuting instructions requiring jumping tonon-consecutiveaddressessuchasa jumpinstruction,asubroutinecall, interruptorreset,etc, themicrocontrollermanagesprogramcontrolbyloadingtherequiredaddressintotheProgramCounter.Forconditionalskipinstructions,oncetheconditionhasbeenmet,thenextinstruction,whichhasalreadybeenfetchedduringthepresentinstructionexecution,isdiscardedandadummycycletakesitsplacewhilethecorrectinstructionisobtained.

Program CounterHigh Byte of Program Low Byte of Program

PC9~ PC8 PCL7~ PCL0

Thelowerbyteof theProgramCounter,knownastheProgramCounterLowregisterorPCL,isavailableforprogramcontrolandisareadableandwriteableregister.Bytransferringdatadirectlyintothisregister,ashortprogramjumpcanbeexecuteddirectly.However,asonlythis lowbyteisavailableformanipulation, the jumpsare limited in thepresentpageofmemory,whichhave256locations.Whensuchprogramjumpsareexecuteditshouldalsobenotedthatadummycyclewillbeinserted.ThelowerbyteoftheProgramCounterisfullyaccessibleunderprogramcontrol.ManipulatingthePCLmightcauseprogrambranching,soanextracycleisneededtopre-fetch.




StackThis isaspecialpartof thememorywhichisusedtosavethecontentsof theProgramCounteronly.Thestackisorganizedinto4levelsandneitherpartofthedatanorpartoftheprogramspace,andisneitherreadablenorwriteable.Theactivatedlevel is indexedbytheStackPointer,andisneitherreadablenorwriteable.Atasubroutinecallorinterruptacknowledgesignal,thecontentsoftheProgramCounterarepushedontothestack.Attheendofasubroutineoraninterruptroutine,signaledbyareturninstruction,RETorRETI,theProgramCounterisrestoredtoitspreviousvaluefromthestack.Afteradevicereset,theStackPointerwillpointtothetopofthestack.

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Ifthestackisfullandanenabledinterrupttakesplace,theinterruptrequestflagwillberecordedbuttheacknowledgesignalwillbeinhibited.WhentheStackPointer isdecremented,byRETorRETI,theinterruptwillbeserviced.Thisfeaturepreventsstackoverflowallowingtheprogrammertousethestructuremoreeasily.However,whenthestackisfull,aCALLsubroutineinstructioncanstillbeexecutedwhichwillresult inastackoverflow.Precautionsshouldbetakentoavoidsuchcaseswhichmightcauseunpredictableprogrambranching.Ifthestackisoverflow,thefirstProgramCountersaveinthestackwillbelost.

Arithmetic and Logic Unit – ALUThearithmetic-logicunitorALUisacriticalareaofthemicrocontrollerthatcarriesoutarithmeticandlogicoperationsoftheinstructionset.Connectedtothemainmicrocontrollerdatabus,theALUreceivesrelatedinstructioncodesandperformstherequiredarithmeticor logicaloperationsafterwhichtheresultwillbeplacedinthespecifiedregister.AstheseALUcalculationoroperationsmayresultincarry,borroworotherstatuschanges,thestatusregisterwillbecorrespondinglyupdatedtoreflectthesechanges.TheALUsupportsthefollowingfunctions:

• Arithmeticoperations:ADD,ADDM,ADC,ADCM,SUB,SUBM,SBC,SBCM,DAA

• Logicoperations:AND,OR,XOR,ANDM,ORM,XORM,CPL,CPLA

• Rotation:RRA,RR,RRCA,RRC,RLA,RL,RLCA,RLC

• IncrementandDecrement:INCA,INC,DECA,DEC

• Branchdecision:JMP,SZ,SZA,SNZ,SIZ,SDZ,SIZA,SDZA,CALL,RET,RETI.




Flash Progam MemoryTheProgramMemoryisthelocationwheretheusercodeorprogramisstored.ForthisdevicetheProgrammMemoryisFlashtype,whichmeansitcanbeprogrammedandre-programmedalargenumberoftimes,allowingtheusertheconvenienceofcodemodificationonthesamedevice.Byusingtheappropriateprogrammingtools,thisFlashdeviceoffersuserstheflexibilitytodebuganddeveloptheirapplicationswhilealsoofferingameansoffieldprogrammingandupdating.

StructureTheProgramMemoryhasacapacityof1K×16bits.TheProgramMemoryisaddressedby theProgramCounterandalsocontainsdata,tableinformationandinterruptentriesinformation.Tabledata,whichcanbesetupinanylocationwithintheProgramMemory,isaddressedbyseparatetablepointerregister.

000H Reset

004H

16 bits

Interrupt Vectors

014H

3FFH

Program Memory Structure

Special VectorsWithintheProgramMemory,certainlocationsarereervedfortheresetandinterrupts.Thelocation000His reserved foruseby thedevice reset forprograminitialisation.Afteradevice reset isinitiated,theprogramwilljumptothislocationandbeginexecution.

Look-up TableAnylocationwithintheProgramMemorycanbedefinedasalook-uptablewhereprogrammerscanstorefixeddata.Tousethelook-uptable,thetablepointermustfirstbesetupbyplacingtheaddressofthelookupdatatoberetrievedinthetablepointerregisters,TBLPandTBHP.Theseregistersdefinethetotaladdressofthelook-uptable.

Aftersettingupthetablepointer,thetabledatacanberetrievedfromtheProgramMemoryusingthe"TABRD[m]"or"TABRDL[m]"instructions,respectively.Whentheinstructionisexecuted,the lowerorder tablebyte from theProgramMemorywillbe transferred to theuserdefinedDataMemoryregister[m]asspecified in the instruction.Thehigherorder tabledatabytefromtheProgramMemorywillbe transferred to theTBLHspecial register.Anyunusedbits in thistransferredhigherorderbytewillbereadas"0".

Theaccompanyingdiagramillustratestheaddressingdataflowofthelook-uptable.

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InstructionTable Location Bits

b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

TABRD [m] PC9 PC8 @7 @6 @5 @4 @3 @2 @1 @0

TABRDL [m] 1 1 @7 @6 @5 @4 @3 @2 @1 @0

Table LocationNote:PC9,PC8:CurrentProgramCounterbits

@7~@0:TablePointerTBLPbits

b9~b0:Tableaddresslocationbits

Table Program ExampleTheaccompanyingexampleshowshowthetablepointerandtabledataisdefinedandretrievedfromthedevices.ThisexampleusesrawtabledatalocatedinthelastpagewhichisstoredthereusingtheORGstatement.ThevalueatthisORGstatementis"300H"whichreferstothestartaddressofthelastpagewithinthe1KProgramMemoryofthemicrocontroller.

Thetablepointerissetupheretohaveaninitialvalueof"06H".ThiswillensurethatthefirstdatareadfromthedatatablewillbeattheProgramMemoryaddress"306H"or6locationsafterthestartofthelastpage.Notethatthevalueforthetablepointerisreferencedtothefirstaddressofthelastpageifthe"TABRDL[m]"instructionisbeingused.Thehighbyteofthetabledatawhichinthiscaseisequal tozerowillbetransferredtotheTBLHregisterautomaticallywhenthe"TABRDL[m]"instructionisexecuted.

Because theTBLHregister isaread-onlyregisterandcannotberestored,careshouldbe takentoensure itsprotectionifboththemainroutineandInterruptServiceRoutineusethetablereadinstructions. Ifusing the tableread instructions, theInterruptServiceRoutinesmaychange thevalueofTBLHandsubsequentlycauseerrors ifusedagainby themainroutine.Asarule it isrecommendedthatsimultaneoususeofthetablereadinstructionsshouldbeavoided.However, insituationswheresimultaneoususecannotbeavoided,theinterruptsshouldbedisabledpriortotheexecutionofanymainroutinetable-readinstructions.Notethatalltablerelatedinstructionsrequiretwoinstructioncyclestocompletetheiroperation.




Table Read Program Exampletempreg1 db ? ; temporary register #1tempreg2 db ? ; temporary register #2 : :mov a,06h ; initialise table pointer - note that this address is referencedmov tblp, a ; to the last page : :tabrdl tempreg1 ; transfers value in table referenced by table pointer to tempreg1 ; data at program memory address "306H" transferred to ; tempreg1 and TBLHdec tblp ; reduce value of table pointer by onetabrdl tempreg2 ; transfers value in table referenced by table pointer to tempreg2 ; data at program memory address "305H" transferred to ; tempreg2 and TBLH ; in this example the data "1AH" is transferred to ; tempreg1 and data "0FH" to register tempreg2 ; the value "00H" will be transferred to the high byte ; register TBLH : :org 300h ; sets initial address of last pagedc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : :

In Circuit ProgrammingTheprovisionofFlashtypeProgramMemoryprovidestheuserwithameansofconvenientandeasyupgradesandmodificationstotheirprogramsonthesamedevice.

Asanadditionalconvenience,Holtekhasprovidedameansofprogrammingthemicrocontrollerin-circuitusinga4-pininterface.Thisprovidesmanufacturerswiththepossibilityofmanufacturingtheircircuitboardscompletewithaprogrammedorun-programmedmicrocontroller,and thenprogrammingorupgradingtheprogramatalaterstage.Thisenablesproductmanufacturerstoeasilykeeptheirmanufacturedproductssuppliedwiththelatestprogramreleaseswithoutremovalandre-insertionofthedevice.

TheHoltekFlashMCUtoWriterProgrammingPincorrespondencetableisasfollows:

Holtek WritePins MCU Programming Pins Function

ICPDA PA0 Serial Address and data – read/write

ICPCK PA2 Programming Serial Clock

VDD VDD Power Supply (5.0V)

VSS VSS Ground

Duringtheprogrammingprocess,theusermusttheretakecaretoensurethatnootheroutputsareconnectedtothesetwopins.

TheProgramMemorycanbeprogrammedserially incircuitusing this4-wire interface.Dataisdownloadedanduploadedseriallyonasinglepinwithanadditional linefor theclock.Twoadditionallinesarerequiredforthepowersupplyandonelineforthereset.Thetechnicaldetailsregardingtheincircuitprogrammingofthedevicearebeyondthescopeofthisdocumentandwillbesuppliedinsupplementaryliterature.




DuringtheprogrammingprocessthemicrocontrollertakescontrolofthePA0andPA2I/Opinsfordataandclockprogrammingpurposes.Theusermusttheretakecaretoensurethatnootheroutputsareconnectedtothesetwopins.

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Note:*mayberesistororcapacitor.Theresistanceof*mustbegreaterthan1korthecapacitanceof*mustbelessthan1nF.

On-chip Debug Support – OCDSAnEVchipexistsforthepurposesofdeviceemulation.ThisEVchipdevicealsoprovidesan"On-ChipDebug"functiontodebugthedeviceduringthedevelopmentprocess.TheEVchipandtheactualMCUdevicesarealmostfunctionallycompatibleexceptforthe"On-ChipDebug"function.Userscanuse theEVchipdevice toemulate the realchipdevicebehaviorbyconnecting theOCDSDAandOCDSCKpinstotheHoltekHT-IDEdevelopmenttools.TheOCDSDApinistheOCDSData/Addressinput/outputpinwhiletheOCDSCKpinistheOCDSclockinputpin.Whenusersuse theEVchipfordebugging,other functionswhicharesharedwith theOCDSDAandOCDSCKpinsintheactualMCUdevicewillhavenoeffectintheEVchip.ForamoredetailedOCDSdescription, refer to thecorrespondingdocumentnamed"Holteke-Linkfor8-bitMCUOCDSUser’sGuide".

Holtek e-Link Pins EV Chip Pins Pin DescriptionOCDSDA OCDSDA On-chip Debug Support Data/Address input/outputOCDSCK OCDSCK On-chip Debug Support Clock input

VDD VDD Power SupplyGND VSS Ground




RAM Data MemoryTheDataMemoryisan8-bitwideRAMinternalmemoryandis the locationwhere temporaryinformationisstored.

StructureDividedintotwosections,thefirstoftheseisanareaofRAM,knownastheSpecialFunctionDataMemory.Herearelocatedregisterswhicharenecessaryforcorrectoperationofthedevice.Manyoftheseregisterscanbereadfromandwrittentodirectlyunderprogramcontrol,however,someremainprotectedfromusermanipulation.

ThesecondareaofDataMemoryisknownastheGeneralPurposeDataMemory,whichisreservedforgeneralpurposeuse.Alllocationswithinthisareaarereadandwriteaccessibleunderprogramcontrol.

ThestartaddressoftheoverallDataMemoryistheaddress00H.

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Data Memory




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Special Purpose Data Memory

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General Purpose Data Memory




Special Function RegisterMostoftheSpecialFunctionRegisterdetailswillbedescribedintherelevantfunctionalsection.Howeverseveralregistersrequireaseparatedescriptioninthissection.

Indirect Addressing Registers – IAR0, IAR1TheIndirectAddressingRegisters,IAR0andIAR1,althoughhavingtheirlocationsinnormalRAMregister,donotactuallyphysicallyexistasnormalregisters.Themethodof indirectaddressingforRAMdatamanipulationisusingtheseIndirectAddressingRegistersandMemoryPointers,incontrasttodirectmemoryaddressing,wheretheactualmemoryaddressisspecified.ActionsontheIAR0andIAR1registerswillresultinnoactualreadorwriteoperationtotheseregistersbutrathertothememorylocationspecifiedbytheircorrespondingMemoryPointers,MP0orMP1.Actingasapair,IAR0andMP0cantogetheraccessdatafromBank0whiletheIAR1andMP1registerpaircanaccessdatafromanybank.AstheIndirectAddressingRegistersarenotphysicallyimplemented,readingtheIndirectAddressingRegistersindirectlywillreturnaresultof"00H"andwritingtotheregistersdirectlywillresultinnooperation.

Memory Pointers – MP0, MP1TwoMemoryPointers, knownasMP0andMP1areprovided.TheseMemoryPointers arephysicallyimplementedintheDataMemoryandcanbemanipulatedinthesamewayasnormalregistersprovidingaconvenientwaywithwhichto indirectlyaddressandtrackdata.WhenanyoperationtotherelevantIndirectAddressingRegistersiscarriedout,theactualaddresswhichthemicrocontrollerdirects to is theaddressspecifiedbytherelatedMemoryPointer.MP0, togetherwithIndirectAddressingRegister,IAR0,areusedtoaccessdatafromBank0,whileMP1andIAR1areusedtoaccessdatafromallbanks.DirectAddressingcanonlybeusedwithBank0,allotherBanksmustbeaddressedindirectlyusingMP1andIAR1.Notethatforthesedevices,theMemoryPointers,MP0andMP1,areboth8-bitregistersandusedtoaccesstheDataMemorytogetherwiththeircorrespondingindirectaddressingregistersIAR0andIAR1.ThefollowingexampleshowshowtoclearasectionoffourDataMemorylocationsalreadydefinedaslocationsadres1toadres4.

Indirect Addressing Program Exampledata . section ‘data’adres1 db?adres2 db?adres3 db?adres4 db?block db? code. section at 0 codeorg 00hstart:mov a,04h ; setup size of blockmov block,amov a,offset adres1 ; Accumulator loaded with first RAM addressmov mp0,a ; setup memory pointer with first RAM addressloop: clr IAR0 ; clear the data at address defined by MP0inc mp0 ; increment memory pointersdz block ; check if last memory location has been clearedjmp loopcontinue:

Theimportantpointtonotehereisthatintheexampleshownabove,noreferenceismadetospecificDataMemoryaddresses.




Accumulator – ACCTheAccumulator iscentral to theoperationofanymicrocontrollerand isclosely relatedwithoperationscarriedoutby theALU.TheAccumulator is theplacewhereall intermediateresultsfromtheALUarestored.Without theAccumulator itwouldbenecessary towrite theresultofeachcalculationorlogicaloperationsuchasaddition,subtraction,shift,etc., totheDataMemoryresultinginhigherprogrammingandtimingoverheads.Data transferoperationsusually involvethetemporarystoragefunctionoftheAccumulator;forexample,whentransferringdatabetweenoneuser-definedregisterandanother, it isnecessary todo thisbypassing thedata throughtheAccumulatorasnodirecttransferbetweentworegistersispermitted.

Program Counter Low Register – PCLToprovideadditionalprogramcontrolfunctions, the lowbyteof theProgramCounter ismadeaccessibletoprogrammersbylocatingitwithintheSpecialPurposeareaoftheDataMemory.Bymanipulatingthisregister,directjumpstootherprogramlocationsareeasilyimplemented.LoadingavaluedirectlyintothisPCLregisterwillcauseajumptothespecifiedProgramMemorylocation,howeverastheregisterisonly8-bitwideonlyjumpswithinthecurrentProgramMemorypagearepermitted.Whensuchoperationsareused,notethatadummycyclewillbeinserted.

Look-up Table Registers – TBLP, TBHP, TBLHThesethreespecialfunctionregistersareusedtocontroloperationof thelook-uptablewhichisstoredintheProgramMemory.TBLPandTBHParethetablepointersandindicate thelocationwhere the tabledata is located.Theirvaluemustbesetupbeforeany tablereadcommandsareexecuted.Theirvaluecanbechanged,forexampleusingthe"INC"or"DEC"instructions,allowingforeasytabledatapointingandreading.TBLHisthelocationwherethehighorderbyteofthetabledataisstoredafteratablereaddatainstructionhasbeenexecuted.Notethatthelowerordertabledatabyteistransferredtoauserdefinedlocation.

Status Register – STATUSThis8-bitregistercontainsthezeroflag(Z),carryflag(C),auxiliarycarryflag(AC),overflowflag(OV),powerdownflag(PDF),andwatchdogtime-outflag(TO).Thesearithmetic/logicaloperationandsystemmanagementflagsareusedtorecordthestatusandoperationofthemicrocontroller.

WiththeexceptionoftheTOandPDFflags,bitsinthestatusregistercanbealteredbyinstructionslikemostotherregisters.AnydatawrittenintothestatusregisterwillnotchangetheTOorPDFflag.Inaddition,operationsrelatedtothestatusregistermaygivedifferentresultsduetothedifferentinstructionoperations.TheTOflagcanbeaffectedonlybyasystempower-up,aWDTtime-outorbyexecutingthe"CLRWDT"or"HALT"instruction.ThePDFflagisaffectedonlybyexecutingthe"HALT"or"CLRWDT"instructionorduringasystempower-up.




TheZ,OV,ACandCflagsgenerallyreflectthestatusofthelatestoperations.

• Cissetifanoperationresultsinacarryduringanadditionoperationorifborrowdoesnottakeplaceduringasubtractionoperation;otherwiseCiscleared.Cisalsoaffectedbyarotatethroughcarryinstruction.

• ACissetifanoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction;otherwiseACiscleared.

• Zissetiftheresultofanarithmeticorlogicaloperationiszero;otherwiseZiscleared.

• OVissetifanoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbit,orviceversa;otherwiseOViscleared.

• PDFisclearedbyasystempower-uporexecutingthe"CLRWDT"instruction.PDFissetbyexecutingthe"HALT"instruction.

• TOisclearedbyasystempower-uporexecutingthe"CLRWDT"or"HALT"instruction.TOissetbyaWDTtime-out.

Inaddition,onenteringaninterruptsequenceorexecutingasubroutinecall,thestatusregisterwillnotbepushedontothestackautomatically.Ifthecontentsofthestatusregistersareimportantandifthesubroutinecancorruptthestatusregister,precautionsmustbetakentocorrectlysaveit.Notethatbits3~0oftheSTATUSregisterarebothreadableandwriteablebits.

STATUS Register Bit 7 6 5 4 3 2 1 0

Name — — TO PDF OV Z AC CR/W — — R/W R/W R/W R/W R/W R/WPOR — — 0 0 × × × ×

"×" unknownBit7~6 Unimplemented,readas"0"Bit5 TO:WatchdogTime-Outflag

0:Afterpoweruporexecutingthe"CLRWDT"or"HALT"instruction1:Awatchdogtime-outoccurred.

Bit4 PDF:Powerdownflag0:Afterpoweruporexecutingthe"CLRWDT"instruction1:Byexecutingthe"HALT"instruction

Bit3 OV:Overflowflag0:Nooverflow1:Anoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbitorviceversa.

Bit2 Z:Zeroflag0:Theresultofanarithmeticorlogicaloperationisnotzero1:Theresultofanarithmeticorlogicaloperationiszero

Bit1 AC:Auxiliaryflag0:Noauxiliarycarry1:Anoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction

Bit0 C:Carryflag0:Nocarry-out1:Anoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation

Cisalsoaffectedbyarotatethroughcarryinstruction.




Systen Control Register – CTRL

CTRL RegisterBit 7 6 5 4 3 2 1 0

Name FSYSON — — — — LVRF LRF WRFR/W R/W — — — — R/W R/W R/WPOR 0 — — — — × 0 0

"×" unknownBit7 FSYSON:fSYScontrolinIDLEmode

0:Disable1:Enable

Bit6~3 Unimplemented,readas"0"Bit2 LVRF:LVRfunctionresetflag

0:Notactive1:Active

Thisbitcanbeclearedto"0",butcannotbesetto"1".Bit1 LRF:LVRControlregistersoftwareresetflag

0:Notactive1:Active

Thisbitcanbeclearedto"0",butcannotbesetto"1".Bit0 WRF:resetcausedbyWE[4:0]setting

0:Notactive1:Active

Thisbitcanbeclearedto"0",butcannotbesetto"1".




OscillatorsVariousoscillatoroptionsoffer theuserawide rangeof functionsaccording to theirvariousapplication requirements.The flexible featuresof theoscillator functionsensure that thebestoptimisationcanbeachievedintermsofspeedandpowersaving.

Oscillator OverviewThedevicesincludetwointernaloscillators,alowspeedoscillatorandahighspeedoscillator.BothcanbechosenastheclocksourceforthemainsystemclockhowevertheslowspeedoscillatorisalsousedasaclocksourceforotherfunctionssuchastheWatchdogTimer,TimeBaseandTimer/EventCounter.Bothoscillators requirenoexternalcomponents for their implementation.Alloscillatoroptionsareselectedusingregisters.Thehighspeedoscillatorprovideshigherperformancebutcarrieswithit thedisadvantageofhigherpowerrequirements,whiletheoppositeisofcoursetruefor the lowspeedoscillator.With thecapabilityofdynamicallyswitchingbetweenfastandslowsystemclock,thedevicehastheflexibilitytooptimisetheperformance/powerratio,afeatureespeciallyimportantinpowersensitiveportableapplications.

Type Name Freq.Internal High Speed RC HIRC 8 MHzInternal Low Speed RC LIRC 32 kHz

Oscillator Types

System Clock ConfiguratiosTherearetwosystemoscillators,onehighspeedoscillatorandonelowspeedoscillator.Thehighspeedoscillatorisafullyinternal8MHzRCoscillator.Thelowspeedoscillatorisafullyinternal32kHzRCoscillator.Selectingwhether the loworhighspeedoscillator isusedas thesystemoscillatorisimplementedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregisterandasthesystemclockcanbedynamicallyselected.

Internal RC Oscillator – HIRCTheinternalRCoscillatorisafullyintegratedsystemoscillatorrequiringnoexternalcomponents.The internalRCoscillator has a fixed frequency of 8MHz.Device trimming during themanufacturingprocessandtheinclusionofinternalfrequencycompensationcircuitisusedtoensurethattheinfluenceofthepowersupplyvoltage,temperatureandprocessvariationsontheoscillationfrequencyareminimised.

Internal 32kHZ Oscillator – LIRCTheLIRCisafullyself-containedfreerunningon-chipRCoscillatorwithatypicalfrequencyof32kHzat5V,requiringnoexternalcomponentsfor its implementation.Device trimmingduringthemanufacturingprocessandtheinclusionofinternalfrequencycompensationcircuitsareusedtoensure that the influenceof thepowersupplyvoltage, temperatureandprocessvariationsontheoscillationfrequencyareminimised.AfterpoweronthisLIRCoscillatorwillbepermanentlyenabled;thereisnoprovisiontodisabletheoscillatorusingregisterbits.




Operating Modes and System ClocksPresentdayapplicationsrequirethat theirmicrocontrollershavehighperformancebutoftenstilldemandthattheyconsumeaslittlepoweraspossible,conflictingrequirementsthatareespeciallytrueinbatterypoweredportableapplications.Thefastclocksrequiredforhighperformancewillbytheirnatureincreasecurrentconsumptionandofcourse,versa,lowerspeedclocksreducecurrentconsumption.AsHoltekhasprovidedthesedeviceswithbothhighandlowspeedclocksourcesandthemeanstoswitchbetweenthemdynamically, theusercanoptimisetheoperationof theirmicrocontrollertoachievethebestperformance/powerratio.

System ClocksThemainsystemclock,cancomefromahighfrequencyfHor lowfrequencyfSUBsource,andisselectedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregister.BoththehighandlowspeedsystemclocksaresourcedfrominternalRCoscillators.

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System Clock Configurations

Note:WhenthesystemclocksourcefSYSisswitchedtofSUBfromfH,thehighspeedoscillationwillstoptoconservethepower.ThusthereisnofH~fH/64clocksourceforusebytheperipheralcircuits.




Control RegisterAsingleregister,SMOD,isusedforoverallcontroloftheinternalclockswithinthedevices.

SMOD RegisterBit 7 6 5 4 3 2 1 0

Name CKS2 CKS1 CKS0 — LTO HTO IDLEN HLCLKR/W R/W R/W R/W — R R R/W R/WPOR 0 0 0 — 0 0 1 1

Bit7~5 CKS2 ~ CKS0:ThesystemclockselectionwhenHLCLKis"0"000:fSUB(fLIRC)001:fSUB(fLIRC)010:fH/64011:fH/32100:fH/16101:fH/8110:fH/4111:fH/2

Thesethreebitsareusedtoselectwhichclockisusedasthesystemclocksource.Inadditiontothesystemclocksource,whichcanbeLIRC,adividedversionofthehighspeedsystemoscillatorcanalsobechosenasthesystemclocksource.

Bit4 Unimplemented,readas"0"Bit3 LTO:Lowspeedsystemoscillatorreadyflag

0:Notready1:Ready

Thisisthelowspeedsystemoscillatorreadyflagwhichindicateswhenthelowspeedsystemoscillator isstableafterpoweronresetorawake-uphasoccurred.TheflagwillbelowwhenintheSLEEPModebutafterawake-uphasoccurred,theflagwillchangetoahighlevelafter1~2clockcyclesiftheLIRCoscillatorisused.

Bit2 HTO:Highspeedsystemoscillatorreadyflag0:Notready1:Ready

Thisisthehighspeedsystemoscillatorreadyflagwhichindicateswhenthehighspeedsystemoscillatorisstableafterawake-uphasoccurred.TheflagwillbelowwhenintheSLEEPorIDLE0Modebutafterpoweronresetorawake-uphasoccurred,theflagwillchangetoahighlevelafter1024clockcyclesiftheHIRCoscillatorisused.

Bit1 IDLEN:IDLEModeControl0:Disable1:Enable

This is theIDLEModeControlbitanddetermineswhathappenswhentheHALTinstructionisexecuted.If thisbit ishigh,whenaHALTinstructionisexecutedthedevicewillenter theIDLEMode. In theIDLE1Mode theCPUwillstoprunningbut thesystemclockwillcontinue tokeep theperipheral functionsoperational, ifFSYSONbitishigh.IfFSYSONbitislow,theCPUandthesystemclockwillallstopinIDLE0mode.IfthebitislowthedevicewillentertheSLEEPModewhenaHALTinstructionisexecuted.

Bit0 HLCLK:SystemClockSelection0:fH/2~fH/64orfSUB

1:fH

ThisbitisusedtoselectifthefHclockorthefH/2~fH/64orfSUBclockisusedasthesystemclock.WhenthebitishighthefHclockwillbeselectedandiflowthefH/2~fH/64orfSUBclockwillbeselected.WhensystemclockswitchesfromthefHclocktothefSUBclockandthefHclockwillbeautomaticallyswitchedofftoconservepower.




System Operation ModesThere are fivedifferentmodesofoperation for themicrocontroller, eachonewith its ownspecial characteristics andwhichcanbe chosenaccording to the specificperformanceandpowerrequirementsof theapplication.Thereare twomodesallowingnormaloperationof themicrocontroller, theNORMALModeandSLOWMode.Theremainingthreemodes, theSLEEP,IDLE0andIDLE1ModeareusedwhenthemicrocontrollerCPUisswitchedofftoconservepower.

Operation ModeDescription

CPU fSYS fSUB fS

NORMAL Mode On fH~fH/64 On OnSLOW Mode On fSUB On OnIDLE0 Mode Off Off On OnIDLE1 Mode Off On On OnSLEEP Mode Off Off On On

NORMAL ModeAsthenamesuggeststhisisoneofthemainoperatingmodeswherethemicrocontrollerhasallofitsfunctionsoperationalandwherethesystemclockisprovidedbythehighspeedoscillator.Thismodeallowsthemicrocontroller tooperatenormallywithaclocksourcethatwillcomefromtheHIRCoscillator.Thehighspeedoscillatorwillhoweverfirstbedividedbyaratiorangingfrom1to64,theactualratiobeingselectedbytheCKS2~CKS0andHLCLKbitsintheSMODregister.Althoughahighspeedoscillatorisused,runningthemicrocontrolleratadividedclockratioreducestheoperatingcurrent.

SLOW Mode This isalsoamodewhere themicrocontrolleroperatesnormallyalthoughnowwithaslowerspeedclocksource.Theclocksourceusedwillbesourcedfromthelowspeedoscillator,theLIRC.Runningthemicrocontrollerinthismodeallowsittorunwithmuchloweroperatingcurrents.IntheSLOWMode,fHisoff.

SLEEP ModeTheSLEEPMode isenteredwhenanHALTinstruction isexecutedand the IDLENbit in theSMODregisterislow.IntheSLEEPmodetheCPUwillbestopped.HoweverthefSUBandfSclockswillcontinuetooperatebecausetheWatchdogTimerfunctionisalwaysenabledanditsclocksourceisfromfSUB.

IDLE0 ModeTheIDLE0ModeisenteredwhenaHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisterishighandtheFSYSONbitintheCTRLregisterislow.IntheIDLE0ModethesystemoscillatorwillbeinhibitedfromdrivingtheCPUbutsomeperipheralfunctionswillremainoperationalsuchastheWatchdogTimerandTimer/EventCounter.IntheIDLE0Mode,thesystemoscillatorwillbestoppedandtheWatchdogTimerclock,fS,willbestillon.

IDLE1 ModeTheIDLE1ModeisenteredwhenanHALTinstructionisexecutedandwhentheIDLENbit intheSMODregisterishighandtheFSYSONbitintheCTRLregisterishigh.IntheIDLE1ModethesystemoscillatorwillbeinhibitedfromdrivingtheCPUbutmaycontinuetoprovideaclocksourcetokeepsomeperipheralfunctionsoperationalsuchastheWatchdogTimerandTimer/EventCounter.IntheIDLE1Mode,thesystemoscillatorwillcontinuetorun,andthissystemoscillatormaybehighspeedorlowspeedsystemoscillator.IntheIDLE1ModetheWatchdogTimerclock,fS,willbeon.




Operating Mode SwitchingThedevicescanswitchbetweenoperatingmodesdynamicallyallowingtheusertoselectthebestperformance/powerratiofor thepresent taskinhand.Inthiswaymicrocontrolleroperationsthatdonotrequirehighperformancecanbeexecutedusingslowerclocksthusrequiringlessoperatingcurrentandprolongingbatterylifeinportableapplications.

Insimple terms,ModeSwitchingbetween theNORMALModeandSLOWMode isexecutedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregisterwhileModeSwitchingfromtheNORMAL/SLOWModestotheSLEEP/IDLEModesisexecutedviatheHALTinstruction.WhenaHALTinstructionisexecuted,whetherthedeviceenterstheIDLEModeortheSLEEPModeisdeterminedbytheconditionof theIDLENbit in theSMODregisterandFSYSONintheCTRLregister.

WhentheHLCLKbitswitchestoalowlevel,whichimpliesthatclocksourceisswitchedfromthehighspeedclocksource,fH,totheclocksource,fH/2~fH/64orfSUB.IftheclockisfromthefSUB,thehighspeedclocksourcewillstoprunningtoconservepower.WhenthishappensitmustbenotedthatthefH/16andfH/64internalclocksourceswillalsostoprunning,whichmayaffecttheoperationofother internalfunctionssuchastheTimer/EventCounter.Theaccompanyingflowchartshowswhathappenswhenthedevicemovesbetweenthevariousoperatingmodes.

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NORMAL Mode to SLOW Mode Switching WhenrunningintheNORMALMode,whichusesthehighspeedsystemoscillator,andthereforeconsumesmorepower,thesystemclockcanswitchtorunintheSLOWModebysettheHLCLKbitto"0"andsettheCKS2~CKS0bitsto"000"or"001"intheSMODregister.Thiswillthenusethelowspeedsystemoscillatorwhichwillconsumelesspower.Usersmaydecidetodothisforcertainoperationswhichdonotrequirehighperformanceandcansubsequentlyreducepowerconsumption.

TheSLOWModeissourcedfromtheLIRCoscillatorandthereforerequiresthisoscillator tobestablebeforefullmodeswitchingoccurs.ThisismonitoredusingtheLTObitintheSMODregister.

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SLOW Mode to NORMAL Mode SwitchingInSLOWMode thesystemuses theLIRClowspeedsystemoscillator.Toswitchback to theNORMALMode,wherethehighspeedsystemoscillatorisused,theHLCLKbitshouldbesetto"1"orHLCLKbit is"0",butCKS2~CKS0isset to"010","011","100","101","110"or"111".Asacertainamountoftimewillberequiredforthehighfrequencyclocktostabilise,thestatusoftheHTObitischecked.Theamountoftimerequiredforhighspeedsystemoscillatorstabilizationdependsuponwhichhighspeedsystemoscillatortypeisused.

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Entering the SLEEP ModeThereisonlyonewayforthedevicestoentertheSLEEPModeandthatistoexecutethe"HALT"instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto"0"andtheWDTison.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• ThesystemclockandTimeBaseclockwillbestoppedandtheapplicationprogramwillstopatthe"HALT"instruction,buttheWDTwillremainwiththeclocksourcecomingfromthefSUBclock.

• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.

• TheWDTwillbeclearedandresumecounting

• TheI/Oportswillmaintaintheirpresentconditions.

• Inthestatusregister,thePowerDownflag,PDF,willbesetandtheWatchdogtime-outflag,TO,willbecleared.




Entering the IDLE0 ModeThereisonlyonewayforthedevicestoentertheIDLE0Modeandthatistoexecutethe"HALT"instructionintheapplicationprogramwiththeIDLENbitinSMODregisterisequalto"1"andtheFSYSONbitinCTRLregisterisequalto"0".Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• Thesystemclockwillbestoppedandtheapplicationprogramwillstopatthe"HALT"instruction,buttheTimeBaseclockandfSUBclockwillbeon.


• TheWDTwillbeclearedandresumecounting



Entering the IDLE1 ModeThereisonlyonewayforthedevicestoentertheIDLE1Modeandthatistoexecutethe"HALT"instructionintheapplicationprogramwiththeIDLENbitinSMODregisterisequalto"1"andtheFSYSONbitinCTRLregisterisequalto"1".Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• ThesystemclockandTimeBaseclockandfSUBclockwillbeonandtheapplicationprogramwillstopatthe"HALT"instruction


• TheWDTwillbeclearedandresumecounting.



Standby Current ConsiderationsAsthemainreasonforenteringtheSLEEPorIDLEModeistokeepthecurrentconsumptionofthedevicestoaslowavalueaspossible,perhapsonlyintheorderofseveralmicro-ampsexceptintheIDLE1Mode,thereareotherconsiderationswhichmustalsobetakenintoaccountbythecircuitdesignerifthepowerconsumptionistobeminimised.SpecialattentionmustbemadetotheI/Opinsonthedevice.Allhigh-impedanceinputpinsmustbeconnectedtoeitherafixedhighorlowlevelasanyfloatinginputpinscouldcreateinternaloscillationsandresultinincreasedcurrentconsumption.Thisalsoappliestodevicewhichhasdifferentpackagetypes,astheremaybeunbondedpins.Thesemusteitherbesetupasoutputsorifsetupasinputsmusthavepull-highresistorsconnected.

Caremustalsobetakenwiththeloads,whichareconnectedtoI/Opins,whicharesetupasoutputs.Theseshouldbeplacedinaconditioninwhichminimumcurrent isdrawnorconnectedonlytoexternalcircuits thatdonotdrawcurrent,suchasotherCMOSinputs.Alsonote thatadditionalstandbycurrentwillalsoberequiredifusingtheLIRCoscillator.

IntheIDLE1Modethesystemoscillatorison,ifthesystemoscillatorisfromthehighspeedsystemoscillator,theadditionalstandbycurrentwillalsobeperhapsintheorderofseveralhundredmicro-amps.




Wake-upAfterthesystementerstheSLEEPorIDLEMode,itcanbewokenupfromoneofvarioussourceslistedasfollows:

• AnexternalfallingedgeonPortA

• Asysteminterrupt

• AWDToverflow

IfthedevicesarewokenupbyaWDToverflow,aWatchdogTimerresetwillbeinitiated.Althoughthiswake-upmethodwill initiatea resetoperation, theactual sourceof thewake-upcanbedeterminedbyexaminingtheTOandPDFflags.ThePDFflagisclearedbyasystempower-uporexecutingtheclearWatchdogTimerinstructionsandissetwhenexecutingthe"HALT"instruction.TheTOflagisset ifaWDTtime-outoccurs,andcausesawake-upthatonlyresetstheProgramCounterandStackPointer,theotherflagsremainintheiroriginalstatus.

EachpinonPortAcanbesetupusingthePAWUregistertopermitanegativetransitiononthepintowake-upthesystem.WhenaPortApinwake-upoccurs,theprogramwillresumeexecutionattheinstructionfollowingthe"HALT"instruction.If thesystemiswokenupbyaninterrupt, thentwopossiblesituationsmayoccur.Thefirstiswheretherelatedinterruptisdisabledortheinterruptisenabledbutthestackisfull,inwhichcasetheprogramwillresumeexecutionattheinstructionfollowingthe"HALT"instruction.Inthissituation,theinterruptwhichwoke-upthedevicewillnotbeimmediatelyserviced,butwillratherbeservicedlaterwhentherelatedinterruptisfinallyenabledorwhenastacklevelbecomesfree.Theothersituationiswheretherelatedinterruptisenabledandthestackisnotfull,inwhichcasetheregularinterruptresponsetakesplace.Ifaninterruptrequestflag issethighbeforeentering theSLEEPorIDLEMode, thewake-upfunctionof therelatedinterruptwillbedisabled.

System Oscillator Wake-up Time(SLEEP Mode)

Wake-up Time(IDLE0 Mode)

Wake-up Time(IDLE1 Mode)

HIRC 1024 HIRC cycles 1024 HIRC cyclesLIRC 1~2 LIRC cycles 1~2 LIRC cycles

Wake-Up Times

Programming ConsiderationsThehighspeedandlowspeedoscillatorsbothusethesameSSTcounter.Forexample,ifthesystemiswokenupfromtheSLEEPModetheHIRCoscillatorneedstostart-upfromanoffstate.

IfthedevicesarewokenupfromtheSLEEPModetotheNORMALMode,thehighspeedsystemoscillatorneedsanSSTperiod.ThedeviceswillexecutethefirstinstructionafterHTOishigh.




Watchdog TimerTheWatchdogTimerisprovidedtopreventprogrammalfunctionsorsequencesfromjumpingtounknownlocations,duetocertainuncontrollableexternaleventssuchaselectricalnoise.

Watchdog Timer Clock SourceTheWatchdogTimerclocksourceisprovidedbytheinternalclockfSUB,whichissourcedfromtheLIRCoscillator.TheWatchdogTimersourceclockisthensubdividedbyaratioof28to218togivelongertimeouts,theactualvaluebeingchosenusingtheWS2~WS0bitsintheWDTCregister.TheLIRCinternaloscillatorhasanapproximateperiodfrequencyof32KHzatasupplyvoltageof5V.

However,itshouldbenotedthatthisspecifiedinternalclockperiodcanvarywithVDD,temperatureandprocessvariations.

Watchdog Timer Control RegisterAsingleregister,WDTC,controlstherequiredtimeoutperiod.

WDTC RegisterBit 7 6 5 4 3 2 1 0

Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 1 0 1 0 0 1 1

Bit7~3 WE4~WE0:WDTSoftwarecontrol01010B:enable10101B:enable(default)Othervalues:MCUreset(resetwillbeactiveafter2~3LIRCclockfordebouncetime).

IftheMCUresetiscausedbyWDTCsoftwarereset,theWRFflaginCTRLregisterwillbesetafterreset.

Bit2~0 WS2~WS0:WDTtime-outperiodselection000:28/fS

001:210/fS

010:212/fS

011:214/fS

100:215/fS

101:216/fS

110:217/fS

111:218/fS

These threebitsdetermine thedivisionratioof theWatchdogTimersourceclock,whichinturndeterminesthetimeoutperiod.

CTRL RegisterBit 7 6 5 4 3 2 1 0

Name FSYSON — — — — LVRF LRF WRFR/W R/W — — — — R/W R/W R/WPOR 0 — — — — × 0 0

"×" unknownBit7,2~1 DecribedinothersectionBit6~3 Unimplemented,readas"0"Bit0 WRF:resetcausedbyWE[4:0]setting

0:Notactive1:Active

Thisbitcanbeclearedto"0",butcannotbesetto"1".




Watchdog Timer OperationTheWatchdogTimeroperatesbyprovidingadeviceresetwhenits timeroverflows.ThismeansthatintheapplicationprogramandduringnormaloperationtheuserhastostrategicallycleartheWatchdogTimerbeforeitoverflowstopreventtheWatchdogTimerfromexecutingareset.Thisisdoneusingtheclearwatchdoginstructions.

Undernormalprogramoperation,aWatchdogTimertime-outwill initialiseadeviceresetandsetthestatusbitTO.However,ifthesystemisintheSLEEPorIDLEMode,whenaWatchdogTimertime-outoccurs,theTObitinthestatusregisterwillbesetandonlytheProgramCounterandStackPointerwillbereset.ThreemethodscanbeadoptedtoclearthecontentsoftheWatchdogTimer.ThefirstisaWDTsoftwarereset,whichmeansacertainvalueiswrittenintotheWE4~WE0bitfiledexcept01010Band10101B,thesecondisusingtheWatchdogTimersoftwareclearinstructionsandthethirdisviaaHALTinstruction.

TocleartheWatchdogTimeris tousethesingle"CLRWDT"instruction.Asimpleexecutionof"CLRWDT"willcleartheWDT.

Themaximumtimeoutperiodiswhenthe218divisionratioisselected.Asanexample,withtheLIRCoscillatorasitssourceclock,thiswillgiveamaximumwatchdogperiodofaround8secondforthe218divisionratio,andaminimumtimeoutof7.8msforthe28divisionration.

“CLR WDT”Instruction

8-stage Divider WDT Prescaler

WE4~WE0 bitsWDTC Register Reset MCU

fS/28

8-to-1 MUX

CLR

WS2~WS0

WDT Time-out(28/fS ~ 218/fS)

“HALT”Instruction

fSfSUB

Watchdog Timer




Reset and InitialisationAresetfunctionisafundamentalpartofanymicrocontrollerensuringthat thedevicecanbesettosomepre-determinedcondition irrespectiveofoutsideparameters.Themost important resetconditionisafterpowerisfirstappliedtothemicrocontroller.Inthiscase, internalcircuitrywillensure that themicrocontroller,afterashortdelay,willbe inawelldefinedstateandready toexecutethefirstprograminstruction.Afterthispower-onreset,certainimportantinternalregisterswillbesettodefinedstatesbeforetheprogramcommences.

Another typeofreset iswhentheWatchdogTimeroverflowsandresets themicrocontroller.Alltypesofresetoperationsresultindifferentregisterconditionsbeingsetup.AnotherresetexistsintheformofaLowVoltageReset,LVR,whereafullreset,isimplementedinsituationswherethepowersupplyvoltagefallsbelowacertainthreshold.

Reset FunctionsTherearefourwaysinwhichamicrocontrollerresetcanoccur,througheventsoccurringbothinternally:

Power-on ResetThemostfundamentalandunavoidablereset is theonethatoccursafterpowerisfirstappliedtothemicrocontroller.AswellasensuringthattheProgramMemorybeginsexecutionfromthefirstmemoryaddress,apower-onresetalsoensures thatcertainother registersarepreset toknownconditions.AlltheI/Oportandportcontrolregisterswillpowerupinahighconditionensuringthatallpinswillbefirstsettoinputs.

ThemicrocontrollerhasaninternalRCresetfunction,duetounstablepoweronconditions.ThistimedelaycreatedbytheRCnetworkensuresthestateofthePORremainslowforanextendedperiodwhilethepowersupplystabilises.Duringthistime,normaloperationofthemicrocontrollerisinhibited.AfterthestateofthePORreachesacertainvoltagevalue,theresetdelaytimetPORisinvokedtoprovideanextradelaytimeafterwhichthemicrocontrollercanbeginnormaloperation.

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Power-On Reset Timing Chart

Low Voltage Reset – LVRThemicrocontrollerscontainalowvoltageresetcircuitinordertomonitorthesupplyvoltageofthedevice.TheLVRfunctionisalwaysenabledwithaspecificLVRvoltage,VLVR.Ifthesupplyvoltageofthedevicesdropstowithinarangeof0.9V~VLVRsuchasmightoccurwhenchangingabattery,theLVRwillautomaticallyresetthedevicesinternallyandtheLVRFbitintheCTRLregisterwillalsobesetto"1".

TheLVRincludesthefollowingspecifications:ForavalidLVRsignal,alowvoltage,i.e.,avoltagein therangebetween0.9V~VLVRmustexist forgreater than thevalue tLVRspecified in theA.C.characteristics.If thelowvoltagestatedoesnotexceedtLVR, theLVRwill ignoreitandwillnotperformaresetfunction.TheactualVLVRissetbytheLVS7~LVS0bitsintheLVRCregister.IftheLVS7~LVS0bitsarechangedtosomecertainvaluesbytheenvironmentalnoise,theLVRwillresetthedeviceafter2~3LIRCclockcycles.Whenthishappens,theLRFbitintheCTRLregisterwillbesetto1.Afterpowerontheregisterwillhavethevalueof01010101B.NotethattheLVRfunctionwillbeautomaticallydisabledwhenthedeviceentersthepowerdownmode.




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Low Voltage Reset Timing Chart

• LVRC Register – BS83A04A-3

Bit 7 6 5 4 3 2 1 0Name LVS7 LVS6 LVS5 LVS4 LVS3 LVS2 LVS1 LVS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 1 0 1 0 1 0 1

Bit7~0 LVS7 ~ LVS0:LVRVoltageSelectcontrol01010101:2.55V00110011:2.55V10011001:2.55V10101010:2.55VOthervalues:MCUreset(resetwillbeactiveafter2~3LIRCclockfordebouncetime)

Note:UsingS/Wtowrite00H~FFHcancontroltheLVRvoltage,alsocanresettheMCU.If theMCUresetiscausedbytheLVRCregister, theLRFflagintheCTRLregisterwillbesethigh.

• LVRC Register – BS83A02A-4/BS83A04A-4

Bit 7 6 5 4 3 2 1 0Name LVS7 LVS6 LVS5 LVS4 LVS3 LVS2 LVS1 LVS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 1 0 1 0 1 0 1

Bit7~0 LVS7 ~ LVS0:LVRVoltageSelectcontrol01010101:2.10V00110011:2.10V10011001:2.10V10101010:2.10VOthervalues:MCUreset(resetwillbeactiveafter2~3LIRCclockfordebouncetime)

Note:UsingS/Wtowrite00H~FFHcancontroltheLVRvoltage,alsocanresettheMCU.If theMCUresetiscausedbytheLVRCregister, theLRFflagintheCTRLregisterwillbesethigh.

• CTRL Register

Bit 7 6 5 4 3 2 1 0Name FSYSON — — — — LVRF LRF WRFR/W R/W — — — — R/W R/W R/WPOR 0 — — — — × 0 0

"×" unknownBit7 DecribedinothersectionBit6~3 Unimplemented,readas"0"Bit2 LVRF:LVRfunctionresetflag

0:Notactive1:Active

Thisbitcanbeclearedto"0",butcannotbesetto"1".Bit1 LRF:LVRControlregistersoftwareresetflag

0:Notactive1:Active

Thisbitcanbeclearedto"0",butcannotbesetto"1".Bit0 Decribedinothersection




Watchdog Time-out Reset during Normal OperationTheWatchdogtime-outResetduringnormaloperationis thesameasahardwarepower-onresetexceptthattheWatchdogtime-outflagTOwillbesettohigh.

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WDT Time-out Reset during Normal Operation Timing Chart

Watchdog Time-out Reset during SLEEP or IDLE ModeTheWatchdogtime-outResetduringSLEEPorIDLEModeisa littledifferentfromotherkindsofreset.MostoftheconditionsremainunchangedexceptthattheProgramCounterandtheStackPointerwillbeclearedto"0"andtheTOflagwillbesetto"1".RefertotheA.C.CharacteristicsfortSSTdetails.

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Note:ThetSSTis1024~1025clockcyclesifthesystemclocksourceisprovidedbyHIRC.ThetSSTis1~2clockforLIRC.

Reset Initial ConditionsThedifferent typesofresetdescribedaffect theresetflagsindifferentways.Theseflags,knownasPDFandTOare located in thestatus registerandarecontrolledbyvariousmicrocontrolleroperations,suchas theSLEEPorIDLEModefunctionorWatchdogTimer.Thereset flagsareshowninthetable:

TO PDF RESET Conditions0 0 Power-on resetu u LVR reset during NORMAL or SLOW Mode operation1 u WDT time-out reset during NORMAL or SLOW Mode operation1 1 WDT time-out reset during IDLE or SLEEP Mode operation

Note:"u"standsforunchanged

Thefollowingtableindicatesthewayinwhichthevariouscomponentsofthemicrocontrollerareaffectedafterapower-onresetoccurs.

Item Condition After RESETProgram Counter Reset to zeroInterrupts All interrupts will be disabledWDT Clear after reset, WDT begins countingTimer/Event Counter Timer Counter will be turned offInput/Output Ports I/O ports will be setup as inputsStack Pointer Stack Pointer will point to the top of the stack

Thedifferentkindsofresetsallaffecttheinternalregistersofthemicrocontrollerindifferentways.Toensurereliablecontinuationofnormalprogramexecutionafteraresetoccurs,itisimportanttoknowwhatconditionthemicrocontrolleris inafteraparticularresetoccurs.Thefollowingtabledescribeshoweachtypeofresetaffectsthemicrocontrollerinternalregisters.




Register LVR & Power-on Reset WDT Time-out(Normal Operation)

WDT Time-out(HALT)

MP0 x x x x x x x x u u u u u u u u u u u u u u u uMP1 x x x x x x x x u u u u u u u u u u u u u u u uACC x x x x x x x x u u u u u u u u u u u u u u u uPCL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TBLP x x x x x x x x u u u u u u u u u u u u u u u uTBLH x x x x x x x x u u u u u u u u u u u u u u u uTBHP - - - - - - x x - - - - - - u u - - - - - - u uSTATUS - - 0 0 x x x x - - 1 u u u u u - - 1 1 u u u uSMOD 0 0 0 - 0 0 11 0 0 0 - 0 0 11 u u u - u u u uCTRL 0 - - - - x 0 0 0 - - - - x 0 0 u - - - - u u uINTEG - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uINTC0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - u u u u u u uINTC1 - - 0 - - - 0 - - - 0 - - - 0 - - - u - - - u -LVRC 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 u u u u u u u u

PABS83A02A-4 - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - u u u uBS83A04A-3BS83A04A-4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u

PACBS83A02A-4 - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - u u u uBS83A04A-3BS83A04A-4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u

PAPUBS83A02A-4 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u uBS83A04A-3BS83A04A-4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PAWUBS83A02A-4 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u uBS83A04A-3BS83A04A-4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

WDTC 0 1 0 1 0 0 11 0 1 0 1 0 0 11 u u u u u u u uTBC - - 0 0 - - - - - - 0 0 - - - - - - u u - - - -TMR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTMRC - - 0 0 - 0 0 0 - - 0 0 - 0 0 0 - - u u - u u uTKTMR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTKC0 - 0 0 0 0 - 0 0 - 0 0 0 0 - 0 0 - u u u u - u uTK16DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTK16DH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTKC1 - - - - - - 1 1 - - - - - - 1 1 - - - - - - u uTKM016DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTKM016DH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTKM0ROL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTKM0ROH - - - - - - 0 0 - - - - - - 0 0 - - - - - - u u

TKM0C0BS83A02A-4 - 0 0 - 0 0 0 0 - 0 0 - 0 0 0 0 - u u - u u u uBS83A04A-3BS83A04A-4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

TKM0C1BS83A02A-4 0 - 0 0 - - 0 0 0 - 0 0 - - 0 0 u - u u - - u uBS83A04A-3BS83A04A-4 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 u - u u u u u u

Note:"-"notimplement"u"means"unchanged"

"x"means"unknown"




Input/Output PortsHoltekmicrocontrollersofferconsiderableflexibilityontheirI/Oports.Mostpinscanhaveeitheraninputoroutputdesignationunderuserprogramcontrol.Additionally,astherearepull-highresistorsandwake-upsoftwareconfigurations,theuserisprovidedwithanI/Ostructuretomeettheneedsofawiderangeofapplicationpossibilities.

Thedevicesprovidebidirectionalinput/outputlineslabeledwithportnamesPA.TheseI/Oportsaremappedto theRAMDataMemorywithspecificaddressesasshownin theSpecialPurposeDataMemorytable.Allof theseI/Oportscanbeusedforinputandoutputoperations.Forinputoperation,theseportsarenon-latching,whichmeanstheinputsmustbereadyattheT2risingedgeofinstruction"MOVA,[m]",wheremdenotestheportaddress.Foroutputoperation,allthedataislatchedandremainsunchangeduntiltheoutputlatchisrewritten.

I/O Register List

Device RegisterName

Bit7 6 5 4 3 2 1 0

BS83A02A-4

PAWU — — — — PAWU3 PAWU2 PAWU1 PAWU0PAPU — — — — PAPU3 PAPU2 PAPU1 PAPU0PAC — — — — PA3 PA2 PA1 PA0PA — — — — PAC3 PAC2 PAC1 PAC0

BS83A04A-3BS83A04A-4

PAWU PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0PAPU PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0

PA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0PAC PAC7 PAC6 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0

Pull-high ResistorsManyproductapplicationsrequirepull-highresistorsfortheirswitchinputsusuallyrequiringtheuseofanexternalresistor.Toeliminatetheneedfortheseexternalresistors,allI/Opins,whenconfiguredasaninputhavethecapabilityofbeingconnectedtoaninternalpull-highresistor.Thesepull-highresistorsareselectedusingregisterPAPUetc.andareimplementedusingweakPMOStransistors.

PAPU Register – BS83A02A-4Bit 7 6 5 4 3 2 1 0

Name — — — — PAPU3 PAPU2 PAPU1 PAPU0R/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0

Bit7~4 Unimplemented,readas"0"Bit3~0 PAPU3~PAPU0:PAportpull-highresistorcontrol

0:Disable1:Enable

PAPU Register – BS83A04A-3/BS83A04A-4Bit 7 6 5 4 3 2 1 0

Name PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 PAPU7~PAPU0:PAportpull-highresistorcontrol0:Disable1:Enable




Port A Wake-upTheHALTinstructionforcesthemicrocontrollerintotheSLEEPorIDLEModewhichpreservespower,afeature that is importantforbatteryandother low-powerapplications.Variousmethodsexisttowake-upthemicrocontroller,oneofwhichistochangethelogicconditionononeofthePortApinsfromhightolow.Thisfunctionisespeciallysuitableforapplicationsthatcanbewokenupviaexternalswitches.EachpinonPortAcanbeselectedindividuallytohavethiswake-upfeatureusingthePAWUregister.

PAWU Register – BS83A02A-4Bit 7 6 5 4 3 2 1 0

Name — — — — PAWU3 PAWU2 PAWU1 PAWU0R/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0

Bit7~4 Unimplemented,readas"0"Bit3~0 PAWU3~PAWU0:PAwake-upfunctioncontrol

0:Disable1:Enable

PAWU Register – BS83A04A-3/BS83A04A-4Bit 7 6 5 4 3 2 1 0

Name PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 PAWU7~PAWU0:PAwake-upfunctioncontrol0:Disable1:Enable

I/O Port Control RegistersTheI/OporthasitsowncontrolregisterknownasPAC,tocontroltheinput/outputconfiguration.With thiscontrol register,eachCMOSoutputor inputcanbe reconfigureddynamicallyundersoftwarecontrol.EachpinoftheI/Oportisdirectlymappedtoabitinitsassociatedportcontrolregister.FortheI/Opintofunctionasaninput, thecorrespondingbitofthecontrolregistermustbewrittenasa"1".Thiswill thenallowthe logicstateof the inputpin tobedirectly readbyinstructions.Whenthecorrespondingbitofthecontrolregisteriswrittenasa"0",theI/OpinwillbesetupasaCMOSoutput.Ifthepiniscurrentlysetupasanoutput,instructionscanstillbeusedtoreadtheoutputregister.However,itshouldbenotedthattheprogramwillinfactonlyreadthestatusoftheoutputdatalatchandnottheactuallogicstatusoftheoutputpin.

PAC Register – BS83A02A-4Bit 7 6 5 4 3 2 1 0

Name — — — — PAC3 PAC2 PAC1 PAC0R/W — — — — R/W R/W R/W R/WPOR — — — — 1 1 1 1

Bit7~4 Unimplemented,readas"0"Bit3~0 PAC3~PAC0:I/OPortbit7~bit0Input/OutputControl

0:Output1:Input




PAC Register – BS83A04A-3/BS83A04A-4Bit 7 6 5 4 3 2 1 0

Name PAC7 PAC6 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 1 1 1 1 1 1 1 1

Bit7~0 PAC7~PAC0:I/OPortbit7~bit0Input/OutputControl0:Output1:Input

I/O Pin StructuresTheaccompanyingdiagrams illustrate the internalstructuresofsomegeneric I/Opin types.AstheexactlogicalconstructionoftheI/Opinwilldifferfromthesedrawings,theyaresuppliedasaguideonlytoassistwiththefunctionalunderstandingoftheI/Opins.Thewiderangeofpin-sharedstructuresdoesnotpermitalltypestobeshown.

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Generic Input/Output Ports

Programming ConsiderationsWithintheuserprogram,oneof thethingsfirst toconsider isport initialisation.Afterareset,allof theI/Odataandportcontrolregisterswillbeset tohigh.ThismeansthatallI/Opinswillbedefaultedtoaninputstate,thelevelofwhichdependsontheotherconnectedcircuitryandwhetherpull-highselectionshavebeenchosen.If theportcontrolregistersarethenprogrammedtosetupsomepinsasoutputs,theseoutputpinswillhaveaninitialhighoutputvalueunlesstheassociatedportdataregistersarefirstprogrammed.Selectingwhichpinsareinputsandwhichareoutputscanbeachievedbyte-widebyloadingthecorrectvalues into theappropriateportcontrolregisterorbyprogrammingindividualbitsintheportcontrolregisterusingthe"SET[m].i"and"CLR[m].i"instructions.Notethatwhenusingthesebitcontrolinstructions,aread-modify-writeoperationtakesplace.Themicrocontrollermustfirstreadinthedataontheentireport,modifyittotherequirednewbitvaluesandthenrewritethisdatabacktotheoutputports.

PortAhas theadditionalcapabilityofprovidingwake-upfunctions.When thedevice is in theSLEEPorIDLEMode,variousmethodsareavailabletowakethedeviceup.OneoftheseisahightolowtransitionofanyofthePortApins.SingleormultiplepinsonPortAcanbesetuptohavethisfunction.




Timer/Event CounterTheprovisionoftimersformanimportantpartofanymicrocontroller,givingthedesignerameansofcarryingouttimerelatedfunctions.Thedevicescontainan8-bittimer.Andtheprovisionofaninternalprescalertotheclockcircuitryongivesaddedrangetothetimer.

TherearetwotypesofregistersrelatedtotheTimer/EventCounters.Thefirst is theregister thatcontainstheactualvalueofthetimerandintowhichaninitialvaluecanbepreloaded.ReadingfromthisregisterretrievesthecontentsoftheTimer/EventCounter.ThesecondtypeofassociatedregisteristheTimerControlRegisterwhichdefinesthetimeroptionsanddetermineshowthetimeristobeused.

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Timer/Event Counter

Configuring the Timer/Event Counter Input Clock SourceTheTimer/EventCounterclocksourcecanoriginatefromeither fSYSor thefSUBOscillator, thechoiceofwhichisdeterminedbytheTSbitintheTMRCregister.Thisinternalclocksourceisfirstdividedbyaprescaler,thedivisionratioofwhichisconditionedbytheTimerControlRegisterbitsTPSC0~TPSC2.

Timer Register – TMRThetimerregisterTMRisaspecialfunctionregisterlocatedintheSpecialPurposeDataMemoryandistheplacewheretheactualtimervalueisstored.Thevalueinthetimerregisterincreasesbyoneeachtimeaninternalclockpulseisreceived.ThetimerwillcountfromtheinitialvalueloadedbythepreloadregistertothefullcountofFFHforthe8-bitTimer/EventCounter,atwhichpointthetimeroverflowsandaninternalinterruptsignalisgenerated.Thetimervaluewillthenresetwiththeinitialpreloadregistervalueandcontinuecounting.

NotethattoachieveamaximumfullrangecountofFFH,thepreloadregistermustfirstbeclearedtoallzeros.Note that if theTimer/EventCounter is inanOFFconditionanddata iswritten toitspreloadregister, thisdatawillbeimmediatelywrittenintotheactualcounter.However, if thecounter isenabledandcounting,anynewdatawritten into thepreloaddataregisterduring thisperiodwillremaininthepreloadregisterandwillonlybewrittenintotheactualcounterthenexttimeanoverflowoccurs.




Timer Control Register – TMRC

ItistheTimerControlRegistertogetherwithitscorrespondingtimerregisterthatcontrolsthefulloperationoftheTimer/EventCounter.Beforethetimercanbeused,it isessentialthattheTimerControlRegisterisfullyprogrammedwiththerightdatatoensureitscorrectoperation,aprocessthatisnormallycarriedoutduringprograminitialisation.

Thetimer-onbit,whichisbit4oftheTimerControlRegisterandknownasTONbit,providesthebasicon/offcontroloftherespectivetimer.Settingthebithighallowsthecountertorun.Clearingthebitstopsthecounter.Bits0~2oftheTMRCregisterdeterminethedivisionratiooftheinputclockprescaler.Inaddition,thebitTSisusedtoselecttheinternalclocksource.

TMRC RegisterBit 7 6 5 4 3 2 1 0

Name — — TS TON — TPSC2 TPSC1 TPSC0R/W — — R/W R/W — R/W R/W R/WPOR — — 0 0 — 0 0 0

Bit7~6 Unimplemented,readas"0"Bit5 TS:Timer/EventCounterClockSource

0:fSYS

1:fSUB

Bit4 TON:Timer/EventCounterCountingEnable0:Disable1:Enable

Bit3 Unimplemented,readas"0"Bit2~0 TPSC2~TPSC0:Timerprescalerrateselection

Timerinternalclock=000:fTP

001:fTP/2010:fTP/4011:fTP/8100:fTP/16101:fTP/32110:fTP/64111:fTP/128

Timer/Event Counter Operation TheTimer/EventCountercanbeutilised tomeasurefixed timeintervals,providingan internalinterruptsignaleachtimetheTimer/EventCounteroverflows.Theinternalclockisusedasthetimerclock.ThetimerinputclockiseitherfSYSorthefSUBOscillator.However,thistimerclocksourceisfurtherdividedbyaprescaler,thevalueofwhichisdeterminedbythebitsTPSC0~TPSC2intheTimerControlRegister.Thetimer-onbit,TONmustbesethightoenablethetimertorun.Eachtimewhenaninternalclockhightolowtransitionoccurs,thetimerwillreloadthevaluealreadyloadedinto thepreloadregisterandcontinuescounting.Atimeroverflowconditionandcorrespondinginternalinterruptisoneofthewake-upsources,however,theinternalinterruptscanbedisabledbyensuringthattheTEbitoftheINTC0registerareresettozero.




PrescalerBitsTPSC0~TPSC2of theTMRCregistercanbeusedtodefineadivisionratiofor theinternalclocksourceoftheTimer/EventCounterenablinglongertimeoutperiodstobesetup.

Programming ConsiderationWhentheTimer/EventCounter is read,or ifdata iswritten to thepreloadregister, theclock isinhibitedtoavoiderrors,howeverasthismayresultinacountingerror,thisshouldbetakenintoaccountbytheprogrammer.Caremustbetakentoensurethat thetimersareproperlyinitializedbeforeusingthemforthefirsttime.Theassociatedtimerenablebitsintheinterruptcontrolregistermustbeproperlysetotherwisetheinternalinterruptassociatedwiththetimerwillremaininactive.Theedgeselect, timermodeandclocksourcecontrolbits in timercontrolregistermustalsobecorrectlyset toensure the timer isproperlyconfiguredfor the requiredapplication. It isalsoimportant toensurethataninitialvalueisfirst loadedintothetimerregistersbeforethetimerisswitchedon;thisisbecauseafterpower-ontheinitialvaluesofthetimerregistersareunknown.

Afterthetimerhasbeeninitializedthetimercanbeturnedonandoffbycontrollingtheenablebitinthetimercontrolregister.WhentheTimer/EventCounteroverflows,itscorrespondinginterruptrequest flag in the interruptcontrol registerwillbeset. If theTimer/EventCounter interrupt isenabledthiswillinturngenerateaninterruptsignal.Howeverirrespectiveofwhethertheinterruptsareenabledornot,aTimer/EventCounteroverflowwillalsogenerateawake-upsignalifthedeviceisinaPower-downcondition.ThissituationmayoccuriftheTimer/EventCounterisintheEventCountingModeandiftheexternalsignalcontinuestochangestate.Insuchacase,theTimer/EventCounterwillcontinuetocounttheseexternaleventsandifanoverflowoccursthedevicewillbewokenupfromitsPower-downcondition.Topreventsuchawake-upfromoccurring, the timerinterruptrequestflagshouldfirstbesethighbefore issuingthe"HALT"instruction toenter theIDLE/SLEEPMode.




Touch Key FunctionThesedevicesprovidetouchkeyfunction.Thetouchkeyfunctionisfullyintegratedandrequiresnoexternalcomponents,allowingtouchkeyfunctiontobeimplementedbythesimplemanipulationofinternalregisters.

Touch Key StructureThetouchkeysarepinsharedwiththePAI/Opins,withthedesiredfunctionchosenviaregisterbits.TheTouchKeyshavetheirowncontrollogiccircuitsandregisterset.

Device Keys - n Touch Key Shared I/O PinBS83A02A-4 2 KEY1~KEY2 PA1, PA3BS83A04A-3BS83A04A-4 4 KEY1~KEY4 PA5, PA1, PA3, PA4

Touch Key Register DefinitionThetouchkeymodulecontainstwoorfourtouchkeyfunctionsdependingonthedevicechosen,hasitsownsuiteofeightregisters.Thefollowingtableshowstheregistersetforthistouchkeymodule.

Name UsageTKTMR Touch key 8-bit Timer/counter registerTKC0 Counter ON/OFF and clear control/ reference clock control/start bit TK16DL Touch key module 16-bit counter low byte contentsTK16DH Touch key module 16-bit counter high byte contentsTKC1 Touch key OSC frequency selectTKM016DH 16-bit C/F counter high byteTKM016DL 16-bit C/F counter low byteTKM0ROL Reference Oscillator internal capacitor selectTKM0ROH Reference Oscillator internal capacitor selectTKM0C0 Control Register 0, Key SelectTKM0C1 Control Register 1, Touch key or I/O select

Touch Key Registers

Device Register Name

Bit7 6 5 4 3 2 1 0

All devices

TKTMR D7 D6 D5 D4 D3 D2 D1 D0TKC0 — TKRCOV TKST TKCFOV TK16OV — TK16S1 TK16S0

TK16DL D7 D6 D5 D4 D3 D2 D1 D0TK16DH D15 D14 D13 D12 D11 D10 D9 D8

TKC1 — — — — — — TKFS1 TKFS0TKM016DL D7 D6 D5 D4 D3 D2 D1 D0TKM016DH D15 D14 D13 D12 D11 D10 D9 D8TKM0ROL D7 D6 D5 D4 D3 D2 D1 D0TKM0ROH — — — — — — D9 D8

BS83A02A-4TKM0C0 — M0MXS0 M0DFEN — M0SOFC M0SOF2 M0SOF1 M0SOF0TKM0C1 M0TSS — M0ROEN M0KOEN — — M0K2IO M0K1IO

BS83A04A-3BS83A04A-4

TKM0C0 M0MXS1 M0MXS0 M0DFEN M0FILEN M0SOFC M0SOF2 M0SOF1 M0SOF0TKM0C1 M0TSS — M0ROEN M0KOEN M0K4IO M0K3IO M0K2IO M0K1IO

Touch Key Register Listing




TKTMR RegisterBit 7 6 5 4 3 2 1 0

Name D7 D6 D5 D4 D3 D2 D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 TouchKey8-bittimer/counterregisterTheTimeslotcounteroverflowtimesetupis(256-TKTMR[7:0])×32

TKC0 RegisterBit 7 6 5 4 3 2 1 0

Name — TKRCOV TKST TKCFOV TK16OV — TK16S1 TK16S0R/W — R/W R/W R/W R/W — R/W R/WPOR — 0 0 0 0 — 0 0

Bit7 Unimplemented,readas"0"Bit6 TKRCOV:Timeslotcounteroverflowflag

0:Nooverflow1:Overflow

Iftimeslotcounterisoverflow,theTouchKeyInterruptrequestflag,TKMF,willbesetandmodulekeyoscillatorandreferenceoscillatorautostop.Allmodule16-bitC/Fcounter,16-bitcounter,5-bittimeslotcounterand8-bittimeslottimercounterwillautooff.

Bit5 TKST:StartTouchKeydetectioncontrolbit0:Stop0→1:On

Ifthisbitis0,the16-bitC/Fcounter,16-bitcounter,5-bittimeslotcounterwillaotuclearexceptfor the8-bitprogrammabletimeslotcounter isnotkown, itsoverflowtimeissetupbytheuser.0→1:BytheTKSTrisingedge,the16-bitC/Fcounter,16-bitcounter,5-bittimeslotcounterand8-bit timeslot timercounterwillautoonandenablekeyoscillatorandreferenceoscillatoroutputclocktoinputtothesecounters.

Bit4 TKCFOV:Touchkeymodule16-bitC/Fcounteroverflowflag0:Notoverflow1:Overflow

Whenthetouchkeymodule16-bitC/Fcounteroverflows, thisbitwillbeset to1.Asthisflagwillnotbeautomaticallycleared,ithastobeclearedbytheapplicationprogram.

Bit3 TK16OV:Touchkeymodule16-bitcounteroverflowflag0:Notoverflow1:Overflow

Whenthetouchkeymodule16-bitcounteroverflows,thisbitwillbesetto1.Asthisflagwillnotbeautomaticallycleared,ithastobeclearedbytheapplicationprogram.

Bit2 Unimplemented,readas"0"Bit1,0 TK16S1, TK16S0:touchkeymodule16-bitcounterclocksourceselection

00:fSYS/101:fSYS/210:fSYS/411:fSYS/8




TKC1 RegisterBit 7 6 5 4 3 2 1 0

Name — — — — — — TKFS1 TKFS0R/W — — — — — — R/W R/WPOR — — — — — — 1 1

Bit7~2 Unimplemented,readas"0"Bit1~0 TKFS1~TKFS0:touchkeyOSCfrequencyselection

00:500kHz01:1000kHz10:1500kHz11:2000kHz

TK16DL RegisterBit 7 6 5 4 3 2 1 0

Name D7 D6 D5 D4 D3 D2 D1 D0R/W R R R R R R R RPOR 0 0 0 0 0 0 0 0

Bit7~0 Touchkeymodule16-bitcounterlowbytecontents

TK16DH RegisterBit 7 6 5 4 3 2 1 0


Bit7~0 Touchkeymodule16-bitcounterhighbytecontents

TKM016DL RegisterBit 7 6 5 4 3 2 1 0


Bit7~0 Module016-bitcounterlowbytecontents

TKM016DH RegisterBit 7 6 5 4 3 2 1 0


Bit7~0 Module016-bitcounterhighbytecontents

TKM0ROL RegisterBit 7 6 5 4 3 2 1 0

Name D7 D6 D5 D4 D3 D2 D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 ReferenceOscillatorinternalcapacitorselectionThereferenceoscillatorisselectedasTKM0RO[9:0]×50pF/1024.




TKM0ROH RegisterBit 7 6 5 4 3 2 1 0

Name — — — — — — D9 D8R/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 ReferenceOscillatorinternalcapacitorselection

ThereferenceoscillatorisselectedasTKM0RO[9:0]×50pF/1024.

TKM0C0 Register – BS83A02A-4Bit 7 6 5 4 3 2 1 0

Name — M0MXS0 M0DFEN — M0SOFC M0SOF2 M0SOF1 M0SOF0R/W — R/W R/W — R/W R/W R/W R/WPOR — 0 0 — 0 0 0 0

Bit7 Unimplemented,readas"0"Bit6 M0MXS0:MultiplexerKeySelect

0:KEY11:KEY2

Bit5 M0DFEN:Multi-frequencyfunctioncontrol0:Disable1:Enable

Bit4 Unimplemented,readas"0"Bit3 M0SOFC:CtoFoscillatorfrequency-hoppingfunctioncontrol

0:ControlledbytheM0SOF2~M0SOF0bits1:Controlledbyhardware,regardlessofwhatisthestateofM0SOF2~M0SOF0bits

Whencontrolledbyhardware,thetimeslotcounterselectedbytheM0SOF2~M0SOF0bitsadjusttheCtoFoscillatorfrequencyautomatically.

Bit2~0 M0SOF2~M0SOF0:SelectingkeyoscillatororreferenceoscillatorfrequencyastheCtoFoscillatoriscontrolledbysoftware000:1380kHz001:1500kHz010:1670kHz011:1830kHz100:2000kHz101:2230kHz110:2460kHz111:2740kHz

Thefrequencymentionedherewilldifferwiththeexternalorinternalcapacitorvalue.Ifthekeyoscillatorfrequencyisselectedas2MHz,userscanadjustthefrequencyinscalewhenselectingotherfrequencies.




TKM0C0 Register – BS83A04A-3/BS83A04A-4Bit 7 6 5 4 3 2 1 0

Name M0MXS1 M0MXS0 M0DFEN M0FILEN M0SOFC M0SOF2 M0SOF1 M0SOF0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 M0MXS1, M0MXS0:MultiplexerKeySelect00:KEY101:KEY210:KEY311:KEY4

Bit5 M0DFEN:Multi-frequencyfunctioncontrol0:Disable1:Enable

Bit4 M0FILEN:Filterfunctioncontrol0:Disable1:Enable

Bit3 M0SOFC:CtoFoscillatorfrequency-hoppingfunctioncontrol0:ControlledbytheM0SOF2~M0SOF0bits1:Controlledbyhardware,regardlessofwhatisthestateofM0SOF2~M0SOF0bits

Whencontrolledbyhardware,thetimeslotcounterselectedbytheM0SOF2~M0SOF0bitsadjusttheCtoFoscillatorfrequencyautomatically.

Bit2~0 M0SOF2~M0SOF0:SelectingkeyoscillatororreferenceoscillatorfrequencyastheCtoFoscillatoriscontrolledbysoftware000:1380kHz001:1500kHz010:1670kHz011:1830kHz100:2000kHz101:2230kHz110:2460kHz111:2740kHz

Thefrequencymentionedherewilldifferwiththeexternalorinternalcapacitorvalue.Ifthekeyoscillatorfrequencyisselectedas2MHz,userscanadjustthefrequencyinscalewhenselectingotherfrequencies.

TKM0C1 Register – BS83A02A-4Bit 7 6 5 4 3 2 1 0

Name M0TSS — M0ROEN M0KOEN — — M0K2IO M0K1IOR/W R/W — R/W R/W — — R/W R/WPOR 0 — 0 0 — — 0 0

Bit7 M0TSS:TimeSlotcounterSelect0:ReferenceOscillator1:fSYS/4

Bit6 Unimplemented,readas"0"Bit5 M0ROEN:ReferenceOscillatorcontrol

0:Disable1:Enable

Bit4 M0KOEN:KeyOscillatorcontrol0:Disable1:Enable

Bit3~2 Unimplemented,readas"0"




Bit1 M0K2IO:I/OPinorTouchKey2FunctionSelect0:I/O1:Touchkeyinput


TKM0C1 Register – BS83A04A-3/BS83A04A-4Bit 7 6 5 4 3 2 1 0

Name M0TSS — M0ROEN M0KOEN M0K4IO M0K3IO M0K2IO M0K1IOR/W R/W — R/W R/W R/W R/W R/W R/WPOR 0 — 0 0 0 0 0 0

Bit7 M0TSS:TimeSlotcounterSelect0:ReferenceOscillator1:fSYS/4

Bit6 Unimplemented,readas"0"Bit5 M0ROEN:ReferenceOscillatorcontrol

0:Disable1:Enable

Bit4 M0KOEN:KeyOscillatorcontrol0:Disable1:Enable





Touch Key OperationWhenafingertouchesorisinproximitytoatouchpad,thecapacitanceofthepadwill increase.Byusingthiscapacitancevariationtochangeslightlythefrequencyoftheinternalsenseoscillator,touchactionscanbesensedbymeasuringthesefrequencychanges.Usinganinternalprogrammabledivider the referenceclock isused togeneratea fixed timeperiod.Bycountinganumberofgeneratedclockcyclesfromthesenseoscillatorduringthisfixedtimeperiodtouchkeyactionscanbedetermined.

ThedevicescontaintwoorfourtouchkeyinputswhicharesharedwithlogicalI/Opins,withthedesiredfunctionselectedusingregisterbits.TheTouchKeymodulealsohas itsown interruptvectorsandsetofinterruptflags.

During this referenceclock fixed interval, thenumberofclockcyclesgeneratedby thesenseoscillatorismeasured,anditisthisvaluethatisusedtodetermineifatouchactionhasbeenmadeornot.Attheendofthefixedreferenceclocktimeinterval,aTouchKeyinterruptsignalwillbegenerated.




WhenaTKSTrisingedgeoccurs,the16-bitC/Fcounter,16-bitcounter,5-bittimeslotcounterand8-bittimeslottimercounterwillautoon.WhileaTKSTfallingedgeoccurs,the16-bitC/Fcounter,16-bitcounterand5-bittimeslotcounterwillautooffexceptthatforthe8-bitprogrammabletimeslotcounter,itsoverflowtimeissetupbytheuser.

Whenthe5-bittimeslotcounterisoverflow,thekeyoscillatorandreferenceoscillatorautostopandthe16-bitC/Fcounter,16-bitcounter,5-bittimeslotcounterand8-bittimeslottimercounterwillautooff.The5-bittimeslotcounterand8-bittimeslottimercounterclocksourcederivefromthereferenceoscillatororfSYS/4.

ThereferenceoscillatorisenabledbysettingthebitM0ROENintheTKM0C1registerto"1".ThekeyoscillatorisenabledbysettingthebitM0KOENintheTKM0C1registerto"1".

Ifthetimeslotcounterisoverflow,aninterruptwilloccur.

Mux.

Touch Key (1 Set = Touch Key*4)

KEY2

KEY3

KEY4

16-bit C/F Counter Overflow

KeyOsc

KeyOsc

KeyOsc

KeyOsc

KEY1

Filter Frequency Doubling

16-bit CounterfSYS/1,fSYS/2,fSYS/4,fSYS/6,fSYS/8 Overflow

Ref Osc Mux.fSYS/4

8-bit time slot timer counter

5-bit time slot counter Overflow

Overflow 8-bit time slot Timer counter preload register

Note:1.Thedottedlinesshowtheportionsthateachtouchkeyindividuallyhas.2.FortheBS83A02A-4,thereareonlytwotouchkeysinonesetandthereisnofilter.

Touch Key Module Block Diagram




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Touch Key or I/O Function Selection

Touch Key InterruptThetouchkeymodule,whichconsistsoftwoorfourtouchkeys,hasoneinterrupt.Ifthetimeslotcounteroverflows,aninterruptwilloccur.Atthesametime,the16-bitC/Fcounter,16-bitcounter,5-bittimeslotand8-bittimeslottimercounterwillautooff.Onlywhenalltheenabledtouchkeysoverflow,aninterruptwilloccur.Moredetailsregardingthetouchkeyinterruptarelocatedintheinterruptsectionofthedatasheet.

Programming ConsiderationsAftertherelevantregistersaresetup,thetouchkeydetectionprocessisinitiatedthechangingtheTKSTbitfromlowtohigh.Thiswillenableandsynchroniseallrelevantoscillators.TheTKRCOVflag,whichisthetimeslotcounterflagwillgohighandremainhighuntil thecounteroverflows.Whenthishappensaninterruptsignalwillbegenerated.

When theexternal touchkeysizeand layoutaredefined, their relatedcapacitanceswill thendeterminethesensoroscillatorfrequency.




InterruptsInterruptsareanimportantpartofanymicrocontrollersystem.WhenanexternaleventoraninternalfunctionsuchasaTouchActionorTimer/EventCounteroverflowrequiresmicrocontrollerattention,theircorrespondinginterruptwillenforcea temporarysuspensionof themainprogramallowingthemicrocontroller todirectattentiontotheirrespectiveneeds.Thedevicescontainoneexternalinterruptandseveralinternalinterruptfunctions.TheexternalinterruptisgeneratedbytheactionoftheexternalINTpin,whiletheinternalinterruptsaregeneratedbyvariousinternalfunctionssuchastheTouchKeys,Timer/EventCounterandTimeBase.

Interrupt RegistersOverall interrupt control,whichbasicallymeans the settingof request flagswhen certainmicrocontrollerconditionsoccurandthesettingofinterruptenablebitsbytheapplicationprogram,iscontrolledbyaseriesofregisters,locatedintheSpecialPurposeDataMemory,asshownintheaccompanying table.Thenumberofregistersdependsuponthedevicechosenbutfall into twocategories.ThefirstistheINTC0~INTC1registerswhichsetuptheprimaryinterrupts,thesecondistheINTEGregisterwhichsetupstheexternalinterrupttriggeredgetype.

Eachregistercontainsanumberofenablebits toenableordisable individual interruptsaswellasinterruptflagstoindicatethepresenceofaninterruptrequest.Thenamingconventionofthesefollowsaspecificpattern.Firstislistedanabbreviatedinterrupttype,thenthe(optional)numberofthatinterruptfollowedbyeitheran"E"forenable/disablebitor"F"forrequestflag.

Function Enable Bit Request FlagGlobal EMI —

INT Pin INTE INTF

Touch Key Module TKME TKMF

Timer/Event Counter TE TF

Time Base TBE TBF

Interrupt Register Bit Naming Conventions

NameBit

7 6 5 4 3 2 1 0INTEG — — — — — — INTS1 INTS0INTC0 — TF TKMF INTF TE TKME INTE EMIINTC1 — — TBF — — — TBE —

Interrupt Register Contents

INTEG Register Bit 7 6 5 4 3 2 1 0

Name — — — — — — INTS1 INTS0R/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 INT2S1~INT2S0:InterruptedgecontrolforINTpin

00:Disable01:Risingedge10:Fallingedge11:Bothrisingandfallingedge




INTC0 Register Bit 7 6 5 4 3 2 1 0

Name — TF TKMF INTF TE TKME INTE EMIR/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 0 0 0 0 0

Bit7 Unimplemented,readas"0"Bit6 TF:Timer/EventCounterinterruptrequestFlag

0:Norequest1:Interruptrequest

Bit5 TKMF:TouchKeymoduleinterruptrequestflag0:Norequest1:Interruptrequest

Bit4 INTF:INTpininterruptrequestflag0:Norequest1:Interruptrequest

Bit3 TE:Timer/EventCounterinterruptcontrol0:Disable1:Enable

Bit2 TKME:TouchKeymoduleinterruptcontrol0:Disable1:Enable

Bit1 INTE:INTinterruptcontrol0:Disable1:Enable

Bit0 EMI:Globalinterruptcontrol0:Disable1:Enable

INTC1 Register Bit 7 6 5 4 3 2 1 0

Name — — TBF — — — TBE —R/W — — R/W — — — R/W —POR — — 0 — — — 0 —

Bit7~6 Unimplemented,readas"0"Bit5 TBF:TimeBaseinterruptrequestflag

0:Norequest1:Interruptrequest

Bit4~2 Unimplemented,readas"0"Bit1 TBE:TimeBaseinterruptControl

0:Disable1:Enable

Bit0 Unimplemented,readas"0"




Interrupt OperationWhentheconditionsforaninterrupteventoccur,suchasaTouchKeyCounteroverflow,Timer/EventCounteroverflow,etc.,therelevantinterruptrequestflagwillbeset.Whethertherequestflagactuallygeneratesaprogramjumptotherelevantinterruptvectorisdeterminedbytheconditionoftheinterruptenablebit.Iftheenablebitissethighthentheprogramwilljumptoitsrelevantvector;iftheenablebitiszerothenalthoughtheinterruptrequestflagissetanactualinterruptwillnotbegeneratedandtheprogramwillnotjumptotherelevantinterruptvector.Theglobalinterruptenablebit,ifclearedtozero,willdisableallinterrupts.

Whenaninterruptisgenerated,theProgramCounter,whichstorestheaddressofthenextinstructiontobeexecuted,willbetransferredontothestack.TheProgramCounterwillthenbeloadedwithanewaddresswhichwillbethevalueofthecorrespondinginterruptvector.Themicrocontrollerwillthenfetchitsnextinstructionfromthisinterruptvector.TheinstructionatthisvectorwillusuallybeaJMPinstructionwhichwilljumptoanothersectionofprogramwhichisknownastheinterruptserviceroutine.Hereislocatedthecodetocontroltheappropriateinterrupt.Theinterruptserviceroutinemustbeterminatedwitha"RETI",whichretrievestheoriginalProgramCounteraddressfromthestackandallowsthemicrocontrollertocontinuewithnormalexecutionatthepointwheretheinterruptoccurred.

Thevarious interruptenablebits, togetherwith theirassociatedrequest flags,areshownin theaccompanyingdiagramswith theirorderofpriority.These interrupt sourceshave theirownindividualvector.Onceaninterruptsubroutineisserviced,alltheotherinterruptswillbeblocked,astheglobalinterruptenablebit,EMIbitwillbeclearedautomatically.Thiswillpreventanyfurtherinterruptnestingfromoccurring.However, ifother interruptrequestsoccurduring this interval,althoughtheinterruptwillnotbeimmediatelyserviced,therequestflagwillstillberecorded.

Ifaninterruptrequiresimmediateservicingwhiletheprogramisalreadyinanotherinterruptserviceroutine,theEMIbitshouldbesetafterenteringtheroutine,toallowinterruptnesting.Ifthestackisfull,theinterruptrequestwillnotbeacknowledged,eveniftherelatedinterruptisenabled,untiltheStackPointerisdecremented.

If immediate service isdesired, the stackmustbeprevented frombecoming full. Incaseofsimultaneousrequests, theaccompanyingdiagramshows thepriority that isapplied.Allof theinterruptrequest flagswhensetwillwake-upthedevices if theyare inSLEEPorIDLEMode,however topreventawake-upfromoccurring thecorrespondingflagshouldbesetbefore thedevicesareinSLEEPorIDLEMode.

External

Touch Key Module

INTF

TKMF

INTE

TKME

EMI 04H

EMI 08H

14HTime Base TBF TBE EMI

Interrupt Name

Request Flags

Enable Bits

Master Enable Vector

EMI auto disabled in ISR

Low

PriorityHigh

xxE Enable Bits

xxF Request Flag, auto reset in ISR

LegendxxF Request Flag, no auto reset in ISR

0CHTimer/Event Counter TF TE EMI

Interrupt Structure




External InterruptTheexternal interrupt iscontrolledbysignal transitionson the INTpin.Anexternal interruptrequestwill takeplacewhen theexternal interrupt request flag, INTF, isset,whichwilloccurwhenatransition,whosetypeischosenbytheedgeselectbits,appearsontheexternal interruptpin.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andrespectiveexternalinterruptenablebit,INTE,mustfirstbeset.Additionallythecorrect interruptedgetypemustbeselectedusingtheINTEGregister toenable theexternalinterruptfunctionandtochoosethetriggeredgetype.Astheexternalinterruptpinispin-sharedwithI/Opin,itcanonlybeconfiguredasexternalinterruptpiniftheexternalinterruptenablebitinthecorrespondinginterruptregisterhasbeenset.Thepinmustalsobesetupasaninputbysettingthecorrespondingbitintheportcontrolregister.Whentheinterruptisenabled,thestackisnotfullandthecorrecttransitiontypeappearsontheexternalinterruptpin,asubroutinecalltotheexternalinterruptvector,willtakeplace.Whentheinterruptisserviced,theexternalinterruptrequestflag,INTF,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.Notethatanypull-highresistorselectionsontheexternalinterruptpinwillremainvalidevenifthepinisusedasanexternalinterruptinput.

TheINTEGregisterisusedtoselectthetypeofactiveedgethatwilltriggertheexternalinterrupt.Achoiceofeitherrisingorfallingorbothedgetypescanbechosentotriggeranexternalinterrupt.NotethattheINTEGregistercanalsobeusedtodisabletheexternalinterruptfunction.

Touch Key InterruptForaTouchKeyinterrupt tooccur, theglobal interruptenablebit,EMI,andthecorrespondingTouchKeyinterruptenableTKMEmustbefirstset.AnactualTouchKeyinterruptwilltakeplacewhentheTouchKeyrequestflag,TKMF,isset,asituationthatwilloccurwhenthetimeslotcounterintherelevantTouchKeymoduleoverflows.Whentheinterruptisenabled,thestackisnotfullandtheTouchKeytimeslotcounteroverflowoccurs,asubroutinecall totherelevant timerinterruptvector,willtakeplace.Whentheinterruptisserviced,theTouchKeyinterruptrequestflag,TKMF,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.

Timer/Event Counter InterruptFor aTimer/EventCounter interrupt tooccur, theglobal interrupt enablebit,EMI, and thecorresponding timer interruptenablebit,TEmust firstbeset.AnactualTimer/EventCounterinterruptwilltakeplacewhentheTimer/EventCounterrequestflag,TF,isset,asituationthatwilloccurwhentherelevantTimer/EventCounteroverflows.Whentheinterruptisenabled,thestackisnotfullandaTimer/EventCounteroverflowoccurs,asubroutinecalltotherelevanttimerinterruptvector,will takeplace.Whentheinterruptisserviced,thetimerinterruptrequestflag,TF,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.

Time Base InterruptTimeBaseInterruptfunctionistoprovideregulartimesignalintheformofaninternalinterrupt.It iscontrolledbytheoverflowsignalfromitsrespective timerfunction.Whenthishappens itsrespectiveinterruptrequestflag,TBF,willbeset.Toallowtheprogramtobranchtotheirrespectiveinterruptvectoraddresses, theglobal interruptenablebit,EMIandTimeBaseenablebit,TBE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandtheTimeBaseoverflows,asubroutinecalltotheirrespectivevectorlocationswilltakeplace.Whentheinterruptisserviced,therespectiveinterruptrequestflag,TBF,willbeautomaticallyresetandtheEMIbitwillbeclearedtodisableotherinterrupts.




ThepurposeoftheTimeBaseInterruptistoprovideaninterruptsignalatfixedtimeperiods.Theirclocksourcesoriginate fromthe internalclocksourcefSYSor fSUB selectedby theTSbit in theTMRCregister.Theinputclockpassesthroughadivider,thedivisionratioofwhichisselectedbyprogrammingtheappropriatebitsintheTBCregistertoobtainlongerinterruptperiodswhosevalueranges.TheclocksourcethatgeneratesfTP,whichinturncontrolstheTimeBaseinterruptperiod,canoriginatefromseveraldifferentsources,asshownintheSystemOperatingModesection.

TBC Register Bit 7 6 5 4 3 2 1 0

Name — — TB1 TB0 — — — —R/W — — R/W R/W — — — —POR — — 0 0 — — — —

Bit7~6 Unimplemented,readas"0"Bit5~4 TB1~TB0:SelectTimeBaseTime-outPeriod

00:1024/fTP

01:2048/fTP

10:4096/fTP

11:8192/fTP

Bit3~0 Unimplemented,readas"0"

MUX Time BasefTPfSYS

fSUB

TB1-TB0

TS

÷ 210~213

Time Base Structure

Interrupt Wake-up FunctionEachof the interruptfunctionshas thecapabilityofwakingupthemicrocontrollerwhenin theSLEEPorIDLEMode.Awake-upisgeneratedwhenaninterruptrequestflagchangesfromlowtohighandis independentofwhethertheinterruptisenabledornot.Therefore,eventhoughthedevicesare intheSLEEPorIDLEModeandtheirsystemoscillatorisstopped,situationssuchasexternaledgetransitionsontheexternalinterruptpins,alowpowersupplyvoltageormaycausetheir respective interrupt flag tobesethighandconsequentlygeneratean interrupt.Caremustthereforebetakenifspuriouswake-upsituationsaretobeavoided.Ifaninterruptwake-upfunctionistobedisabledthenthecorrespondinginterruptrequestflagshouldbesethighbeforethedeviceenterstheSLEEPorIDLEMode.Theinterruptenablebitshavenoeffectontheinterruptwake-upfunction.




Programming ConsiderationsBydisablingtherelevantinterruptenablebits,arequestedinterruptcanbepreventedfrombeingserviced,however,oncean interrupt request flag is set, itwill remain in thiscondition in theinterruptregisteruntilthecorrespondinginterruptisservicedoruntiltherequestflagisclearedbyasoftwareinstruction.

It isrecommendedthatprogramsdonotusethe"CALL"instructionwithintheinterruptservicesubroutine.Interruptsoftenoccurinanunpredictablemannerorneedtobeservicedimmediately.Ifonlyonestackisleftandtheinterruptisnotwellcontrolled,theoriginalcontrolsequencewillbedamagedonceaCALLsubroutineisexecutedintheinterruptsubroutine.

Everyinterrupthasthecapabilityofwakingupthemicrocontrollerwhenit isinSLEEPorIDLEMode,thewakeupbeinggeneratedwhentheinterruptrequestflagchangesfromlowtohigh.IfitisrequiredtopreventacertaininterruptfromwakingupthemicrocontrollerthenitsrespectiverequestflagshouldbefirstsethighbeforeenteringtheSLEEPorIDLEMode.

AsonlytheProgramCounter ispushedontothestack, thenwhentheinterrupt isserviced, if thecontentsof theaccumulator,statusregisterorotherregistersarealteredbythe interruptserviceprogram,theircontentsshouldbesavedinadvance.

Toreturnfromaninterruptsubroutine,eitheraRETorRETIinstructionmaybeexecuted.TheRETIinstructioninadditiontoexecutingareturntothemainprogramalsoautomaticallysetstheEMIbithightoallowfurtherinterrupts.TheRETinstructionhoweveronlyexecutesareturntothemainprogramleavingtheEMIbitinitspresentzerostateandthereforedisablingtheexecutionoffurtherinterrupts.




Application Circuits

BS83A02A-4

VDD

VSS

VDD

0.1uF

PA1/Key1

PA3/Key2

PAD

PADPA2

PA0/INT Control Device

VDD

VSS

PA2

VDD

0.1uF

VDD VDD

PA0/INTPA1/Key1

PA3/Key2

PAD

PAD




BS83A04A-3/BS83A04A-4

VDD

VSS

VDD

0.1uF

PA5/Key1

PA1/Key2

PA4/Key4

VDD

VSS

PA7

PA2

VDD

0.1uF

PA6

VDD VDD VDD

PAD

PAD

PAD

PA0/INT

VDD

PAD PA3/Key3

PA5/Key1

PA1/Key2

PA4/Key4

PAD

PAD

PAD

PAD PA3/Key3

PA7

PA2

PA6

PA0/INTControl Device




Instruction Set

IntroductionCentral to thesuccessfuloperationofanymicrocontroller is its instructionset,whichisasetofprograminstructioncodesthatdirectsthemicrocontrollertoperformcertainoperations.InthecaseofHoltekmicrocontroller,acomprehensiveandflexiblesetofover60instructionsisprovidedtoenableprogrammerstoimplementtheirapplicationwiththeminimumofprogrammingoverheads.

Foreasierunderstandingofthevariousinstructioncodes, theyhavebeensubdividedintoseveralfunctionalgroupings.

Instruction TimingMostinstructionsareimplementedwithinoneinstructioncycle.Theexceptionstothisarebranch,call,or tablereadinstructionswheretwoinstructioncyclesarerequired.Oneinstructioncycleisequalto4systemclockcycles,thereforeinthecaseofan8MHzsystemoscillator,mostinstructionswouldbeimplementedwithin0.5μsandbranchorcall instructionswouldbeimplementedwithin1μs.Although instructionswhichrequireonemorecycle to implementaregenerally limited totheJMP,CALL,RET,RETIandtablereadinstructions, it is important torealize thatanyotherinstructionswhichinvolvemanipulationoftheProgramCounterLowregisterorPCLwillalsotakeonemorecycletoimplement.AsinstructionswhichchangethecontentsofthePCLwill implyadirect jumptothatnewaddress,onemorecyclewillberequired.Examplesofsuchinstructionswouldbe"CLRPCL"or"MOVPCL,A".Forthecaseofskipinstructions,itmustbenotedthatiftheresultofthecomparisoninvolvesaskipoperationthenthiswillalsotakeonemorecycle,ifnoskipisinvolvedthenonlyonecycleisrequired.

Moving and Transferring DataThe transferofdatawithin themicrocontrollerprogram isoneof themost frequentlyusedoperations.MakinguseofthreekindsofMOVinstructions,datacanbetransferredfromregisterstotheAccumulatorandvice-versaaswellasbeingabletomovespecificimmediatedatadirectlyintotheAccumulator.Oneofthemostimportantdatatransferapplicationsis toreceivedatafromtheinputportsandtransferdatatotheoutputports.

Arithmetic OperationsTheabilitytoperformcertainarithmeticoperationsanddatamanipulationisanecessaryfeatureofmostmicrocontrollerapplications.WithintheHoltekmicrocontrollerinstructionsetarearangeofaddandsubtract instructionmnemonicstoenablethenecessaryarithmetictobecarriedout.Caremustbe taken toensurecorrecthandlingofcarryandborrowdatawhenresultsexceed255foradditionandlessthan0forsubtraction.TheincrementanddecrementinstructionsINC,INCA,DECandDECAprovideasimplemeansofincreasingordecreasingbyavalueofoneofthevaluesinthedestinationspecified.




Logical and Rotate OperationThestandardlogicaloperationssuchasAND,OR,XORandCPLallhavetheirowninstructionwithintheHoltekmicrocontroller instructionset.Aswiththecaseofmost instructionsinvolvingdatamanipulation, datamust pass through theAccumulatorwhichmay involve additionalprogrammingsteps. Inall logicaldataoperations, thezero flagmaybeset if the resultof theoperationiszero.AnotherformoflogicaldatamanipulationcomesfromtherotateinstructionssuchasRR,RL,RRCandRLCwhichprovideasimplemeansofrotatingonebitrightorleft.Differentrotateinstructionsexistdependingonprogramrequirements.Rotateinstructionsareusefulforserialportprogrammingapplicationswheredatacanberotatedfromaninternalregister intotheCarrybitfromwhereitcanbeexaminedandthenecessaryserialbitsethighorlow.Anotherapplicationwhichrotatedataoperationsareusedistoimplementmultiplicationanddivisioncalculations.

Branches and Control TransferProgrambranchingtakestheformofeitherjumpstospecifiedlocationsusingtheJMPinstructionor toa subroutineusing theCALL instruction.Theydiffer in the sense that in thecaseofasubroutinecall, theprogrammustreturn to the instruction immediatelywhenthesubroutinehasbeencarriedout.Thisisdonebyplacingareturninstruction"RET"inthesubroutinewhichwillcausetheprogramtojumpbacktotheaddressrightaftertheCALLinstruction.InthecaseofaJMPinstruction,theprogramsimplyjumpstothedesiredlocation.ThereisnorequirementtojumpbacktotheoriginaljumpingoffpointasinthecaseoftheCALLinstruction.Onespecialandextremelyusefulsetofbranchinstructionsaretheconditionalbranches.Hereadecisionisfirstmaderegardingtheconditionofacertaindatamemoryor individualbits.Dependingupon theconditions, theprogramwillcontinuewiththenextinstructionorskipoveritandjumptothefollowinginstruction.These instructionsare thekey todecisionmakingandbranchingwithin theprogramperhapsdeterminedbytheconditionofcertaininputswitchesorbytheconditionofinternaldatabits.

Bit OperationsTheabilitytoprovidesinglebitoperationsonDataMemoryisanextremelyflexiblefeatureofallHoltekmicrocontrollers.Thisfeature isespeciallyusefulforoutputportbitprogrammingwhereindividualbitsorportpinscanbedirectlysethighorlowusingeitherthe"SET[m].i"or"CLR[m].i" instructionsrespectively.Thefeatureremovestheneedforprogrammers tofirstreadthe8-bitoutputport,manipulatetheinputdatatoensurethatotherbitsarenotchangedandthenoutputtheportwiththecorrectnewdata.Thisread-modify-writeprocessistakencareofautomaticallywhenthesebitoperationinstructionsareused.

Table Read OperationsDatastorage isnormally implementedbyusing registers.However,whenworkingwith largeamountsoffixeddata, thevolumeinvolvedoftenmakesit inconvenienttostorethefixeddataintheDataMemory.Toovercomethisproblem,HoltekmicrocontrollersallowanareaofProgramMemory tobesetasa tablewheredatacanbedirectlystored.Asetofeasy touse instructionsprovides themeansbywhich this fixeddatacanbereferencedandretrievedfromtheProgramMemory.

Other OperationsInaddition to theabovefunctional instructions,a rangeofother instructionsalsoexistsuchasthe"HALT"instructionforPower-downoperationsand instructions tocontrol theoperationoftheWatchdogTimerfor reliableprogramoperationsunderextremeelectricorelectromagneticenvironments.Fortheirrelevantoperations,refertothefunctionalrelatedsections.




Instruction Set SummaryThefollowingtabledepictsasummaryoftheinstructionsetcategorisedaccordingtofunctionandcanbeconsultedasabasicinstructionreferenceusingthefollowinglistedconventions.

Table Conventionsx:Bitsimmediatedatam:DataMemoryaddressA:Accumulatori:0~7numberofbitsaddr:Programmemoryaddress

Mnemonic Description Cycles Flag AffectedArithmeticADD A,[m] Add Data Memory to ACC 1 Z, C, AC, OVADDM A,[m] Add ACC to Data Memory 1Note Z, C, AC, OVADD A,x Add immediate data to ACC 1 Z, C, AC, OVADC A,[m] Add Data Memory to ACC with Carry 1 Z, C, AC, OVADCM A,[m] Add ACC to Data memory with Carry 1Note Z, C, AC, OVSUB A,x Subtract immediate data from the ACC 1 Z, C, AC, OVSUB A,[m] Subtract Data Memory from ACC 1 Z, C, AC, OVSUBM A,[m] Subtract Data Memory from ACC with result in Data Memory 1Note Z, C, AC, OVSBC A,[m] Subtract Data Memory from ACC with Carry 1 Z, C, AC, OVSBCM A,[m] Subtract Data Memory from ACC with Carry, result in Data Memory 1Note Z, C, AC, OVDAA [m] Decimal adjust ACC for Addition with result in Data Memory 1Note CLogic OperationAND A,[m] Logical AND Data Memory to ACC 1 ZOR A,[m] Logical OR Data Memory to ACC 1 ZXOR A,[m] Logical XOR Data Memory to ACC 1 ZANDM A,[m] Logical AND ACC to Data Memory 1Note ZORM A,[m] Logical OR ACC to Data Memory 1Note ZXORM A,[m] Logical XOR ACC to Data Memory 1Note ZAND A,x Logical AND immediate Data to ACC 1 ZOR A,x Logical OR immediate Data to ACC 1 ZXOR A,x Logical XOR immediate Data to ACC 1 ZCPL [m] Complement Data Memory 1Note ZCPLA [m] Complement Data Memory with result in ACC 1 ZIncrement & DecrementINCA [m] Increment Data Memory with result in ACC 1 ZINC [m] Increment Data Memory 1Note ZDECA [m] Decrement Data Memory with result in ACC 1 ZDEC [m] Decrement Data Memory 1Note ZRotateRRA [m] Rotate Data Memory right with result in ACC 1 NoneRR [m] Rotate Data Memory right 1Note NoneRRCA [m] Rotate Data Memory right through Carry with result in ACC 1 CRRC [m] Rotate Data Memory right through Carry 1Note CRLA [m] Rotate Data Memory left with result in ACC 1 NoneRL [m] Rotate Data Memory left 1Note NoneRLCA [m] Rotate Data Memory left through Carry with result in ACC 1 CRLC [m] Rotate Data Memory left through Carry 1Note C




Mnemonic Description Cycles Flag AffectedData MoveMOV A,[m] Move Data Memory to ACC 1 NoneMOV [m],A Move ACC to Data Memory 1Note NoneMOV A,x Move immediate data to ACC 1 NoneBit OperationCLR [m].i Clear bit of Data Memory 1Note NoneSET [m].i Set bit of Data Memory 1Note NoneBranchJMP addr Jump unconditionally 2 NoneSZ [m] Skip if Data Memory is zero 1Note NoneSZA [m] Skip if Data Memory is zero with data movement to ACC 1Note NoneSZ [m].i Skip if bit i of Data Memory is zero 1Note NoneSNZ [m].i Skip if bit i of Data Memory is not zero 1Note NoneSIZ [m] Skip if increment Data Memory is zero 1Note NoneSDZ [m] Skip if decrement Data Memory is zero 1Note NoneSIZA [m] Skip if increment Data Memory is zero with result in ACC 1Note NoneSDZA [m] Skip if decrement Data Memory is zero with result in ACC 1Note NoneCALL addr Subroutine call 2 NoneRET Return from subroutine 2 NoneRET A,x Return from subroutine and load immediate data to ACC 2 NoneRETI Return from interrupt 2 NoneTable ReadTABRD [m] Read table (specific page) to TBLH and Data Memory 2Note NoneTABRDC [m] Read table (current page) to TBLH and Data Memory 2Note NoneTABRDL [m] Read table (last page) to TBLH and Data Memory 2Note NoneMiscellaneousNOP No operation 1 NoneCLR [m] Clear Data Memory 1Note NoneSET [m] Set Data Memory 1Note NoneCLR WDT Clear Watchdog Timer 1 TO, PDFCLR WDT1 Pre-clear Watchdog Timer 1 TO, PDFCLR WDT2 Pre-clear Watchdog Timer 1 TO, PDFSWAP [m] Swap nibbles of Data Memory 1Note NoneSWAPA [m] Swap nibbles of Data Memory with result in ACC 1 NoneHALT Enter power down mode 1 TO, PDFNote:1.Forskipinstructions,iftheresultofthecomparisoninvolvesaskipthentwocyclesarerequired,ifno

skiptakesplaceonlyonecycleisrequired.2.AnyinstructionwhichchangesthecontentsofthePCLwillalsorequire2cyclesforexecution.3.For the"CLRWDT1"and"CLRWDT2"instructions theTOandPDFflagsmaybeaffectedbytheexecution status.TheTOandPDF flagsareclearedafterboth "CLRWDT1"and"CLRWDT2"instructionsareconsecutivelyexecuted.OtherwisetheTOandPDFflagsremainunchanged.




Instruction Definition

ADC A,[m] AddDataMemorytoACCwithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]+CAffectedflag(s) OV,Z,AC,C

ADCM A,[m] AddACCtoDataMemorywithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]+CAffectedflag(s) OV,Z,AC,C

ADD A,[m] AddDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]Affectedflag(s) OV,Z,AC,C

ADD A,x AddimmediatedatatoACCDescription ThecontentsoftheAccumulatorandthespecifiedimmediatedataareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+xAffectedflag(s) OV,Z,AC,C

ADDM A,[m] AddACCtoDataMemoryDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]Affectedflag(s) OV,Z,AC,C

AND A,[m] LogicalANDDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″[m]Affectedflag(s) Z

AND A,x LogicalANDimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″xAffectedflag(s) Z

ANDM A,[m] LogicalANDACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalAND operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″AND″[m]Affectedflag(s) Z




CALL addr SubroutinecallDescription Unconditionallycallsasubroutineatthespecifiedaddress.TheProgramCounterthen incrementsby1toobtaintheaddressofthenextinstructionwhichisthenpushedontothe stack.Thespecifiedaddressisthenloadedandtheprogramcontinuesexecutionfromthis newaddress.Asthisinstructionrequiresanadditionaloperation,itisatwocycleinstruction.Operation Stack←ProgramCounter+1 ProgramCounter←addrAffectedflag(s) None

CLR [m] ClearDataMemoryDescription EachbitofthespecifiedDataMemoryisclearedto0.Operation [m]←00HAffectedflag(s) None

CLR [m].i ClearbitofDataMemoryDescription BitiofthespecifiedDataMemoryisclearedto0.Operation [m].i←0Affectedflag(s) None

CLR WDT ClearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CLR WDT1 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksin conjunctionwithCLRWDT2andmustbeexecutedalternatelywithCLRWDT2tohave effect.RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT2will havenoeffect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CLR WDT2 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksinconjunction withCLRWDT1andmustbeexecutedalternatelywithCLRWDT1tohaveeffect. RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT1willhaveno effect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CPL [m] ComplementDataMemoryDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Operation [m]←[m]Affectedflag(s) Z




CPLA [m] ComplementDataMemorywithresultinACCDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Thecomplementedresultisstoredin theAccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]Affectedflag(s) Z

DAA [m] Decimal-AdjustACCforadditionwithresultinDataMemoryDescription ConvertthecontentsoftheAccumulatorvaluetoaBCD(BinaryCodedDecimal)value resultingfromthepreviousadditionoftwoBCDvariables.Ifthelownibbleisgreaterthan9 orifACflagisset,thenavalueof6willbeaddedtothelownibble.Otherwisethelownibble remainsunchanged.Ifthehighnibbleisgreaterthan9oriftheCflagisset,thenavalueof6 willbeaddedtothehighnibble.Essentially,thedecimalconversionisperformedbyadding 00H,06H,60Hor66HdependingontheAccumulatorandflagconditions.OnlytheCflag maybeaffectedbythisinstructionwhichindicatesthatiftheoriginalBCDsumisgreaterthan 100,itallowsmultipleprecisiondecimaladdition.Operation [m]←ACC+00Hor [m]←ACC+06Hor [m]←ACC+60Hor [m]←ACC+66HAffectedflag(s) C

DEC [m] DecrementDataMemoryDescription DatainthespecifiedDataMemoryisdecrementedby1.Operation [m]←[m]−1Affectedflag(s) Z

DECA[m] DecrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisdecrementedby1.Theresultisstoredinthe Accumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]−1Affectedflag(s) Z

HALT EnterpowerdownmodeDescription Thisinstructionstopstheprogramexecutionandturnsoffthesystemclock.Thecontentsof theDataMemoryandregistersareretained.TheWDTandprescalerarecleared.Thepower downflagPDFissetandtheWDTtime-outflagTOiscleared.Operation TO←0 PDF←1Affectedflag(s) TO,PDF

INC [m] IncrementDataMemoryDescription DatainthespecifiedDataMemoryisincrementedby1.Operation [m]←[m]+1Affectedflag(s) Z

INCA [m] IncrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisincrementedby1.TheresultisstoredintheAccumulator. ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]+1Affectedflag(s) Z




JMP addr JumpunconditionallyDescription ThecontentsoftheProgramCounterarereplacedwiththespecifiedaddress.Program executionthencontinuesfromthisnewaddress.Asthisrequirestheinsertionofadummy instructionwhilethenewaddressisloaded,itisatwocycleinstruction.Operation ProgramCounter←addrAffectedflag(s) None

MOV A,[m] MoveDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Operation ACC←[m]Affectedflag(s) None

MOV A,x MoveimmediatedatatoACCDescription TheimmediatedataspecifiedisloadedintotheAccumulator.Operation ACC←xAffectedflag(s) None

MOV [m],A MoveACCtoDataMemoryDescription ThecontentsoftheAccumulatorarecopiedtothespecifiedDataMemory.Operation [m]←ACCAffectedflag(s) None

NOP NooperationDescription Nooperationisperformed.Executioncontinueswiththenextinstruction.Operation NooperationAffectedflag(s) None

OR A,[m] LogicalORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwise logicalORoperation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″[m]Affectedflag(s) Z

OR A,x LogicalORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″xAffectedflag(s) Z

ORM A,[m] LogicalORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″OR″[m]Affectedflag(s) Z

RET ReturnfromsubroutineDescription TheProgramCounterisrestoredfromthestack.Programexecutioncontinuesattherestored address.Operation ProgramCounter←StackAffectedflag(s) None




RET A,x ReturnfromsubroutineandloadimmediatedatatoACCDescription TheProgramCounterisrestoredfromthestackandtheAccumulatorloadedwiththespecified immediatedata.Programexecutioncontinuesattherestoredaddress.Operation ProgramCounter←Stack ACC←xAffectedflag(s) None

RETI ReturnfrominterruptDescription TheProgramCounterisrestoredfromthestackandtheinterruptsarere-enabledbysettingthe EMIbit.EMIisthemasterinterruptglobalenablebit.Ifaninterruptwaspendingwhenthe RETIinstructionisexecuted,thependingInterruptroutinewillbeprocessedbeforereturning tothemainprogram.Operation ProgramCounter←Stack EMI←1Affectedflag(s) None

RL [m] RotateDataMemoryleftDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←[m].7Affectedflag(s) None

RLA [m] RotateDataMemoryleftwithresultinACCDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0. TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremain unchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←[m].7Affectedflag(s) None

RLC [m] RotateDataMemoryleftthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←C C←[m].7Affectedflag(s) C

RLCA [m] RotateDataMemoryleftthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7replacesthe Carrybitandtheoriginalcarryflagisrotatedintothebit0.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←C C←[m].7Affectedflag(s) C

RR [m] RotateDataMemoryrightDescription ThecontentsofthespecifiedDataMemoryarerotatedrightby1bitwithbit0rotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←[m].0Affectedflag(s) None




RRA [m] RotateDataMemoryrightwithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bitwithbit0 rotatedintobit7.TherotatedresultisstoredintheAccumulatorandthecontentsofthe DataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←[m].0Affectedflag(s) None

RRC [m] RotateDataMemoryrightthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←C C←[m].0Affectedflag(s) C

RRCA [m] RotateDataMemoryrightthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0replaces theCarrybitandtheoriginalcarryflagisrotatedintobit7.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←C C←[m].0Affectedflag(s) C

SBC A,[m] SubtractDataMemoryfromACCwithCarryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheAccumulator.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]−CAffectedflag(s) OV,Z,AC,C

SBCM A,[m] SubtractDataMemoryfromACCwithCarryandresultinDataMemoryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheDataMemory.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]−CAffectedflag(s) OV,Z,AC,C

SDZ [m] SkipifdecrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]−1 Skipif[m]=0Affectedflag(s) None




SDZA [m] SkipifdecrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0, theprogramproceedswiththefollowinginstruction.Operation ACC←[m]−1 SkipifACC=0Affectedflag(s) None

SET [m] SetDataMemoryDescription EachbitofthespecifiedDataMemoryissetto1.Operation [m]←FFHAffectedflag(s) None

SET [m].i SetbitofDataMemoryDescription BitiofthespecifiedDataMemoryissetto1.Operation [m].i←1Affectedflag(s) None

SIZ [m] SkipifincrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]+1 Skipif[m]=0Affectedflag(s) None

SIZA [m] SkipifincrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot 0theprogramproceedswiththefollowinginstruction.Operation ACC←[m]+1 SkipifACC=0Affectedflag(s) None

SNZ [m].i SkipifbitiofDataMemoryisnot0Description IfbitiofthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i≠0Affectedflag(s) None

SUB A,[m] SubtractDataMemoryfromACCDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheAccumulator.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]Affectedflag(s) OV,Z,AC,C




SUBM A,[m] SubtractDataMemoryfromACCwithresultinDataMemoryDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheDataMemory.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]Affectedflag(s) OV,Z,AC,C

SUB A,x SubtractimmediatedatafromACCDescription TheimmediatedataspecifiedbythecodeissubtractedfromthecontentsoftheAccumulator. TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionisnegative,theC flagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−xAffectedflag(s) OV,Z,AC,C

SWAP [m] SwapnibblesofDataMemoryDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.Operation [m].3~[m].0↔[m].7~[m].4Affectedflag(s) None

SWAPA [m] SwapnibblesofDataMemorywithresultinACCDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.The resultisstoredintheAccumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC.3~ACC.0←[m].7~[m].4 ACC.7~ACC.4←[m].3~[m].0Affectedflag(s) None

SZ [m] SkipifDataMemoryis0Description IfthecontentsofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.Operation Skipif[m]=0Affectedflag(s) None

SZA [m] SkipifDataMemoryis0withdatamovementtoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Ifthevalueiszero, thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstruction whilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0the programproceedswiththefollowinginstruction.Operation ACC←[m] Skipif[m]=0Affectedflag(s) None

SZ [m].i SkipifbitiofDataMemoryis0Description IfbitiofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthisrequires theinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultisnot0,theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i=0Affectedflag(s) None




TABRD [m] Readtable(specificpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(specificpage)addressedbythetablepointerpair (TBHPandTBLP)ismovedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

TABRDC [m] Readtable(currentpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(currentpage)addressedbythetablepointer(TBLP)is movedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

TABRDL [m] Readtable(lastpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(lastpage)addressedbythetablepointer(TBLP)ismoved tothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

XOR A,[m] LogicalXORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″[m]Affectedflag(s) Z

XORM A,[m] LogicalXORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalXOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″XOR″[m]Affectedflag(s) Z

XOR A,x LogicalXORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″xAffectedflag(s) Z




Package Information

Note that thepackage informationprovidedhere is for consultationpurposesonly.As thisinformationmaybeupdatedatregularintervalsusersareremindedtoconsulttheHoltekwebsiteforthelatestversionofthePackage/CartonInformation.

Additionalsupplementaryinformationwithregardtopackagingislistedbelow.Clickontherelevantsectiontobetransferredtotherelevantwebsitepage.

• PackageInformation(includeOutlineDimensions,ProductTapeandReelSpecifications)

• TheOperationInstructionofPackingMaterials

• Cartoninformation

http://www.holtek.com/en/

http://www.holtek.com/en/package_carton_information




6-pin DFN (2mm×2mm) Outline Dimensions

EL

E2

K

e b3

16

4

D D2

A1

A3

A

SymbolDimensions in inch

Min. Nom. Max.

A 0.028 0.030 0.031

A1 0.000 0.001 0.002

A3 — 0.008 BSC —

b 0.010 0.012 0.014

D — 0.079 BSC —

E — 0.079 BSC —

e — 0.026 BSC —

D2 0.053 0.055 0.057

E2 0.022 0.024 0.026

L 0.010 0.012 0.014

K 0.008 — —

SymbolDimensions in mm

Min. Nom. Max.

A 0.700 0.750 0.800

A1 0.000 0.020 0.050

A3 — 0.200 BSC —

b 0.250 0.300 0.350

D — 2.00 BSC —

E — 2.00 BSC —

e — 0.65 BSC —

D2 1.350 1.400 1.450

E2 0.550 0.600 0.650

L 0.250 0.300 0.350

K 0.200 — —




6-pn SOT23-6 Outline Dimensions

H


Min. Nom. Max.A — — 0.057

A1 — — 0.006A2 0.035 0.045 0.051b 0.012 — 0.020C 0.003 — 0.009D — 0.114 BSC —E — 0.063 BSC —e — 0.037 BSC —

e1 — 0.075 BSC —H — 0.110 BSC —L1 — 0.024 BSC —θ 0° — 8°



A1 — — 0.15A2 0.90 1.15 1.30b 0.30 — 0.50C 0.08 — 0.22D — 2.90 BSC —E — 1.60 BSC —e — 0.95 BSC —e1 — 1.90 BSC —H — 2.80 BSC —L1 — 0.60 BSC —θ 0° — 8°




8-pin SOP (150mil) Outline Dimensions

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Min. Nom. Max.A — 0.236 BSC —B — 0.154 BSC —C 0.012 — 0.020C′ — 0.193 BSC —D — — 0.069E — 0.050 BSC —F 0.004 — 0.010G 0.016 — 0.050H 0.004 — 0.010α 0° — 8°


Min. Nom. Max.A — 6.00 BSC —B — 3.90 BSC —C 0.31 — 0.51C′ — 4.90 BSC —D — — 1.75E — 1.27 BSC —F 0.10 — 0.25G 0.40 — 1.27H 0.10 — 0.25α 0° — 8°




10-pin MSOP Outline Dimensions

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A1 0.000 — 0.006A2 0.030 0.033 0.037b 0.007 — 0.013c 0.003 — 0.009D — 0.118 BSC —E — 0.193 BSC —E1 — 0.118 BSC —e — 0.020 BSC —L 0.016 0.024 0.031

L1 — 0.037 BSC —y — 0.004 —α 0° — 8°



A1 0.000 — 0.150A2 0.750 0.850 0.950b 0.170 — 0.330c 0.080 — 0.230D — 3.000 BSC —E — 4.900 BSC —E1 — 3.000 BSC —e — 0.500 BSC —L 0.400 0.600 0.800

L1 — 0.950 BSC —y — 0.1 —α 0° — 8°




16-pin NSOP (150mil) Outline Dimensions

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Min. Nom. Max.A — 0.236 BSC —B — 0.154 BSC —C 0.012 — 0.020 C' — 0.390 BSC —D — — 0.069 E — 0.050 BSC —F 0.004 — 0.010 G 0.016 — 0.050 H 0.004 — 0.010 α 0° ― 8°


Min. Nom. Max.A — 6.000 BSC —B — 3.900 BSC —C 0.31 — 0.51 C' — 9.900 BSC —D — — 1.75 E — 1.270 BSC —F 0.10 — 0.25 G 0.40 — 1.27 H 0.10 — 0.25 α 0° ― 8°




Copyright© 2017 by HOLTEK SEMICONDUCTOR INC.

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

touch i/o flash mcu - 首頁 - holtek€¦ · rev. 1.71 6 april 11, 2017 rev. 1.71 7 april 11, 2017...

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