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Networking Fire Protection Flash MCU

BA45FH0082

Revision: V1.00 Date: st 1 01st 1 01

Rev. 1.00 st 1 01 Rev. 1.00 3 st 1 01

BA45FH0082Networking Fire Protection Flash MCU


Table of Contents

Features ............................................................................................................ 6CPU Featres ......................................................................................................................... 6Peripheral Featres ................................................................................................................. 6Two Line Power Line Data Transceiver Featres ................................................................... 6

General Description ......................................................................................... 7Block Diagram .................................................................................................. 8Pin Assignment ................................................................................................ 9Pin Description .............................................................................................. 10

Internally Connected Pins ......................................................................................................11

Absolute Maximum Ratings .......................................................................... 12D.C. Characteristics ....................................................................................... 12

Operatin Voltae Characteristics ......................................................................................... 1Standby Crrent Characteristics ........................................................................................... 13Operatin Crrent Characteristics ......................................................................................... 13

A.C. Characteristics ....................................................................................... 14Hih Speed Internal Oscillator – HIRC – Freqency ccracy ............................................. 14Low Speed Internal Oscillator Characteristics – LIRC .......................................................... 14Operatin Freqency Characteristic Crves ......................................................................... 1System Start Up Time Characteristics .................................................................................. 1

Input/Output Characteristics ........................................................................ 16Memory Characteristics ................................................................................ 16LVD/LVR Electrical Characteristics .............................................................. 17Reference Voltage Electrical Characteristics .............................................. 17A/D Converter Electrical Characteristics ..................................................... 18Power Line Data Transceiver Electrical Characteristics ............................ 18Power-on Reset Characteristics ................................................................... 19System Architecture ...................................................................................... 20

Clockin and Pipelinin ......................................................................................................... 0Proram Conter ................................................................................................................... 1Stack ..................................................................................................................................... 1rithmetic and Loic Unit – LU ...........................................................................................

Flash Program Memory ................................................................................. 23Strctre ................................................................................................................................ 3Special Vectors ..................................................................................................................... 3Look-p Table ....................................................................................................................... 3Table Proram Example ........................................................................................................ 4In Circit Prorammin – ICP ............................................................................................... On-Chip Deb Spport – OCDS .........................................................................................

Rev. 1.00 st 1 01 Rev. 1.00 3 st 1 01



Data Memory .................................................................................................. 26Strctre ................................................................................................................................ 6General Prpose Data Memory ............................................................................................ Special Prpose Data Memory .............................................................................................

Special Function Register Description ........................................................ 28Indirect ddressin Reisters – IR0 IR1 ......................................................................... 8Memory Pointers – MP0 MP1 .............................................................................................. 8Bank Pointer – BP ................................................................................................................. 9ccmlator – CC .............................................................................................................. 9Proram Conter Low Reister – PCL ................................................................................. 9Look-p Table Reisters – TBLP TBHP TBLH .................................................................... 9Stats Reister – STTUS ................................................................................................... 30

EEPROM Data Memory .................................................................................. 31EEPROM Data Memory Strctre ........................................................................................ 31EEPROM Reisters .............................................................................................................. 31Readin Data from the EEPROM ......................................................................................... 33Writin Data to the EEPROM ................................................................................................ 33Write Protection ..................................................................................................................... 33EEPROM Interrpt ................................................................................................................ 33Prorammin Considerations ................................................................................................ 34

Oscillators ...................................................................................................... 35Oscillator Overview ............................................................................................................... 3System Clock Configurations ............................................................................................... 3Internal RC Oscillator – HIRC .............................................................................................. 36Internal 3kHz Oscillator – LIRC ........................................................................................... 36

Operating Modes and System Clocks ......................................................... 36System Clocks ...................................................................................................................... 36System Operation Modes ...................................................................................................... 3Control Reisters .................................................................................................................. 38Operatin Mode Switchin .................................................................................................... 40Standby Crrent Considerations ........................................................................................... 43Wake-p ................................................................................................................................ 44

Watchdog Timer ............................................................................................. 45Watchdo Timer Clock Sorce .............................................................................................. 4Watchdo Timer Control Reister ......................................................................................... 4Watchdo Timer Operation ................................................................................................... 46

Reset and Initialisation ................................................................................. 47Reset Fnctions .................................................................................................................... 4Reset Initial Conditions ........................................................................................................ 0

Input/Output Ports ........................................................................................ 53Pll-hih Resistors ................................................................................................................ 3Port Wake-p ..................................................................................................................... 4

Rev. 1.00 4 st 1 01 Rev. 1.00 st 1 01



I/O Port Control Reisters ..................................................................................................... 4Pin-shared Fnctions ............................................................................................................ I/O Pin Strctres .................................................................................................................. Prorammin Considerations ............................................................................................... 8

Timer Modules – TM ...................................................................................... 58Introdction ........................................................................................................................... 8TM Operation ........................................................................................................................ 8TM Clock Sorce ................................................................................................................... 9TM Interrpts ......................................................................................................................... 9TM External Pins ................................................................................................................... 9TM Inpt/Otpt Pin Selection .............................................................................................. 9Prorammin Considerations ................................................................................................ 60

Standard Type TM – STM .............................................................................. 61Standard Type TM Operation ................................................................................................ 61Standard Type TM Reister Description ............................................................................... 6Standard Type TM Operation Modes .................................................................................... 68

Analog to Digital Converter .......................................................................... 79/D Overview ........................................................................................................................ 9Reisters Descriptions .......................................................................................................... 80/D Converter Reference Voltae ......................................................................................... 8/D Converter Inpt Sinals .................................................................................................. 83/D Operation ....................................................................................................................... 83Conversion Rate and Timin Diaram .................................................................................. 84Smmary of /D Conversion Steps ....................................................................................... 84Prorammin Considerations ................................................................................................ 86/D Transfer Fnction ........................................................................................................... 86/D Prorammin Examples ................................................................................................. 8

Power Line Data Transceiver ....................................................................... 89Shared Power Line ................................................................................................................ 90Data Transmission (From master controller to slave device) ................................................ 90Data Reception (From slave device to master controller) ..................................................... 91Crrent Modlator ................................................................................................................ 9pplication Considerations .................................................................................................... 9Power Line Data Transceiver pplication Circits ................................................................. 9

Interrupts ........................................................................................................ 93Interrpt Reisters ................................................................................................................. 93Interrpt Operation ................................................................................................................ 96External Interrpt ................................................................................................................... 9RX Data Transmission Detection Interrpt ............................................................................ 98Timer Modle Interrpts ........................................................................................................ 98LVD Interrpt ......................................................................................................................... 98EEPROM Interrpt ................................................................................................................ 98/D Converter Interrpt ......................................................................................................... 99Time Base Interrpts ............................................................................................................. 99

Rev. 1.00 4 st 1 01 Rev. 1.00 st 1 01



Interrpt Wake-p Fnction ................................................................................................. 101Prorammin Considerations .............................................................................................. 101

Low Voltage Detector – LVD ....................................................................... 102LVD Reister ....................................................................................................................... 10LVD Operation ..................................................................................................................... 103

Application Circuits ..................................................................................... 103Instruction Set .............................................................................................. 104

Introdction ......................................................................................................................... 104Instrction Timin ................................................................................................................ 104Movin and Transferrin Data ............................................................................................. 104rithmetic Operations .......................................................................................................... 104Loical and Rotate Operation ............................................................................................. 10Branches and Control Transfer ........................................................................................... 10Bit Operations ..................................................................................................................... 10Table Read Operations ....................................................................................................... 10Other Operations ................................................................................................................. 10

Instruction Set Summary ............................................................................ 106Table Conventions ............................................................................................................... 106

Instruction Definition ................................................................................... 108Package Information ....................................................................................117

16-pin NSOP (10mil) Otline Dimensions ..........................................................................1180-pin SSOP (10mil) Otline Dimensions ..........................................................................119

Rev. 1.00 6 st 1 01 Rev. 1.00 st 1 01



Features

CPU Features• OperatingVoltage

♦ fSYS=2MHz:2.2V~5.5V♦ fSYS=4MHz:2.2V~5.5V

• Upto1μsinstructioncyclewith4MHzsystemclockatVDD=5V

• Powerdownandwake-upfunctionstoreducepowerconsumption

• Oscillators:♦ InternalHighSpeed2/4MHzRCOscillator–HIRC♦ InternalLowSpeed32kHzRCOscillator–LIRC

• Fullyintegratedinternaloscillatorsrequirenoexternalcomponents

• Multi-modeoperation:FAST,SLOW,IDLEandSLEEP

• Allinstructionsexecutedin1~2instructioncycles

• Tablereadinstructions

• 63powerfulinstructions

• 6-levelsubroutinenesting

• Bitmanipulationinstruction

Peripheral Features• FlashProgramMemory:2K×15

• RAMDataMemory:128×8

• TrueEEPROMMemory:64×8

• WatchdogTimerfunction

• Upto13bidirectionalI/Olines

• SingleexternalinterruptlinesharedwithI/Opin

• TwoTimerModulesfortimemeasurement,inputcapture,comparematchoutput,PWMoutputfunctionorsinglepulseoutputfunction

• 8externalchannels12-bitresolutionA/Dconverter

• DualTime-Basefunctionsforgenerationoffixedtimeinterruptsignals

• Lowvoltageresetfunction–LVR

• Lowvoltagedetectfunction–LVD

• Packagetypes:16-pinNSOP,20-pinSSOP

Two Line Power Line Data Transceiver Features• CompleteDataTransmissiononPowerLinefunctions

• HighMaximumInputVoltage:42V

• IntegratedLowDropoutVoltageRegulator

• IntegratedLowVoltageDetectorforPowerSupplyMonitoring

• IntegratedComparator

• OpendrainNMOSdriverforflexibleinterfacing

• PowerandResetProtectionFeatures

• Minimalexternalcomponentrequirements

Rev. 1.00 6 st 1 01 Rev. 1.00 st 1 01



General DescriptionTheBA45FH0082isaFlashMemory8-bithighperformanceRISCarchitecturemicrocontrollers,designedfornetworkingtypefireprotectionperipheralproducts.OfferinguserstheconvenienceofFlashMemorymulti-programmingfeatures,thedevicealsoincludesawiderangeoffunctionsandfeatures.OthermemoryincludesanareaofRAMDataMemoryaswellasanareaoftrueEEPROMmemoryforstorageofnon-volatiledatasuchasserialnumbers,calibrationdataetc.

Analogfeatureincludesamulti-channel12-bitA/Dconverter.MultipleandextremelyflexibleTimerModulesprovidetiming,pulsegenerationandPWMgenerationfunctions.ProtectivefeaturessuchasaninternalWatchdogTimer,LowVoltageResetandLowVoltageDetectorcoupledwithexcellentnoiseimmunityandESDprotectionensurethatreliableoperationismaintainedinhostileelectricalenvironments.

Thedevicealsocontaina twoline typepower linedata transceiver. Insystemswhereamastercontrollercontrolsanumberof individual interconnectedsubsystemssuchas found insmokedetector systems,watermetering systems, solar energy system,etc., thecostof the lengthyinterconnectingcablingcanbeamajorfactor.Bysendingdataalongthepowersupplylines, theinterconnectingcablescanbereducedtoasimpletwolinetype,thusgreatlyreducingbothcableandinstallationcosts.Withtheadditionofafewexternalcomponents,thispowerlinedatatransceiverdevicecontainsalltheinternalcomponentsrequiredtoprovideuserswithasystemforpowerlinedatatransmissionandreception.Dataismodulatedontothepowerlinebythesimplereductionofthepowerlinevoltageforaspecificperiodoftime.Powersupplyvoltagechangescanbeinitiatedbythemastercontrollerfordatareceptionorinitiatedbythepowerlinedatatransceiverfordatatransmission.AninternalvoltageregulatorwithaSoft-startandshortcircuitprotectionfunctionsensuresthataconstantvoltagepowersupplyisprovidedtotheinterconnectedsubsystemunitswhileaninternalvoltagedetectormonitorsthepowerlinevoltagelevel.AninternalcomparatorisusedtotranslatethedifferentialsignalintoalogicsignalfortheMCU.

Afullchoiceofinternallowandhighoscillatorfunctionsareprovided,thefullyintegratedsystemoscillators requirenoexternalcomponents for their implementation.Theability tooperateandswitchdynamicallybetweenarangeofoperatingmodesusingdifferentclocksourcesgivesuserstheabilitytooptimisemicrocontrolleroperationandminimisepowerconsumption.

TheinclusionofflexibleI/Oprogrammingfeatures,Time-BasefunctionsalongwithmanyotherfeaturesensurethatthedevicewillfindexcellentuseinfireprotectionperipheralapplicationssuchasTemperaturealarms,Output/Inputmodules,Acousto-opticalarms,Firedoormonitorsinadditiontomanyothers.

Rev. 1.00 8 st 1 01 Rev. 1.00 9 st 1 01



Block Diagram

Holtek 8-bitMCU

Power Line Data

Transceiver

VSS VSS

TX

RX

IS

TRX

PB5

PB6/RXINT

CN

VOVOVDD

VCC

VIN(3.3V)I/O ports

A/D pinsIS

TRX

CN

VDD (3.3V)

VSS VSS

STM0

Phase Protect

Interrupt Controller

BusM

UX

VDD

SYSCLK

Reset Circuit

LVD/LVR

Stack6-Level

RAM128 × 8

ROM2K × 15

EEPROM64 × 8

WatchdogTimer

Port ADriver

HIRC2/4MHz

LIRC32kHz

MU

X

Analog Digital Converter

Timers

INT0~INT1

AN0~AN7

Pin-SharedWith Port A&B

Pin- SharedWith Port A&B

Port BDriver

PA0~PA7

VREF

Clock System

Time Bases

Digital Peripherals

HT8 MCU Core

PB0~PB4

Auto Converter

10-bit PWM

Phase Detect

STP0

STP1

VBG12-bitADC

Analog Peripherals

I/O

: Pin-Shared Node

STM1

Phase Protect

16-bit PWM

Phase Detect

GND

Pin-SharedFunction

Pin-SharedWith Port B

RES

Rev. 1.00 8 st 1 01 Rev. 1.00 9 st 1 01



Pin Assignment

VSS/AVSS

PB4/RES

VDD/AVDD

PA0/ICPDA/OCDSDAPA2/ICPCK/OCDSCK

PA6/AN6

PA1/STP0/VREFPA3/STCK0/AN4

PA5/STP0I/AN5PA4/INTPB0/STP1/AN0

VSSTRX

CN ISVCC

BA45FH0082/BA45VH008216 NSOP-A

161514131211109

12345678

20191817161514131211

12345678910

VDD/AVDDVSS/AVSS

VSSTRXCN IS

VCC

PA1/STP0/VREFPB0/STP1/AN0

PB3/AN3

PB1/STCK1/AN1PB2/STP1I/AN2

PB4/RES

PA3/STCK0/AN4

PA7/AN7PA6/AN6PA5/STP0I/AN5PA4/INT

PA0/ICPDA/OCDSDAPA2/ICPCK/OCDSCK

BA45FH0082/BA45VH008220 SSOP-A

Note:1.If thepin-sharedpinfunctionshavemultipleoutputs, thedesiredpin-sharedfunctionisdeterminedbythecorrespondingsoftwarecontrolbits.

2.TheOCDSDAandOCDSCKpinsaresuppliedasOCDSdedicatedpinsandassuchonlyavailablefortheBA45VH0082devicewhichistheOCDSEVchipfortheBA45FH0082device.

3.Forlesspin-countpackagetypestherewillbeunbondedpinsofwhichstatusshouldbeproperlyconfigured toavoid thecurrentconsumptionresultingfroman input floatingcondition.Refer to the“StandbyCurrentConsiderations”and“Input/OutputPorts”sections.

Rev. 1.00 10 st 1 01 Rev. 1.00 11 st 1 01



Pin DescriptionWiththeexceptionof thepowerpinsandsomerelavant transformercontrolpins,allpinsonthedevicecanbereferencedby theirPortnames,e.g.PA0,PA1etc,whichrefer to thedigital I/Ofunctionofthepins.HoweverthesePortpinsarealsosharedwithotherfunctionsuchastheTimerModulepinsetc.Thefunctionofeachpinislistedinthefollowingtable,howeverthedetailsbehindhoweachpinisconfigurediscontainedinothersectionsofthedatasheet.Notethatwheremorethanonepackagetypeexiststhetablewillreflectthesituationforthelargerpackagetype.

Pin Name Function OPT I/T O/T Description

P0/ICPD/OCDSD

P0 PWUPPU ST CMOS General prpose I/O. Reister enabled pll-p and wake-p.

ICPD — ST CMOS ICP data/addressOCDSD — ST CMOS OCDS data/address for EV chip only.

P1/STP0/VREFP1

PWUPPUPS0

ST CMOS General prpose I/O. Reister enabled pll-p and wake-p.

STP0 PS0 — CMOS STM0 non-invertin otptVREF PS0 N — /D converter extemal reference inpt

P/ICPCK/OCDSCK

P PWUPPU ST CMOS General prpose I/O. Reister enabled pll-p and wake-p.

ICPCK — ST — ICP clock inpt OCDSCK — ST — OCDS clock inpt for EV chip only

P3/STCK0/N4P3

PWUPPUPS0


STCK0 PS0 ST — STM0 clock inptN4 PS0 N — /D converter analo inpt

P4/INTP4 PWU

PPU ST CMOS General prpose I/O. Reister enabled pll-p and wake-p.

INT INTEGINTC0 ST — External interrpt inpt

P/STP0I/NP

PWUPPUPS1


STP0I PS1 ST — STM0 captre inptN PS1 N — /D converter analo inpt

P6/N6P6

PWUPPUPS1


N6 PS1 N — /D converter analo inpt

P/NP

PWUPPUPS1


N PS1 N — /D converter analo inpt

PB0/STP1/N0PB0 PBPU

PBS0 ST CMOS General prpose I/O. Reister enabled pll-p.

STP1 PBS0 ST — STM1 non-invertin otptN0 PBS0 N — /D converter analo inpt

PB1/STCK1/N1PB1 PBPU


STCK1 PBS0 ST — STM1 clock inptN1 PBS0 N — /D converter analo inpt

Rev. 1.00 10 st 1 01 Rev. 1.00 11 st 1 01



Pin Name Function OPT I/T O/T Description

PB/STP1I/NPB PBPU


STP1I PBS0 ST — STM1 captre inptN PBS0 N — /D converter analo inpt

PB3/N3PB3 PBPU


N3 PBS0 N — /D converter analo inpt

PB4/RESPB4 PBPU ST CMOS General prpose I/O. Reister enabled pll-p.RES RSTC ST — External reset inpt

CN CN — N — Comparator neative inptIS IS — — NMOS Sorce terminal of constant crrent NMOS driverTRX TRX — DI DO Transceiver sinal detect/modlateVCC VCC — PWR — Power line data transceiver LDO inptVSS VSS — PWR — Power line data transceiver neative power spply rond.

VDD/VDDVDD — PWR — Power line data transceiver LDO otpt

MCU diital positive power spply.VDD — PWR — nalo positive power spply.

VSS/VSSVSS — PWR — MCU diital neative power spply.

VSS — PWR — nalo neative power spply rond.

Legend:I/T:Inputtype O/T:OutputtypeOPT:Optionalbyregisteroption ST:SchmittTriggerinputCMOS:CMOSoutput NMOS:NMOSoutputAN:Analogsignal PWR:PowerDI:Digitalinput DO:Digitaloutput

Internally Connected PinsAmongthepinsmentionedinthetablesaboveseveralpinsarenotconnectedtoexternalpackagepins.ThesepinsareinterconnectionpinsbetweentheMCUandthepowerlinedatatransceiverchipandarelistedinthefollowingtable.Thedescriptionisprovidedfromthepowerlinedatatransceiverchipstandpoint.

Power Line Data Transceiver Pin Name Type Description

RX O Comparator otpt transmitter sinal detect otpt Internally connected to the MCU I/O line PB6/RXINT

TX I Inpt pin for constant crrent modlate Internally connected to the MCU I/O line PB

VO PWR LDO otptConnected to MCU positive power spply VDD

Rev. 1.00 1 st 1 01 Rev. 1.00 13 st 1 01



Absolute Maximum RatingsSupplyVoltage...................................................................................................VSS-0.3VtoVSS+6.0V

InputVoltage.....................................................................................................VSS-0.3VtoVDD+0.3V

StorageTemperature..................................................................................................... -50°Cto125°C

OperatingTemperature................................................................................................... -40°Cto85°C

IOLTotal....................................................................................................................................... 80mA

IOHTotal...................................................................................................................................... -80mA

TotalPowerDissipation........................................................................................................... 500mW

Note:Theseare stress ratingsonly.Stressesexceeding the range specifiedunder “AbsoluteMaximumRatings”maycausesubstantialdamageto thedevice.Functionaloperationofthisdeviceatotherconditionsbeyondthose listed in thespecification isnot impliedandprolongedexposuretoextremeconditionsmayaffectdevicereliability.

D.C. CharacteristicsFordatainthefollowingtables,notethatfactorssuchasoscillatortype,operatingvoltage,operatingfrequency,pin loadconditions, temperatureandprograminstruction type,etc.,canallexertaninfluenceonthemeasuredvalues.

Operating Voltage CharacteristicsTa=-40°C~8°C

Symbol Parameter Test Conditions Min. Typ. Max. Unit

VDDOperatin Voltae – HIRC

fSYS = MHz . — .V

fSYS = 4MHz . — .Operatin Voltae – LIRC fSYS = 3kHz . — . V

Rev. 1.00 1 st 1 01 Rev. 1.00 13 st 1 01



Standby Current CharacteristicsTa=°C

Symbol Standby ModeTest Conditions

Min. Typ. Max. Max.@85°C Unit

VDD Conditions

ISTB

SLEEP Mode

.VWDT off

— 0. 0.6 0.

μA

3V — 0. 0.8 1V — 0. 1 1.

.VWDT on

— 1. .4 .93V — 1. 3 3.6V — 3 6

IDLE0 Mode – LIRC.V

fSUB on— .4 4 4.8

μA3V — 3 6V — 10 1

IDLE1 Mode – HIRC

.VfSUB on fSYS = MHz

— 0.06 0.1 0.14

m

3V — 0.0 0.14 0.16V — 0.13 0.6 0.8

.VfSUB on fSYS = 4MHz

— 0.09 0.0 0.3V — 0.11 0. 0.4V — 0.1 0.4 0.46

Notes:Whenusingthecharacteristictabledata,thefollowingnotesshouldbetakenintoconsideration:1.Anydigitalinputsaresetupinanon-floatingcondition.2.Allmeasurementsaretakenunderconditionsofnoloadandwithallperipheralsinanoffstate.3.TherearenoDCcurrentpaths.4.AllStandbyCurrentvaluesaretakenafteraHALTinstructionexecutionthusstoppingall instructionexecution.

Operating Current CharacteristicsTa=°C

Symbol Operating ModeTest Conditions

Min. Typ. Max. UnitVDD Conditions

IDD

SLOW Mode – LIRC.V

fSYS = 3kHz— 8 16

μA3V — 10 0V — 30 0

FST Mode – HIRC

.VfSYS = MHz

— 0.1 0.

m

3V — 0. 0.3V — 0.4 0.6

.VfSYS = 4MHz

— 0.3 0.3V — 0.4 0.6V — 0.8 1.

Notes:Whenusingthecharacteristictabledata,thefollowingnotesshouldbetakenintoconsideration:1.Anydigitalinputsaresetupinanon-floatingcondition.2.Allmeasurementsaretakenunderconditionsofnoloadandwithallperipheralsinanoffstate.3.TherearenoDCcurrentpaths.4.AllOperatingCurrentvaluesaremeasuredusingacontinuousNOPinstructionprogramloop.

Rev. 1.00 14 st 1 01 Rev. 1.00 1 st 1 01



A.C. CharacteristicsFordatainthefollowingtables,notethatfactorssuchasoscillatortype,operatingvoltage,operatingfrequencyandtemperatureetc.,canallexertaninfluenceonthemeasuredvalues.

High Speed Internal Oscillator – HIRC – Frequency AccuracyDuringtheprogramwritingoperationthewriterwill trimtheHIRCoscillatoratauserselectedHIRCfrequencyanduserselectedvoltageofeither3Vor5V.

2/4MHz

Symbol ParameterTest Conditions

Min Typ Max UnitVDD Temp.

fHIRC

MHz Writer Trimmed HIRC Freqency

3V/V°C -1% +1%

MHz-0°C~60°C -% +%-40°C~8°C -3% +3%

.V~.V°C -9% +9%-40°C~8°C -10% +10%

4MHz Writer Trimmed HIRC Freqency

3V/V°C -1% 4 +1%

MHz-40°C~8°C -% 4 +%

.V~.V°C -.% 4 +.%-40°C~8°C -3% 4 +3%

Notes:1.The3V/5VvaluesforVDDareprovidedasthesearethetwoselectablefixedvoltagesatwhichtheHIRCfrequencyistrimmedbythewriter.

2.The rowbelow the3V/5Vtrimvoltage row isprovided toshow thevalues for the fullVDD rangeoperatingvoltage.Itisrecommendedthatthetrimvoltageisfixedat3Vforapplicationvoltagerangesfrom2.2Vto3.6Vandfixedat5Vforapplicationvoltagerangesfrom3.3Vto5.5V.

3.Theminimumandmaximumtolerancevaluesprovidedinthetableareonlyforthefrequencyatwhichthewriter trimstheHIRCoscillator.After trimmingat thischosenspecificfrequencyanychangeinHIRCoscillatorfrequencyusingtheoscillatorregistercontrolbitsbytheapplicationprogramwillgiveafrequencytolerancetowithin±20%.

Low Speed Internal Oscillator Characteristics – LIRCTa=25°C, unless otherwise specified



fLIRC LIRC Freqency .V~.V°C -10% 3 +10%

kHz-40°C~8°C -0% 3 +60%

tSTRT LIRC Start Up Time — — — — 00 μs

Rev. 1.00 14 st 1 01 Rev. 1.00 1 st 1 01



Operating Frequency Characteristic Curves

System Operating Frequency

Operating Voltage2.2V 5.5V

~~

4MHz

2MHz

~~

System Start Up Time CharacteristicsTa=-40°C~8°C



tSST

System Start-p TimeWake-p from Condition where fSYS is Off

— fSYS = fH ~ fH/64 fH = fHIRC — 16 — tHIRC

— fSYS = fSUB = fLIRC — — tLIRC

System Start-p TimeWake-p from Condition where fSYS is On

— fSYS = fH ~ fH/64 fH = fHIRC — — tH— fSYS = fSUB = fLIRC — — tSUB

System Speed Switch TimeFST to SLOW Mode orSLOW to FST Mode

— fHIRC switches from off → on — 16 — tHIRC

tRSTD

System Reset Delay TimeReset Sorce from Power-on Reset orLVR Hardware Reset

— RRPOR = V/ms4 48 4 ms

System Reset Delay TimeWDTC/RSTC Software Reset — —

System Reset Delay TimeReset Sorce from WDT Overflow orReset Pin Reset

— — 8 16 4 ms

Notes:1.FortheSystemStart-uptimevalues,whetherfSYSisonoroffdependsuponthemodetypeandthecho-senfSYSsystemoscillator.DetailsareprovidedintheSystemOperatingModessection.

2.Thetimeunits,shownbythesymbolstHIRC.aretheinverseofthecorrespondingfrequencyvaluesasprovidedinthefrequencytables.ForexampletHIRC=1/fHIRC,tSYS=1/fSYSetc.

3.If theLIRCisusedasthesystemclockandif it isoffwhenintheSLEEPMode, thenanadditionalLIRCstartuptime,tSTART,asprovidedintheLIRCfrequencytable,mustbeaddedtothetSSTtimeinthetableabove.

4.TheSystemSpeedSwitchTimeiseffectivelythetimetakenforthenewlyactivatedoscillatortostartup.

Rev. 1.00 16 st 1 01 Rev. 1.00 1 st 1 01



Input/Output CharacteristicsTa=°C



VILInpt Low Voltae for I/O Ports or Inpt Pins

V — 0 — 1.V— — 0 — 0.VDD

Inpt Low Voltae for External Reset Pin — — 0 — 0.4VDD

VIHInpt Hih Voltae for I/O Ports or Inpt Pins

V — 3. — .0V— — 0.8VDD — VDD

Inpt Hih Voltae for External Reset Pin — — 0.9VDD — VDD

IOL Sink Crrent for I/O Pins3V

VOL = 0.1VDD1. 31 —

mV 31 6 —

IOH Sorce Crrent for I/O Pins3V

VOH = 0.9VDD-3. -.0 —

mV -. -14. —

RPH Pll-hih Resistance for I/O Ports(Note)3V

—0 60 100

kΩV 10 30 0

ILEK Inpt Leakae Crrent V VIN = VDD or VIN = VSS — — ±1 μAtTPI TM Captre Inpt Minimm Plse Width — — 0.3 — — μstTCK TM Clock Inpt Minimm Plse Width — — 0.3 — — μstINT Interrpt Inpt Pin Minimm Plse Width — — 10 — — μstRES External Reset Pin Minimm Plse Width — — 10 — — μstSRESET Minimm Software Reset Plse Width to Reset — — 4 90 10 μs

Note:TheRPH internalpullhighresistancevalueiscalculatedbyconnectingtogroundandenablingtheinputpinwithapull-highresistorandthenmeasuringtheinputsinkcurrentatthespecifiedsupplyvoltagelevel.DividingthevoltagebythismeasuredcurrentprovidestheRPHvalue.

Memory CharacteristicsTa=-40°C~8°C



VRW VDD for Read / Write — — VDDmin — VDDmax VFlash Program Memory / Data EEPROM MemorytDEW Data EEPROM Write Cycle Time — — — 4 6 msIDDPGM Prorammin / Erase Crrent on VDD — — — — .0 mEP Cell Endrance — — 100K — — E/WtRETD ROM Data Retention Time — Ta = °C — 40 — YearRAM Data MemoryVDR RM Data Retention Voltae Device in SLEEP Mode 1.0 V

Rev. 1.00 16 st 1 01 Rev. 1.00 1 st 1 01



LVD/LVR Electrical CharacteristicsTa=°C



VLVR Low Voltae Reset Voltae — LVR enable -% .1 +% V

VLVD Low Voltae Detection Voltae —

LVD enable voltae select .0V

-%

.0

+% V

LVD enable voltae select .V .LVD enable voltae select .4V .4LVD enable voltae select .V .LVD enable voltae select 3.0V 3.0LVD enable voltae select 3.3V 3.3LVD enable voltae select 3.6V 3.6LVD enable voltae select 4.0V 4.0

ILVRLVDBG Operatin Crrent

3V LVD enable LVR enableVBGEN=0

— — 18

μAV — 0 3V LVD enable LVR enable

VBGEN=1— — 10

V — 180 00

tLVDS LVDO Stable Time— For LVR enable VBGEN=0

LVD off → on — — 1μs

— For LVR disable VBGEN=0LVD off → on — — 10

tLVRMinimm Low Voltae Width to Reset — — 10 40 480 μs

tLVDMinimm Low Voltae Width to Interrpt — — 60 10 40 μs

ILVR dditional Crrent for LVR Enable — LVD disable VBGEN=0 — — 4 μAILVD dditional Crrent for LVD Enable — LVR disable VBGEN=0 — — 4 μA

Reference Voltage Electrical CharacteristicsTa=°C



VBG Bandap Reference Voltae — — -% 1.04 +% VtBGS VBG Trn On Stable Time — No load — — 10 μsIBG dditional Crrent for VBG Enable — LVR disable LVD disable — — 180 μA

Note:TheVBGvoltagecanbeusedastheA/Dconverterinternalsignalinput.

Rev. 1.00 18 st 1 01 Rev. 1.00 19 st 1 01



A/D Converter Electrical CharacteristicsTa=°C



VDD Operatin Voltae — — . — . VVDI Inpt Voltae — — 0 — VREF VVREF Reference Voltae — — — VDD V

DNL Differential Non-linearity

3VVREF = VDD tDCK = 0.5μs

— — ±3 LSBV3V

VREF = VDD tDCK = 8μsV

INL Interal Non-linearity

3VVREF = VDD tDCK = 0.5μs

— — ±4 LSBV3V

VREF = VDD tDCK = 8μsV

IDC dditional Crrent for DC Enable3V

No load (tDCK = 0.5μs)— 1 m

V — 1. 3 mtDCK Clock Period — — 0. — 10 μstONST DC On-to-Start Time — — 4 — — μstDS Samplin Time — — — 4 — tDCK

tDCConversion Time (Inclde DC Sample and Hold Time) — — — 16 — tDCK

Power Line Data Transceiver Electrical CharacteristicsTa=°C



VCC Operatin Voltae — — — 4 VICC Operatin Crrent — VCC = 4V VDD No Load — 0 40 μAVT Threshold Voltae — — — VMRK-.6 — V

IMC Modlate Crrent— RS = 100Ω — 1 —

m— RS = 47Ω — 3 —

VIL Inpt Low Voltae for TX LineV — 0 — 1.

V3.3V — 0 — 0.VDD

VIH Inpt Hih Voltae for TX LineV — 3. —

V3.3V — 0.8VDD — VDD

IOL Sink Crrent for RX Line3.3V

VOL = 0.1VDD4 8 —

mV 10 0 —

IOH Sorce Crrent for RX Line3.3V

VOH = 0.9VDD- -4 —

mV - -10 —

RPH Pll-hih Resistance for TX — — -30% 0 30% kΩLDO

VOUT Otpt Voltae3.3V

VCC = V ILOD = 10m3. 3.3 3.4

VV 4.8 .1

IOUT Otpt Crrent —VCC = 10V, ΔVOUT = -3% 60 — —

mVCC = 7V, ΔVOUT = -3% 30 — —

ΔVLINE Line Relation — V ≤ VIN ≤ 4V ILOD = 1m — — 0. %/V

Rev. 1.00 18 st 1 01 Rev. 1.00 19 st 1 01





TC Temperature Coefficient3.3V Ta = -40°C ~ 8°C

VCC = V ILOD = 10m— ±0. ±1

mV/°CV — ±0. ±1.

ΔVOUT_

RIPPLEOtpt Voltae Ripple — VCC = V ILOD = 10m — — 40 mV

tSTRT LDO Startp Time3.3V VCC = V ILOD = 1m

VOUT = 3.3V ± 3% — — 10 ms

V VCC = V ILOD = 1m VOUT = V ± 3% — — 10 ms

IOL Sink Crrent for VDD — VCC = V VOL = 0.V 0.8 — — mLVDVLVD Low Voltae Detection Voltae — — .0 . . VTC Temperature Coefficient (ΔVLVD/ΔTa) — Ta = -40°C ~ 8°C — ±0.9 — mV/°C

VDETPower p Detection Voltae (VCC

Positive-oin Threshold Voltae) — — 6. 6. 6.8 V

ComparatorOL Open Loop Gain — — 60 80 — dBVHYS Hysteresis — — — 0.1 — VtRP Response Time — — — — μsConstant Current ModulatortRP Response Time — No Load — — μs

Power-on Reset CharacteristicsTa=°C



VPORVDD Start Voltae to Ensre Power-on Reset — — — — 100 mV

RRPORVDD Risin Rate to Ensre Power-on Reset — — 0.03 — — V/ms

tPORMinimm Time for VDD Stays at VPOR to Ensre Power-on Reset — — 1 — — ms

VDD

tPOR RRPOR

VPOR

Time

Rev. 1.00 0 st 1 01 Rev. 1.00 1 st 1 01



System ArchitectureAkeyfactorinthehigh-performancefeaturesoftherangeofmicrocontrollersisattributedtotheirinternalsystemarchitecture.ThedevicetakesadvantageoftheusualfeaturesfoundwithinRISCmicrocontrollersprovidingincreasedspeedofoperationandenhancedperformance.Thepipeliningscheme is implemented in suchaway that instruction fetchingand instructionexecutionareoverlapped,henceinstructionsareeffectivelyexecutedinonecyclewiththeexceptionsofbranchorcall instructions.An8-bitwideALUisusedinpracticallyall instructionsetoperations,whichcarriesoutarithmeticoperations,logicoperations,rotation,increment,decrement,branchdecisions,etc.The internaldatapath issimplifiedbymovingdata throughtheAccumulatorandtheALU.Certain internalregistersare implemented in theDataMemoryandcanbedirectlyor indirectlyaddressed.Thesimpleaddressingmethodsof theseregistersalongwithadditionalarchitecturalfeaturesensurethataminimumofexternalcomponentsisrequiredtoprovideafunctionalI/OandA/Dcontrolsystemwithmaximumreliabilityandflexibility.Thismakesthedevicesuitableforlow-cost,high-volumeproductionforcontrollerapplications.

Clocking and PipeliningThemainsystemclock,derivedfromeitheranHIRCorLIRCoscillator issubdividedintofourinternallygeneratednon-overlappingclocks,T1~T4.TheProgramCounter is incrementedat thebeginningoftheT1clockduringwhichtimeanewinstructionisfetched.TheremainingT2~T4clockscarryoutthedecodingandexecutionfunctions.Inthisway,oneT1~T4clockcycleformsoneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakesplaceinconsecutiveinstructioncycles, thepipeliningstructureof themicrocontrollerensures that instructionsareeffectivelyexecuted inone instructioncycle.Theexception to thisare instructionswhere thecontentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhichcasetheinstructionwilltakeonemoreinstructioncycletoexecute.

For instructions involvingbranches,suchas jumporcall instructions, twomachinecyclesarerequired tocomplete instructionexecution.Anextracycle is requiredas theprogramtakesonecycletofirstobtaintheactualjumporcalladdressandthenanothercycletoactuallyexecutethebranch.Therequirementforthisextracycleshouldbetakenintoaccountbyprogrammersintimingsensitiveapplications.

Fetch Inst. (PC)

(System Clock)fSYS

Phase Clock T1

Phase Clock T

Phase Clock T3

Phase Clock T4

Proram Conter PC PC+1 PC+

PipelininExecte Inst. (PC-1) Fetch Inst. (PC+1)

Execte Inst. (PC) Fetch Inst. (PC+)

Execte Inst. (PC+1)

System Clocking and Pipelining

Rev. 1.00 0 st 1 01 Rev. 1.00 1 st 1 01



Fetch Inst. 11 MOV [1H] CLL DELY3 CPL [1H]4 : :6 DELY: NOP

Execte Inst. 1 Fetch Inst. Execte Inst.

Fetch Inst. 3 Flsh PipelineFetch Inst. 6 Execte Inst. 6

Fetch Inst.

Instruction Fetching

Program CounterDuringprogramexecution, theProgramCounter isused tokeep trackof theaddressof thenext instruction tobeexecuted. It isautomatically incrementedbyoneeach timean instructionisexecutedexcept for instructions, suchas“JMP”or“CALL” thatdemandsa jump toanon-consecutiveProgramMemoryaddress.Onlythelower8bits,knownastheProgramCounterLowRegister,aredirectlyaddressablebytheapplicationprogram.

Whenexecuting instructions requiring jumps tonon-consecutiveaddresses suchas a jumpinstruction,asubroutinecall, interruptorreset,etc., themicrocontrollermanagesprogramcontrolbyloadingtherequiredaddressintotheProgramCounter.Forconditionalskipinstructions,oncetheconditionhasbeenmet,thenextinstruction,whichhasalreadybeenfetchedduringthepresentinstructionexecution,isdiscardedandadummycycletakesitsplacewhilethecorrectinstructionisobtained.

Program Counter

Program Counter High Byte PCL RegisterPC10~PC8 PCL~PCL0

Program Counter

Thelowerbyteof theProgramCounter,knownastheProgramCounterLowregisterorPCL,isavailableforprogramcontrolandisareadableandwriteableregister.Bytransferringdatadirectlyintothisregister,ashortprogramjumpcanbeexecuteddirectly.However,asonlythis lowbyteisavailableformanipulation, the jumpsare limited to thepresentpageofmemory, that is256locations.Whensuchprogramjumpsareexecuted itshouldalsobenoted thatadummycyclewillbeinserted.ManipulatingthePCLregistermaycauseprogrambranching,soanextracycleisneededtopre-fetch.

StackThisisaspecialpartofthememorywhichisusedtosavethecontentsoftheProgramCounteronly.Thestackisorganisedinto6levelsandisneitherpartofthedatanorpartoftheprogramspace,andisneitherreadablenorwriteable.Theactivatedlevel is indexedbytheStackPointer,andisneitherreadablenorwriteable.Atasubroutinecallorinterruptacknowledgesignal,thecontentsoftheProgramCounterarepushedontothestack.Attheendofasubroutineoraninterruptroutine,signaledbyareturninstruction,RETorRETI,theProgramCounterisrestoredtoitspreviousvaluefromthestack.Afteradevicereset,theStackPointerwillpointtothetopofthestack.

If thestackisfullandanenabledinterrupttakesplace,theinterruptrequestflagwillberecordedbuttheacknowledgesignalwillbeinhibited.WhentheStackPointer isdecremented,byRETorRETI,theinterruptwillbeserviced.Thisfeaturepreventsstackoverflowallowingtheprogrammertousethestructuremoreeasily.However,whenthestackisfull,aCALLsubroutineinstructioncanstillbeexecutedwhichwillresult inastackoverflow.Precautionsshouldbetakentoavoidsuchcaseswhichmightcauseunpredictableprogrambranching.Ifthestackisoverflow,thefirstProgramCountersaveinthestackwillbelost.

Rev. 1.00 st 1 01 Rev. 1.00 3 st 1 01



StackPointer

Stack Level

Stack Level 1

Stack Level 3:::

Stack Level 6

Proram Memory

Proram Conter

Bottom of Stack

Top of Stack

Arithmetic and Logic Unit – ALUThearithmetic-logicunitorALUisacriticalareaofthemicrocontrollerthatcarriesoutarithmeticandlogicoperationsoftheinstructionset.Connectedtothemainmicrocontrollerdatabus,theALUreceivesrelatedinstructioncodesandperformstherequiredarithmeticor logicaloperationsafterwhichtheresultwillbeplacedinthespecifiedregister.AstheseALUcalculationoroperationsmayresultincarry,borroworotherstatuschanges,thestatusregisterwillbecorrespondinglyupdatedtoreflectthesechanges.TheALUsupportsthefollowingfunctions:

• Arithmeticoperations:ADD,ADDM,ADC,ADCM,SUB,SUBM,SBC,SBCM,DAA

• Logicoperations:AND,OR,XOR,ANDM,ORM,XORM,CPL,CPLA

• Rotation:RRA,RR,RRCA,RRC,RLA,RL,RLCA,RLC

• IncrementandDecrement:INCA,INC,DECA,DEC

• Branchdecision:JMP,SZ,SZA,SNZ,SIZ,SDZ,SIZA,SDZA,CALL,RET,RETI

Rev. 1.00 st 1 01 Rev. 1.00 3 st 1 01



Flash Program MemoryTheProgramMemoryisthelocationwheretheusercodeorprogramisstored.ForthisdevicetheProgramMemoryisFlashtype,whichmeansitcanbeprogrammedandre-programmeda largenumberoftimes,allowingtheusertheconvenienceofcodemodificationonthesamedevice.Byusingtheappropriateprogrammingtools,theFlashdeviceofferuserstheflexibilitytoconvenientlydebuganddevelop their applicationswhilealsoofferingameansof fieldprogrammingandupdating.

StructureTheProgramMemoryhasacapacityof2K×15bits.TheProgramMemoryisaddressedby theProgramCounterandalsocontainsdata,tableinformationandinterruptentries.Tabledata,whichcanbesetupinanylocationwithintheProgramMemory,isaddressedbyaseparatetablepointerregister.

Look-p Table

Initialisation Vector000H

004H

0CH

FFH

Interrpt Vectors

1 bits

n00H

nFFH

Program Memory Structure

Special VectorsWithintheProgramMemory,certainlocationsarereservedfortheresetandinterrupts.Thelocation000His reserved foruseby thedevice reset forprograminitialisation.Afteradevice reset isinitiated,theprogramwilljumptothislocationandbeginexecution.

Look-up Table AnylocationwithintheProgramMemorycanbedefinedasalook-uptablewhereprogrammerscanstorefixeddata.Tousethelook-uptable,thetablepointermustfirstbesetupbyplacingtheaddressof thelookupdatatoberetrievedinthetablepointerregister,TBLPandTBHP.Theseregistersdefinethetotaladdressofthelook-uptable.

Aftersettingupthetablepointer,thetabledatacanberetrievedfromtheProgramMemoryusingthecorrespondingtablereadinstructionsuchas“TABRD[m]”or“TABRDL[m]”respectively.Whentheinstructionisexecuted,thelowerordertablebytefromtheProgramMemorywillbetransferredtotheuserdefinedDataMemoryregister[m]asspecifiedintheinstruction.ThehigherordertabledatabytefromtheProgramMemorywillbetransferredtotheTBLHspecialregister.

Theaccompanyingdiagramillustratestheaddressingdataflowofthelook-uptable.

Rev. 1.00 4 st 1 01 Rev. 1.00 st 1 01



Last Pae orTBHP Reister

ddress

TBLP Reister

Data16 bits

Proram Memory

Reister TBLH User Selected Reister

Hih Byte Low Byte

Table Program ExampleThefollowingexampleshowshowthetablepointerandtabledataisdefinedandretrievedfromthemicrocontroller.ThisexampleusesrawtabledatalocatedintheProgramMemorywhichisstoredthereusingtheORGstatement.ThevalueatthisORGstatementis“700H”whichreferstothestartaddressofthelastpagewithinthe2KProgramMemoryofthemicrocontroller.Thetablepointerlowbyteregisterissetupheretohaveaninitialvalueof“06H”.ThiswillensurethatthefirstdatareadfromthedatatablewillbeattheProgramMemoryaddress“706H”or6locationsafterthestartofthelastpage.NotethatthevalueforthetablepointerisreferencedtothefirstaddressspecifiedbyTBLPandTBHPifthe“TABRD[m]”instructionisbeingused.ThehighbyteofthetabledatawhichinthiscaseisequaltozerowillbetransferredtotheTBLHregisterautomaticallywhenthe“TABRD[m]”instructionisexecuted.

Because theTBLHregister isaread-onlyregisterandcannotberestored,careshouldbe takentoensure itsprotection ifboth themain routineand InterruptServiceRoutineuse table readinstructions. Ifusing the tableread instructions, theInterruptServiceRoutinesmaychange thevalueoftheTBLHandsubsequentlycauseerrorsifusedagainbythemainroutine.Asaruleitisrecommendedthatsimultaneoususeofthetablereadinstructionsshouldbeavoided.However, insituationswheresimultaneoususecannotbeavoided,theinterruptsshouldbedisabledpriortotheexecutionofanymainroutinetable-readinstructions.Notethatalltablerelatedinstructionsrequiretwoinstructioncyclestocompletetheiroperation.

Table Read Program Exampletempreg1 db ? ; temporary register #1tempreg2 db ? ; temporary register #2::mov a,06h ; initialise low table pointer - note that this address is referencedmov tblp,a ; to the last page or the page that tbhp pointedmov a,07h ; initialise high table pointermov tbhp,a ; It is not necessary to set tbhp register if executing “tabrdl” ; instruction::tabrd tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address “706H” transferred to tempreg1 and TBLHdec tblp ; reduce value of table pointer by onetabrd tempreg2 ; transfers value in table referenced by table pointer ; data at program memory address “705H” transferred to ; tempreg2 and TBLH in this example the data “1AH” is ; transferred to tempreg1 and data “0FH” to register tempreg2::org 700h ; sets initial address of program memorydc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh:

Rev. 1.00 4 st 1 01 Rev. 1.00 st 1 01



In Circuit Programming – ICPTheprovisionofFlashtypeProgramMemoryprovidestheuserwithameansofconvenientandeasyupgradesandmodificationstotheirprogramsonthesamedevice.Asanadditionalconvenience,ameansofprogrammingthemicrocontrollerin-circuithasprovidedusinga4-pininterface.Thisprovidesmanufacturerswiththepossibilityofmanufacturingtheircircuitboardscompletewithaprogrammedorun-programmedmicrocontroller,andthenprogrammingorupgradingtheprogramata laterstage.Thisenablesproductmanufacturers toeasilykeep theirmanufacturedproductssuppliedwiththelatestprogramreleaseswithoutremovalandre-insertionofthedevice.

TheFlashMCUtoWriterProgrammingPincorrespondencetableisasfollows:

Writer Pins MCU Programming Pins Pin DescriptionICPD P0 Prorammin serial data/addressICPCK P Prorammin clockVDD VDD Power spplyVSS VSS Grond

TheProgramMemoryandEEPROMdataMemorycanbothbeprogrammedseriallyin-circuitusingthis4-wireinterface.Dataisdownloadedanduploadedseriallyonasinglepinwithanadditionallinefor theclock.Twoadditional linesarerequiredfor thepowersupply.The technicaldetailsregardingthein-circuitprogrammingofthedevicearebeyondthescopeofthisdocumentandwillbesuppliedinsupplementaryliterature.

Duringtheprogrammingprocess,takingcontroloftheICPDAandICPCKpinsfordataandclockprogrammingpurposes.Theusermusttheretakecaretoensurethatnootheroutputsareconnectedtothesetwopins.

* *

Writer_VDD

ICPD

ICPCK

Writer_VSS

To other Circit

VDD

P0

P

VSS

Writer Connector Sinals

MCU ProramminPins

Note:*mayberesistororcapacitor.Theresistanceof*mustbegreaterthan1kΩorthecapacitanceof*mustbelessthan1nF.

On-Chip Debug Support – OCDSAnEVchipexistsforthepurposesofdeviceemulation.ThisEVchipdevicealsoprovidesan“On-ChipDebug”functiontodebugthedeviceduringthedevelopmentprocess.TheEVchipandtheactualMCUdevicearealmostfunctionallycompatibleexceptforthe“On-ChipDebug”function.Userscanuse theEVchipdevice toemulate the realchipdevicebehaviorbyconnecting theOCDSDAandOCDSCKpinstotheHT-IDEdevelopmenttools.TheOCDSDApinis theOCDSData/Addressinput/outputpinwhiletheOCDSCKpinistheOCDSclockinputpin.WhenusersusetheEVchipfordebugging,otherfunctionswhicharesharedwiththeOCDSDAandOCDSCKpins

Rev. 1.00 6 st 1 01 Rev. 1.00 st 1 01



intheactualMCUdevicewillhavenoeffectintheEVchip.However,thetwoOCDSpinswhicharepin-sharedwiththeICPprogrammingpinsarestillusedastheFlashMemoryprogrammingpinsforICP.ForamoredetailedOCDSdescription,refertothecorrespondingdocument.

e-Link Pins EV Chip Pins Pin DescriptionOCDSD OCDSD On-chip deb spport data/address inpt/otptOCDSCK OCDSCK On-chip deb spport clock inpt

VDD VDD Power spplyVSS VSS Grond

Data MemoryTheDataMemoryisavolatileareaof8-bitwideRAMinternalmemoryandisthelocationwheretemporaryinformationisstored.

Categorizedintotwotypes,thefirstoftheseisanareaofRAMwherespecialfunctionregistersarelocated.Theseregistershavefixedlocationsandarenecessaryforcorrectoperationofthedevice.Manyoftheseregisterscanbereadfromandwrittentodirectlyunderprogramcontrol,however,someremainprotectedfromusermanipulation.ThesecondareaofDataMemoryisreservedforgeneralpurposeuse.All locationswithin thisareaarereadandwriteaccessibleunderprogramcontrol.

StructureTheDataMemory is subdivided into twobanks, allofwhichare implemented in8-bitwideMemory.TheSpecialPurposeDataMemoryregistersareaccessibleinBank0,withtheexceptionof theEECregisterataddress40H,which isonlyaccessible inBank1.SwitchingbetweenthedifferentDataMemorybanksisachievedbyproperlysettingtheBankPointertocorrectvalue.ThestartaddressoftheDataMemoryistheaddress00H.

Special Purpose Data Memory General Purpose Data Memory

Available Banks Capacity Bank: Address0: 00H~3FH1: 40H (EEC only) 18×8 0: 40H~BFH

Data Memory Summary

00H

40H

BFH

Special Prpose Data Memory

General Prpose Data Memory

Bank 0

3FHEEC at 40H in Bank1 only

(Bank 0: 00H~3FH)

(Bank 0: 40H~BFH)

Data Memory Structure

Rev. 1.00 6 st 1 01 Rev. 1.00 st 1 01



General Purpose Data MemoryAllmicrocontrollerprogramsrequireanareaofread/writememorywheretemporarydatacanbestoredandretrievedforuselater.ItisthisareaofRAMmemorythatisknownasGeneralPurposeDataMemory.ThisareaofDataMemoryisfullyaccessiblebytheuserprogramingforbothreadingandwritingoperations.Byusingthebitoperationinstructions individualbitscanbesetorresetunderprogramcontrolgivingtheuseralargerangeofflexibilityforbitmanipulationintheDataMemory.

Special Purpose Data MemoryThis area ofDataMemory iswhere registers, necessary for the correct operation of themicrocontroller,arestored.Mostof theregistersarebothreadableandwriteablebutsomeareprotectedandarereadableonly,thedetailsofwhicharelocatedundertherelevantSpecialFunctionRegistersection.Notethatforlocationsthatareunused,anyreadinstructiontotheseaddresseswillreturnthevalue“00H”.

00H IR001H MP00H IR103H MP104H0H CC06H PCL0H TBLP08H TBLH09H0H STTUS0BH0CH

STM0C1

0DH

PWU

0EH0FH10H

RSTFC

11H1H

19HWDTC

18H

TB0C1BH1H

1DH1CH

1FH

SCCHIRCC

13H14H

INTC

1HP

16H1H

PC

PBPU

0H1HH

9H8H

BHH

DHCH

FHEH

3H4HH6HH

PPU

1EH

Bank 0

30H31H3H

PSCREE

TB1C

40H

3EH

BP

STM1C0

RSTC

STM0C0

SDOLSDOH

EED

Bank 1

INTEGINTC0

SDC0SDC1LVDC

INTC1

EEC

Bank 0 Bank 1

: Unsed read as 00H

TBHP

PBC

STM0DLSTM0DHSTM0LSTM0H

PB

STM1DL

PBS0

33H

3H34H

3H36H

39H38H

3H

STM1C1

PS1

STM1DHSTM1LSTM1HSTM1RP

PS0

3BH

3DH3CH

3FH

Special Purpose Data Memory

Rev. 1.00 8 st 1 01 Rev. 1.00 9 st 1 01



Special Function Register DescriptionMostoftheSpecialFunctionRegisterdetailswillbedescribedintherelevantfunctionalsections,howeverseveralregistersrequireaseparatedescriptioninthissection.

Indirect Addressing Registers – IAR0, IAR1TheIndirectAddressingRegisters,IAR0andIAR1,althoughhavingtheirlocationsinnormalRAMregisterspace,donotactuallyphysicallyexistasnormalregisters.ThemethodofindirectaddressingforRAMdatamanipulationuses theseIndirectAddressingRegistersandMemoryPointers, incontrasttodirectmemoryaddressing,wheretheactualmemoryaddressisspecified.ActionsontheIAR0andIAR1registerswillresultinnoactualreadorwriteoperationtotheseregistersbutrathertothememorylocationspecifiedbytheircorrespondingMemoryPointers,MP0orMP1.Actingasapair,IAR0andMP0cantogetheraccessdataonlyfromBank0whiletheIAR1registertogetherwiththeMP1registerpaircanaccessdatafromanyDataMemoryBank.AstheIndirectAddressingRegistersarenotphysicallyimplemented,readingtheIndirectAddressingRegisterswillreturnaresultof“00H”andwritingtotheregisterswillresultinnooperation.

Memory Pointers – MP0, MP1TwoMemoryPointers, knownasMP0andMP1areprovided.TheseMemoryPointers arephysicallyimplementedintheDataMemoryandcanbemanipulatedinthesamewayasnormalregistersprovidingaconvenientwaywithwhichtoaddressandtrackdata.WhenanyoperationtotherelevantIndirectAddressingRegistersiscarriedout,theactualaddressthatthemicrocontrollerisdirectedtoistheaddressspecifiedbytherelatedMemoryPointer.MP0,togetherwithIndirectAddressingRegister,IAR0,areusedtoaccessdatafromBank0,whileMP1andIAR1areusedtoaccessdatafromallbanksaccordingtotheBPregister.DirectAddressingcanbeusedinBank0,allotherbanksmustbeaddressedindirectlyusingMP1andIAR1.

ThefollowingexampleshowshowtoclearasectionoffourDataMemorylocationsalreadydefinedaslocationsadres1toadres4.

Indirect Addressing Program Exampledata .section ´data´adres1 db ?adres2 db ?adres3 db ?adres4 db ?block db ?code .section at 0 code´org 00hstart: mov a, 04h ; setup size of block mov block, a mova,offsetadres1 ;AccumulatorloadedwithfirstRAMaddress movmp0,a ;setupmemorypointerwithfirstRAMaddressloop: clrIAR0 ;clearthedataataddressdefinedbyMP0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loopcontinue:

Theimportantpointtonotehereisthatintheexampleshownabove,noreferenceismadetospecificDataMemoryaddresses.

Rev. 1.00 8 st 1 01 Rev. 1.00 9 st 1 01



Bank Pointer – BPFor thisdevice, theDataMemory isdivided into twobanks,Bank0andBank1.Selecting therequiredDataMemoryareaisachievedusingtheBankPointer.Bit0oftheBankPointerisusedtoselectDataMemoryBanks0~1.

TheDataMemoryis initialised toBank0afterareset,exceptforaWDTtime-outreset in theSLEEP/IDLEMode,inwhichcase,theDataMemorybankremainsunaffected.ItshouldbenotedthattheSpecialFunctionDataMemoryisnotaffectedbythebankselection,whichmeansthattheSpecialFunctionRegisterscanbeaccessedfromwithinanybank.Directlyaddressing theDataMemorywillalwaysresultinBank0beingaccessedirrespectiveofthevalueoftheBankPointer.AccessingdatafromBank1mustbeimplementedusingIndirectAddressing.

BP Register

Bit 7 6 5 4 3 2 1 0Name — — — — — — — DMBP0R/W — — — — — — — R/WPOR — — — — — — — 0

Bit7~1 Unimplemented,readas“0”Bit0 DMBP0:SelectDataMemoryBanks

0:Bank01:Bank1

Accumulator – ACC TheAccumulator iscentral to theoperationofanymicrocontrollerand isclosely relatedwithoperationscarriedoutby theALU.TheAccumulator is theplacewhereall intermediateresultsfromtheALUarestored.Without theAccumulator itwouldbenecessary towrite theresultofeachcalculationorlogicaloperationsuchasaddition,subtraction,shift,etc., totheDataMemoryresultinginhigherprogrammingandtimingoverheads.Data transferoperationsusually involvethetemporarystoragefunctionoftheAccumulator;forexample,whentransferringdatabetweenoneuser-definedregisterandanother, it isnecessary todo thisbypassing thedata throughtheAccumulatorasnodirecttransferbetweentworegistersispermitted.

Program Counter Low Register – PCL Toprovideadditionalprogramcontrolfunctions, the lowbyteof theProgramCounter ismadeaccessibletoprogrammersbylocatingitwithintheSpecialPurposeareaoftheDataMemory.Bymanipulatingthisregister,directjumpstootherprogramlocationsareeasilyimplemented.LoadingavaluedirectlyintothisPCLregisterwillcauseajumptothespecifiedProgramMemorylocation,however,astheregisterisonly8-bitwide,onlyjumpswithinthecurrentProgramMemorypagearepermitted.Whensuchoperationsareused,notethatadummycyclewillbeinserted.

Look-up Table Registers – TBLP, TBHP, TBLH Thesethreespecialfunctionregistersareusedtocontroloperationof thelook-uptablewhichisstoredintheProgramMemory.TBLPandTBHParethetablepointersandindicate thelocationwhere the tabledata is located.Theirvaluemustbesetupbeforeany tablereadcommandsareexecuted.Theirvaluecanbechanged,forexampleusingthe“INC”or“DEC”instructions,allowingforeasytabledatapointingandreading.TBLHisthelocationwherethehighorderbyteofthetabledataisstoredafteratablereaddatainstructionhasbeenexecuted.Notethatthelowerordertabledatabyteistransferredtoauserdefinedlocation.

Rev. 1.00 30 st 1 01 Rev. 1.00 31 st 1 01



Status Register – STATUS This8-bitregistercontainsthezeroflag(Z),carryflag(C),auxiliarycarryflag(AC),overflowflag(OV),powerdownflag(PDF),andwatchdogtime-outflag(TO).Thesearithmetic/logicaloperationandsystemmanagementflagsareusedtorecordthestatusandoperationofthemicrocontroller.

WiththeexceptionoftheTOandPDFflags,bitsinthestatusregistercanbealteredbyinstructionslikemostotherregisters.AnydatawrittenintothestatusregisterwillnotchangetheTOorPDFflag.Inaddition,operationsrelatedtothestatusregistermaygivedifferentresultsduetothedifferentinstructionoperations.TheTOflagcanbeaffectedonlybyasystempower-up,aWDTtime-outorbyexecutingthe“CLRWDT”or“HALT”instruction.ThePDFflagisaffectedonlybyexecutingthe“HALT”or“CLRWDT”instructionorduringasystempower-up.

TheZ,OV,ACandCflagsgenerallyreflectthestatusofthelatestoperations.

• Cissetifanoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation;otherwiseCiscleared.Cisalsoaffectedbyarotatethroughcarryinstruction.

• ACissetifanoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction;otherwiseACiscleared.

• Zissetiftheresultofanarithmeticorlogicaloperationiszero;otherwiseZiscleared.

• OVissetifanoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbit,orviceversa;otherwiseOViscleared.

• PDFisclearedbyasystempower-uporexecutingthe“CLRWDT”instruction.PDFissetbyexecutingthe“HALT”instruction.

• TOisclearedbyasystempower-uporexecutingthe“CLRWDT”or“HALT”instruction.TOissetbyaWDTtime-out.

Inaddition,onenteringaninterruptsequenceorexecutingasubroutinecall,thestatusregisterwillnotbepushedontothestackautomatically.Ifthecontentsofthestatusregistersareimportantandifthesubroutinecancorruptthestatusregister,precautionsmustbetakentocorrectlysaveit.

STATUS Register

Bit 7 6 5 4 3 2 1 0Name — — TO PDF OV Z C CR/W — — R R R/W R/W R/W R/WPOR — — 0 0 x x x x

“x”: nknownBit7~6 Unimplemented,readas“0”Bit5 TO:WatchdogTime-OutFlag

0:Afterpoweruporexecutingthe“CLRWDT”or“HALT”instruction1:Awatchdogtime-outoccurred.

Bit4 PDF:PowerDownFlag0:Afterpoweruporexecutingthe“CLRWDT”instruction1:Byexecutingthe“HALT”instruction

Bit3 OV:OverflowFlag0:Nooverflow1:Anoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbitorviceversa.

Rev. 1.00 30 st 1 01 Rev. 1.00 31 st 1 01



Bit2 Z:ZeroFlag0:Theresultofanarithmeticorlogicaloperationisnotzero1:Theresultofanarithmeticorlogicaloperationiszero

Bit1 AC:Auxiliaryflag0:Noauxiliarycarry1:Anoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction

Bit0 C:CarryFlag0:Nocarry-out1:Anoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation

The“C”flagisalsoaffectedbyarotatethroughcarryinstruction.

EEPROM Data MemoryThisdevicecontainsanareaofinternalEEPROMDataMemory.EEPROMisbyitsnatureanon-volatile formof re-programmablememory,withdata retentionevenwhen itspowersupply isremoved.Byincorporatingthiskindofdatamemory,awholenewhostofapplicationpossibilitiesaremadeavailabletothedesigner.TheavailabilityofEEPROMstorageallowsinformationsuchasproductidentificationnumbers,calibrationvalues,specificuserdata,systemsetupdataorotherproductinformationtobestoreddirectlywithintheproductmicrocontroller.TheprocessofreadingandwritingdatatotheEEPROMmemoryhasbeenreducedtoaverytrivialaffair.

EEPROM Data Memory StructureTheEEPROMDataMemorycapacityis64×8bitsforthedevice.UnliketheProgramMemoryandRAMDataMemory, theEEPROMDataMemoryisnotdirectlymappedintomemoryspaceandisthereforenotdirectlyaddressableinthesamewayastheothertypesofmemory.ReadandWriteoperationsto theEEPROMarecarriedout insinglebyteoperationsusinganaddressandadataregisterinBank0andasinglecontrolregisterinBank1.

EEPROM RegistersThreeregisterscontroltheoveralloperationoftheinternalEEPROMDataMemory.Thesearetheaddressregister,EEA,thedataregister,EEDandasinglecontrolregister,EEC.AsboththeEEAandEEDregistersarelocatedinBank0,theycanbedirectlyaccessedinthesamewasasanyotherSpecialFunctionRegister.TheEECregisterhowever,beinglocatedinBank1,canbereadfromorwritten to indirectlyusing theMP1MemoryPointerandIndirectAddressingRegister, IAR1.BecausetheEECcontrolregister is locatedataddress40HinBank1, theMP1MemoryPointermustfirstbesettothevalue40HandtheBankPointerregisterBPsettothevalue,01H,beforeanyoperationsontheEECregisterareexecuted.

Register Name

Bit

7 6 5 4 3 2 1 0EE — — EE EE4 EE3 EE EE1 EE0EED D D6 D D4 D3 D D1 D0EEC — — — — WREN WR RDEN RD

EEPROM Registers List

Rev. 1.00 3 st 1 01 Rev. 1.00 33 st 1 01



EEA Register

Bit 7 6 5 4 3 2 1 0Name — — EE EE4 EE3 EE EE1 EE0R/W — — R/W R/W R/W R/W R/W R/WPOR — — 0 0 0 0 0 0

Bit7~6 Unimplemented,readas“0”Bit5~0 EEA5~EEA0:DataEEPROMaddressbit5~bit0

EED Register

Bit 7 6 5 4 3 2 1 0Name D D6 D D4 D3 D D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 D7~D0:DataEEPROMdatabit7~bit0

EEC Register

Bit 7 6 5 4 3 2 1 0Name — — — — WREN WR RDEN RDR/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0

Bit7~4 Unimplemented,readas“0”Bit3 WREN:DataEEPROMWriteEnable

0:Disable1:Enable

This is theDataEEPROMWriteEnableBitwhichmustbesethighbeforeDataEEPROMwriteoperationsarecarriedout.Clearingthisbit tozerowill inhibitDataEEPROMwriteoperations.

Bit2 WR:EEPROMWriteControl0:Writecyclehasfinished1:Activateawritecycle

This is theDataEEPROMWriteControlBitandwhensethighbytheapplicationprogramwillactivateawritecycle.Thisbitwillbeautomaticallyresettozerobythehardwareafterthewritecyclehasfinished.SettingthisbithighwillhavenoeffectiftheWRENhasnotfirstbeensethigh.

Bit1 RDEN:DataEEPROMReadEnable0:Disable1:Enable

This is theDataEEPROMReadEnableBitwhichmustbesethighbeforeDataEEPROMreadoperationsarecarriedout.Clearingthisbit tozerowill inhibitDataEEPROMreadoperations.

Bit0 RD:EEPROMReadControl0:Readcyclehasfinished1:Activateareadcycle

This is theDataEEPROMReadControlBitandwhensethighbytheapplicationprogramwillactivateareadcycle.Thisbitwillbeautomaticallyresettozerobythehardwareafterthereadcyclehasfinished.SettingthisbithighwillhavenoeffectiftheRDENbithasnotfirstbeensethigh.

Note:TheWREN,WR,RDENandRDcannotbesethighatthesametimeinoneinstruction.TheWRandRDcannotbesethighatthesametime.

Rev. 1.00 3 st 1 01 Rev. 1.00 33 st 1 01



Reading Data from the EEPROMToreaddatafromtheEEPROM,thereadenablebit,RDEN,intheEECregistermustfirstbesethightoenablethereadfunction.TheEEPROMaddressofthedatatobereadmustthenbeplacedintheEEAregister.IftheRDbitintheEECregisterisnowsethigh,areadcyclewillbeinitiated.SettingtheRDbithighwillnotinitiateareadoperationif theRDENbithasnotbeenset.Whenthereadcycleterminates,theRDbitwillbeautomaticallyclearedtozero,afterwhichthedatacanbereadfromtheEEDregister.ThedatawillremainintheEEDregisteruntilanotherreadorwriteoperationisexecuted.Theapplicationprogramcanpoll theRDbit todeterminewhenthedataisvalidforreading.

Writing Data to the EEPROMTheEEPROMaddressofthedatatobewrittenmustfirstbeplacedintheEEAregisterandthedataplacedintheEEDregister.TowritedatatotheEEPROM,thewriteenablebit,WREN,intheEECregistermustfirstbesethightoenablethewritefunction.Afterthis,theWRbitintheEECregistermustbe immediatelysethighto initiateawritecycle.These twoinstructionsmustbeexecutedconsecutively.Theglobal interruptbitEMIshouldalsofirstbeclearedbefore implementinganywriteoperations,andthensetagainafterthewritecyclehasstarted.NotethatsettingtheWRbithighwillnotinitiateawritecycleiftheWRENbithasnotbeenset.AstheEEPROMwritecycleiscontrolledusinganinternaltimerwhoseoperationisasynchronoustomicrocontrollersystemclock,acertaintimewillelapsebeforethedatawillhavebeenwrittenintotheEEPROM.DetectingwhenthewritecyclehasfinishedcanbeimplementedeitherbypollingtheWRbitintheEECregisterorbyusingtheEEPROMinterrupt.Whenthewritecycleterminates,theWRbitwillbeautomaticallycleared tozeroby themicrocontroller, informing theuser that thedatahasbeenwritten to theEEPROM.TheapplicationprogramcanthereforepolltheWRbittodeterminewhenthewritecyclehasended.

Write ProtectionProtectionagainst inadvertentwriteoperation isprovided inseveralways.After thedevice ispowered-on theWriteEnablebit in thecontrol registerwillbeclearedpreventinganywriteoperations.Alsoatpower-ontheBankPointer,BP,willbereset tozero,whichmeansthatDataMemoryBank0willbeselected.AstheEEPROMcontrolregisterislocatedinBank1,thisaddsafurthermeasureofprotectionagainstspuriouswriteoperations.Duringnormalprogramoperation,ensuringthattheWriteEnablebitinthecontrolregisterisclearedwillsafeguardagainstincorrectwriteoperations.

EEPROM InterruptTheEEPROMwriteinterruptisgeneratedwhenanEEPROMwritecyclehasended.TheEEPROMinterruptmustfirstbeenabledbysettingtheDEEbit in therelevant interruptregister.WhenanEEPROMwritecycleends,theDEFrequestflagwillbeset.IftheglobalandEEPROMinterruptsareenabledand thestack isnot full,a jump to theassociatedEEPROMInterruptvectorwilltakeplace.When theEEPROMinterrupt isserviced, theEEPROMinterrupt flagDEFwillbeautomaticallycleared.TheEMIbitwillalsobeautomaticallyclearedtodisableother interrupts.MoredetailscanbeobtainedintheInterruptsection.

Rev. 1.00 34 st 1 01 Rev. 1.00 3 st 1 01



Programming ConsiderationsCaremustbe taken thatdata isnot inadvertentlywritten to theEEPROM.ProtectioncanbeenhancedbyensuringthattheWriteEnablebitisnormallyclearedtozerowhennotwriting.AlsotheBankPointercouldbenormallyclearedtozeroasthiswouldinhibitaccesstoBank1wheretheEEPROMcontrolregisterexist.Althoughcertainlynotnecessary,considerationmightbegivenintheapplicationprogramtothecheckingofthevalidityofnewwritedatabyasimplereadbackprocess.

WhenwritingdatatheWRbitmustbesethighimmediatelyaftertheWRENbithasbeensethigh,toensurethewritecycleexecutescorrectly.Theglobal interruptbitEMIshouldalsobeclearedbeforeawritecycleisexecutedandthenre-enabledafterthewritecyclestarts.Notethatthedeviceshouldnotenter theIDLEorSLEEPmodeuntil theEEPROMreadorwriteoperationis totallycomplete.Otherwise,theEEPROMreadorwriteoperationwillfail.

Programming Examples

Reading data from the EEPROM – polling methodMOV A,EEPROM_ADRES ;userdefinedaddressMOV EEA,AMOV A,040H ;setupmemorypointerMP1MOV MP1,A ;MP1pointstoEECregisterMOV A,01H ;setupBankpointerMOV BP,ASET IAR1.1 ;setRDENbit,enablereadoperationsSET IAR1.0 ;startReadCycle-setRDbitBACK:SZ IAR1.0 ;checkforreadcycleendJMP BACKCLR IAR1 ;disableEEPROMreadCLR BPMOV A,EED ;movereaddatatoregisterMOV READ_DATA,A

Writing Data to the EEPROM – polling methodMOV A,EEPROM_ADRES ;userdefinedaddressMOV EEA,AMOV A,EEPROM_DATA ;userdefineddataMOV EED,AMOV A,040H ;setupmemorypointerMP1MOV MP1,A ;MP1pointstoEECregisterMOV A,01H ;setupBankpointerMOV BP,ACLR EMISET IAR1.3 ;setWRENbit,enablewriteoperationsSET IAR1.2 ;startWriteCycle-setWRbit–executedimmediately ;aftersetWRENbitSETEMIBACK:SZ IAR1.2 ;checkforwritecycleendJMP BACKCLR IAR1 ;disableEEPROMwriteCLR BP

Rev. 1.00 34 st 1 01 Rev. 1.00 3 st 1 01



OscillatorsVariousoscillatoroptionsoffer theuserawide rangeof functionsaccording to theirvariousapplication requirements.The flexible featuresof theoscillator functionsensure that thebestoptimisationcanbeachievedintermsofspeedandpowersaving.Oscillatorselectionsandoperationareselectedthroughrelevantcontrolregisters.

Oscillator OverviewInadditiontobeingthesourceofthemainsystemclocktheoscillatorsalsoprovideclocksourcesfortheWatchdogTimerandTimeBaseInterrupts.Twofullyintegratedinternaloscillators,requiringnoexternalcomponents,areprovidedtoformawiderangeofbothfastandslowsystemoscillators.Alloscillatoroptionsareselectedthroughtheregisters.Thehigherfrequencyoscillatorsprovidehigherperformancebutcarrywith it thedisadvantageofhigherpowerrequirements,while theoppositeisofcoursetruefor thelowerfrequencyoscillators.Withthecapabilityofdynamicallyswitchingbetween fastandslowsystemclock, thedevicehave the flexibility tooptimize theperformance/powerratio,afeatureespeciallyimportantinpowersensitiveportableapplications.

Type Name Freq.Internal Hih Speed RC HIRC /4MHzInternal Low Speed RC LIRC 3kHz

Oscillator Types

System Clock Configurations Thereare twomethodsofgeneratingthesystemclock,ahighspeedoscillatoranda lowspeedoscillator.Thehighspeedoscillator is the internal2/4MHzRCoscillator,HIRC.Thelowspeedoscillator is the internal32kHzRCoscillator,LIRC.Selectingwhether the loworhighspeedoscillatorisusedasthesystemoscillatoris implementedusingtheCKS2~CKS0bits intheSCCregisterandthesystemclockcanbedynamicallyselected.

Theactualsourceclockusedforthelowspeedoscillatorsischosenviaregisters.ThefrequencyoftheslowspeedorhighspeedsystemclockisdeterminedusingtheCKS2~CKS0bitsintheSCCregister.Notethattwooscillatorselectionsmustbemadenamelyonehighspeedandonelowspeedsystemoscillators.It isnotpossibletochooseano-oscillatorselectionforeither thehighor lowspeedoscillator.

Prescaler

fH

Hih Speed Oscillator

Low Speed Oscillator

fH/

fH/16

fH/64

fH/8

fH/4

fH/3

CKS~CKS0

fSYS

fSUBfSUB

fLIRC

SLEEPIDLE0

IDLESLEEP

LIRC

HIRCHIRCEN

System Clock Configurations

Rev. 1.00 36 st 1 01 Rev. 1.00 3 st 1 01



Internal RC Oscillator – HIRC TheinternalRCoscillatorisafullyintegratedsystemoscillatorrequiringnoexternalcomponents.The internalRCoscillator has a fixed frequencyof 2/4MHz.Device trimmingduring themanufacturingprocessandtheinclusionof internalfrequencycompensationcircuitsareusedtoensurethat theinfluenceof thepowersupplyvoltage, temperatureandprocessvariationsontheoscillationfrequencyareminimised.Asaresult,atapowersupplyof3Vor5Vandatatemperatureof25°Cdegrees,theselectedtrimmedoscillationfrequencywillhaveatolerancewithin1%.

Internal 32kHz Oscillator – LIRCTheInternal32kHzSystemOscillator isafullyintegratedRCoscillatorwithatypicalfrequencyof32kHzat5V,requiringnoexternalcomponentsforitsimplementation.Devicetrimmingduringthemanufacturingprocessandtheinclusionofinternalfrequencycompensationcircuitsareusedtoensurethattheinfluenceofthepowersupplyvoltage,temperatureandprocessvariationsontheoscillationfrequencyareminimised.Asaresult,atapowersupplyof5Vandatatemperatureof25˚Cdegrees,thefixedoscillationfrequencyof32kHzwillhaveatolerancewithin10%.

Operating Modes and System ClocksPresentdayapplicationsrequirethat theirmicrocontrollershavehighperformancebutoftenstilldemandthattheyconsumeaslittlepoweraspossible,conflictingrequirementsthatareespeciallytrueinbatterypoweredportableapplications.Thefastclocksrequiredforhighperformancewillbytheirnatureincreasecurrentconsumptionandofcourseviceversa,lowerspeedclocksreducecurrentconsumption.Asbothhighandlowspeedclocksourcesareprovidedthemeanstoswitchbetweenthemdynamically,theusercanoptimisetheoperationoftheirmicrocontrollertoachievethebestperformance/powerratio.

System ClocksThedevicehasdifferentclocksources forboth theCPUandperipheral functionoperation.Byprovidingtheuserwithawiderangeofclockselectionsusingregisterprogramming,aclocksystemcanbeconfiguredtoobtainmaximumapplicationperformance.

Themainsystemclock,cancomefromeitherahighfrequency,fH,orlowfrequency,fSUB,andisselectedusingtheCKS2~CKS0bits intheSCCregister.ThehighspeedsystemclockissourcedfromtheHIRCoscillator.ThelowspeedsystemclocksourcecanbesourcedfromtheinternalclockfSUB.IffSUBisselectedthenitcanbesourcedfromtheLIRCoscillator.Theotherchoice,whichisadividedversionofthehighspeedsystemoscillatorhasarangeoffH/2~fH/64.

Rev. 1.00 36 st 1 01 Rev. 1.00 3 st 1 01



Prescaler

fH

Hih Speed Oscillator

Low Speed Oscillator

fH/

fH/16

fH/64

fH/8

fH/4

fH/3

CKS~CKS0

fSYS

fSUBfSUB

SLEEPIDLE0

IDLESLEEP

LIRC

HIRCHIRCEN

fLIRC

LVD

Time Base 0

Prescaler

TB0[:0]Time Base 1

WDT

LVR

fSYS/4fSYS

Device Clock Configurations

Note:WhenthesystemclocksourcefSYSisswitchedtofSUBfromfH,thehighspeedoscillatorcanbestoppedtoconservethepowerorcontinuetooscillatetoprovidetheclocksource,fH~fH/64,forperipheralcircuittouse,whichisdeterminedbyconfiguringthecorrespondinghighspeedoscillatorenablecontrolbit.

System Operation ModesThere are six differentmodesof operation for themicrocontroller, eachonewith its ownspecial characteristics andwhichcanbe chosenaccording to the specificperformanceandpowerrequirementsof theapplication.Thereare twomodesallowingnormaloperationof themicrocontroller,theFASTModeandSLOWMode.Theremainingfourmodes,theSLEEP,IDLE0,IDLE1andIDLE2ModeareusedwhenthemicrocontrollerCPUisswitchedofftoconservepower.

Operation Mode CPU

Register SettingfSYS fH fSUB fLIRC

FHIDEN FSIDEN CKS2~CKS0FST On x x 000~110 fH~fH/64 On On OnSLOW On x x 111 fSUB On/Off (1) On On

IDLE0 Off 0 1000~110 Off

Off On On111 On

IDLE1 Off 1 1 xxx On On On On

IDLE Off 1 0000~110 On

On Off On111 Off

SLEEP Off 0 0 xxx Off Off Off On/Off()

“x”: don’t careNote:1.ThefHclockwillbeswitchedonoroffbyconfiguringthecorrespondingoscillatorenablebit in the

SLOWmode.2.ThefLIRCclockcanbeswitchedonoroffwhichiscontrolledbytheWDTfunctionbeingenabledordisabledintheSLEEPmode.

Rev. 1.00 38 st 1 01 Rev. 1.00 39 st 1 01



FAST ModeAsthenamesuggeststhisisoneofthemainoperatingmodeswherethemicrocontrollerhasallofitsfunctionsoperationalandwherethesystemclockisprovidedbythehighspeedoscillator.ThismodeoperatesallowingthemicrocontrollertooperatenormallywithaclocksourcewillcomefromtheHIRCoscillator.Thehighspeedoscillatorwillhoweverfirstbedividedbyaratiorangingfrom1to64,theactualratiobeingselectedbytheCKS2~CKS0bitsintheSCCregister.Althoughahighspeedoscillatorisused,runningthemicrocontrolleratadividedclockratioreducestheoperatingcurrent.

SLOW ModeThisisalsoamodewherethemicrocontrolleroperatesnormallyalthoughnowwithaslowerspeedclocksource.TheclocksourceusedwillbefromfSUB.ThefSUBclockisderivedfromtheLIRCoscillator.

SLEEP ModeTheSLEEPModeisenteredwhenanHALTinstructionisexecutedandwhentheFHIDENandFSIDENbitarelow.IntheSLEEPmodetheCPUwillbestopped,andthefSUBclocktoperipheralwillbestoppedtoo.HoweverthefLIRCclockcancontinuetooperateiftheWDTfunctionisenabled.

IDLE0 ModeTheIDLE0ModeisenteredwhenaHALTinstructionisexecutedandwhentheFHIDENbit intheSCCregister is lowandtheFSIDENbit intheSCCregister ishigh.IntheIDLE0ModetheCPUwillbeswitchedoffbutthelowspeedoscillatorwillbeturnedontodrivesomeperipheralfunctions.

IDLE1 ModeTheIDLE1ModeisenteredwhenanHALTinstructionisexecutedandwhentheFHIDENbitintheSCCregisterishighandtheFSIDENbitintheSCCregisterishigh.IntheIDLE1ModetheCPUwillbeswitchedoffbutboththehighandlowspeedoscillatorswillbeturnedontoprovideaclocksourcetokeepsomeperipheralfunctionsoperational.

IDLE2 ModeTheIDLE2ModeisenteredwhenanHALTinstructionisexecutedandwhentheFHIDENbitintheSCCregisterishighandtheFSIDENbitintheSCCregisterislow.IntheIDLE2ModetheCPUwillbeswitchedoffbutthehighspeedoscillatorwillbeturnedontoprovideaclocksourcetokeepsomeperipheralfunctionsoperational.

Control RegistersThe registers,SCCandHIRCC,areused tocontrol the systemclockand thecorrespondingoscillatorconfigurations.

Register Name

Bit

7 6 5 4 3 2 1 0SCC CKS CKS1 CKS0 — — — FHIDEN FSIDEN

HIRCC — — — — HIRC1 HIRC0 HIRCF HIRCEN

System Operating Mode Control Registers List

Rev. 1.00 38 st 1 01 Rev. 1.00 39 st 1 01



SCC Register

Bit 7 6 5 4 3 2 1 0Name CKS CKS1 CKS0 — — — FHIDEN FSIDENR/W R/W R/W R/W — — — R/W R/WPOR 0 0 0 — — — 0 0

Bit7~5 CKS2~CKS0:Systemclockselection000:fH

001:fH/2010:fH/4011:fH/8100:fH/16101:fH/32110:fH/64111:fSUB

Thesethreebitsareusedtoselectwhichclockisusedasthesystemclocksource.InadditiontothesystemclocksourcedirectlyderivedfromfHorfSUB,adividedversionofthehighspeedsystemoscillatorcanalsobechosenasthesystemclocksource.

Bit4~2 Unimplemented,readas“0”Bit1 FHIDEN:HighFrequencyoscillatorcontrolwhenCPUisswitchedoff

0:Disable1:Enable

Thisbit isusedtocontrolwhether thehighspeedoscillator isactivatedorstoppedwhentheCPUisswitchedoffbyexecutingan“HALT”instruction.

Bit0 FSIDEN:LowFrequencyoscillatorcontrolwhenCPUisswitchedoff0:Disable1:Enable

Thisbit isusedtocontrolwhether the lowspeedoscillator isactivatedorstoppedwhentheCPUisswitchedoffbyexecutingan“HALT”instruction.

HIRCC Register

Bit 7 6 5 4 3 2 1 0Name — — — — HIRC1 HIRC0 HIRCF HIRCENR/W — — — — R/W R/W R R/WPOR — — — — 0 0 0 1

Bit7~4 Unimplemented,readas“0”Bit3~2 HIRC1~HIRC0:HIRCFrequencyselection

00:2MHz01:4MHz10:Reserved11:2MHz

WhentheHIRCoscillator isenabledor theHIRCfrequencyselection ischangedbyapplicationprogram,theclockfrequencywillautomaticallybechangedafter theHIRCFflagissetto1.

Bit1 HIRCF:HIRCoscillatorstableflag0:HIRCunstable1:HIRCstable

Thisbit isusedto indicatewhether theHIRCoscillator isstableornot.WhentheHIRCENbitissetto1toenabletheHIRCoscillatorortheHIRCfrequencyselectionischangedbyapplicationprogram,theHIRCFbitwillfirstbeclearedto0andthensetto1aftertheHIRCoscillatorisstable.

Rev. 1.00 40 st 1 01 Rev. 1.00 41 st 1 01



Bit0 HIRCEN:HIRCoscillatorenablecontrol0:Disable1:Enable

Operating Mode SwitchingThedevicecanswitchbetweenoperatingmodesdynamicallyallowingtheusertoselect thebestperformance/powerratiofor thepresent taskinhand.Inthiswaymicrocontrolleroperationsthatdonotrequirehighperformancecanbeexecutedusingslowerclocksthusrequiringlessoperatingcurrentandprolongingbatterylifeinportableapplications.

Insimpleterms,ModeSwitchingbetweentheFASTModeandSLOWModeisexecutedusingtheCKS2~CKS0bitsintheSCCregisterwhileModeSwitchingfromtheFAST/SLOWModestotheSLEEP/IDLEModesisexecutedviatheHALTinstruction.WhenanHALTinstructionisexecuted,whetherthedeviceenterstheIDLEModeortheSLEEPModeisdeterminedbytheconditionoftheFHIDENandFSIDENbitsintheSCCregister.

FASTfSYS=fH~fH/64

fH onCPU rnfSYS onfSUB on

SLOWfSYS=fSUBfSUB on

CPU rnfSYS onfH on/off

IDLE0HLT instrction exected

CPU stopFHIDEN=0FSIDEN=1

fH offfSUB on



fH onfSUB on



fH onfSUB off

SLEEPHLT instrction exected


fH offfSUB off

Rev. 1.00 40 st 1 01 Rev. 1.00 41 st 1 01



FAST Mode to SLOW Mode SwitchingWhenrunning in theFASTMode,whichuses thehighspeedsystemoscillator,and thereforeconsumesmorepower, the systemclock can switch to run in theSLOWModeby set theCKS2~CKS0bitsto“111”intheSCCregister.Thiswillthenusethelowspeedsystemoscillatorwhichwillconsumelesspower.Usersmaydecidetodothisforcertainoperationswhichdonotrequirehighperformanceandcansubsequentlyreducepowerconsumption.

TheSLOWModeissourcedfromtheLIRCoscillatorandthereforerequires thisoscillator tobestablebeforefullmodeswitchingoccurs.

FAST Mode

SLOW Mode

CKS~CKS0 = 111

SLEEP Mode

FHIDEN=0 FSIDEN=0HLT instrction is exected

IDLE0 Mode


IDLE1 Mode


IDLE2 Mode


Rev. 1.00 4 st 1 01 Rev. 1.00 43 st 1 01



SLOW Mode to FAST Mode SwitchingInSLOWmodethesystemclockisderivedfromfSUB.WhensystemclockisswitchedbacktotheFASTmodefromfSUB, theCKS2~CKS0bitsshouldbeset to“000”~“110”andthenthesystemclockwillrespectivelybeswitchedtofH~fH/64.

However, if fH isnotused inSLOWmodeand thusswitchedoff, itwill takesometime tore-oscillateandstabilisewhenswitchingtotheFASTmodefromtheSLOWMode.ThisismonitoredusingtheHIRCFbit intheHIRCCregister.Thetimedurationrequiredforthehighspeedsystemoscillatorstabilizationisspecifiedintherelevantcharacteristics.

FAST Mode

SLOW Mode

CKS~CKS0 = 000~110

SLEEP Mode


IDLE0 Mode


IDLE1 Mode


IDLE2 Mode


Entering the SLEEP ModeThereisonlyonewayforthedevicetoentertheSLEEPModeandthatistoexecutethe“HALT”instructionintheapplicationprogramwithboththeFHIDENandFSIDENbitsintheSCCregisterequalto“0”.InthismodealltheclocksandfunctionswillbeswitchedoffexcepttheWDTfunction.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• Thesystemclockwillbestoppedandtheapplicationprogramwillstopatthe“HALT”instruction.

• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.

• TheI/Oportswillmaintaintheirpresentconditions.

• Inthestatusregister,thePowerDownflagPDFwillbeset,andWDTtimeoutflagTOwillbecleared.

• TheWDTwillbeclearedandresumecountingastheWDTisenabled.IftheWDTisdisabledthenWDTwillbeclearedandstopped.

Entering the IDLE0 ModeThereisonlyonewayforthedevicetoentertheIDLE0Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeFHIDENbitintheSCCregisterequalto“0”andtheFSIDENbitintheSCCregisterequalto“1”.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

Rev. 1.00 4 st 1 01 Rev. 1.00 43 st 1 01



• ThefHclockwillbestoppedandtheapplicationprogramwillstopatthe“HALT”instruction,butthefSUBclockwillbeon.





Entering the IDLE1 ModeThereisonlyonewayforthedevicetoentertheIDLE1Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwithboththeFHIDENandFSIDENbitsintheSCCregisterequalto“1”.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• ThefHandfSUBclockswillbeonbuttheapplicationprogramwillstopatthe“HALT”instruction.





Entering the IDLE2 ModeThereisonlyonewayforthedevicetoentertheIDLE2Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeFHIDENbitintheSCCregisterequalto“1”andtheFSIDENbitintheSCCregisterequalto“0”.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• ThefHclockwillbeonbutthefSUBclockwillbeoffandtheapplicationprogramwillstopatthe“HALT”instruction.





Standby Current ConsiderationsAsthemainreasonforenteringtheSLEEPorIDLEModeistokeepthecurrentconsumptionofthedevicetoaslowavalueaspossible,perhapsonlyintheorderofseveralmicro-ampsexceptintheIDLE1andIDLE2Mode,thereareotherconsiderationswhichmustalsobetakenintoaccountbythecircuitdesignerif thepowerconsumptionistobeminimised.SpecialattentionmustbemadetotheI/Opinsonthedevice.Allhigh-impedanceinputpinsmustbeconnectedtoeitherafixedhighorlowlevelasanyfloatinginputpinscouldcreateinternaloscillationsandresultinincreasedcurrentconsumption.Thisalsoappliestodeviceswhichhavedifferentpackagetypes,astheremaybeunbonbedpins.Thesemusteitherbesetupasoutputsorifsetupasinputsmusthavepull-highresistorsconnected.

Rev. 1.00 44 st 1 01 Rev. 1.00 4 st 1 01



Caremustalsobetakenwiththeloads,whichareconnectedtoI/Opins,whicharesetupasoutputs.Theseshouldbeplacedinaconditioninwhichminimumcurrent isdrawnorconnectedonlytoexternalcircuits thatdonotdrawcurrent,suchasotherCMOSinputs.Alsonote thatadditionalstandbycurrentwillalsoberequirediftheLIRCoscillatorhasenabled.

In theIDLE1andIDLE2Modethehighspeedoscillator ison, if theperipheral functionclocksourceisderivedfromthehighspeedoscillator,theadditionalstandbycurrentwillalsobeperhapsintheorderofseveralhundredmicro-amps.

Wake-upTominimisepowerconsumptionthedevicecanenter theSLEEPoranyIDLEMode,wheretheCPUwillbeswitchedoff.However,whenthedeviceiswokenupagain,itwilltakeaconsiderabletimefortheoriginalsystemoscillatortorestart,stabliseandallownormaloperationtoresume.

AfterthesystementerstheSLEEPorIDLEMode,itcanbewokenupfromoneofvarioussourceslistedasfollows:

• AnexternalfallingedgeonPortA

• Anexternalreset

• Asysteminterrupt

• AWDToverflow

Ifthesystemiswokenupbyanexternalreset,thedevicewillexperienceafullsystemreset.Whenthedeviceexecutes the“HALT”instruction, thePDFflagwillbeset to1.ThePDFflagwillbeclearedto0 if thedeviceexperiencesasystempower-uporexecutes theclearWatchdogTimerinstruction.IfthesystemiswokenupbyaWDToverflow,aWatchdogTimerresetwillbeinitiatedandtheTOflagwillbesetto1.TheTOflagissetifaWDTtime-outoccursandcausesawake-upthatonlyresetstheProgramCounterandStackPointer,otherflagsremainintheiroriginalstatus.

EachpinonPortAcanbesetupusingthePAWUregistertopermitanegativetransitiononthepintowakeupthesystem.WhenaPortApinwake-upoccurs,theprogramwillresumeexecutionattheinstructionfollowingthe“HALT”instruction.If thesystemiswokenupbyaninterrupt, thentwopossiblesituationsmayoccur.Thefirstiswheretherelatedinterruptisdisabledortheinterruptisenabledbutthestackisfull,inwhichcasetheprogramwillresumeexecutionattheinstructionfollowingthe“HALT”instruction.Inthissituation,theinterruptwhichwokeupthedevicewillnotbeimmediatelyserviced,butwillratherbeservicedlaterwhentherelatedinterruptisfinallyenabledorwhenastacklevelbecomesfree.Theothersituationiswheretherelatedinterruptisenabledandthestackisnotfull,inwhichcasetheregularinterruptresponsetakesplace.Ifaninterruptrequestflag issethighbeforeentering theSLEEPorIDLEMode, thewake-upfunctionof therelatedinterruptwillbedisabled.

Rev. 1.00 44 st 1 01 Rev. 1.00 4 st 1 01



Watchdog TimerTheWatchdogTimerisprovidedtopreventprogrammalfunctionsorsequencesfromjumpingtounknownlocations,duetocertainuncontrollableexternaleventssuchaselectricalnoise.

Watchdog Timer Clock SourceTheWatchdogTimerclocksource isprovidedby the internalclock, fLIRC,which issuppliedbytheLIRCoscillator.TheLIRCinternaloscillatorhasanapproximatefrequencyof32kHzandthisspecifiedinternalclockperiodcanvarywithVDD,temperatureandprocessvariations.TheWatchdogTimersourceclockisthensubdividedbyaratioof28to218togivelongertimeouts,theactualvaluebeingchosenusingtheWS2~WS0bitsintheWDTCregister.

Watchdog Timer Control RegisterAsingleregister,WDTC,controlstherequiredtimeoutperiodaswellastheenable/disableandresetMCUoperation.

WDTC Register

Bit 7 6 5 4 3 2 1 0Name WE4 WE3 WE WE1 WE0 WS WS1 WS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 1 0 1 0 0 1 1

Bit7~3 WE4~WE0:WDTfunctionsoftwarecontrol10101:Disable01010:EnableOthers:ResetMCU

Whenthesebitsarechangedbytheenvironmentalnoiseorsoftwaresettingtoresetthemicrocontroller,theresetoperationwillbeactivatedafteradelaytime,tSRESET,andtheWRFbitintheRSTFCregisterwillbesethigh.

Bit2~0 WS2~WS0:WDTtime-outperiodselection000:28/fLIRC001:210/fLIRC010:212/fLIRC011:214/fLIRC100:215/fLIRC101:216/fLIRC110:217/fLIRC111:218/fLIRC

These threebitsdetermine thedivisionratioof thewatchdog timersourceclock,whichinturndeterminesthetime-outperiod.

RSTFC Register

Bit 7 6 5 4 3 2 1 0Name — — — — RSTF LVRF — WRFR/W — — — — R/W R/W — R/WPOR — — — — 0 x — 0

“x”: nknownBit7~4 Unimplemented,readas“0”Bit3 RSTF:Resetcontrolregistersoftwareresetflag

DescribedelsewhereBit2 LVRF:LVRfunctionresetflag

Describedelsewhere

Rev. 1.00 46 st 1 01 Rev. 1.00 4 st 1 01



Bit1 Unimplemented,readas“0”Bit0 WRF:WDTControlRegisterSoftwareResetFlag

0:Notoccur1:Occurred

Thisbit issethighbytheWDTControlregistersoftwareresetandclearedbytheapplicationprogram.Notethatthisbitcanonlybeclearedtozerobytheapplicationprogram.

Watchdog Timer OperationTheWatchdogTimeroperatesbyprovidingadeviceresetwhenits timeroverflows.ThismeansthatintheapplicationprogramandduringnormaloperationtheuserhastostrategicallycleartheWatchdogTimerbeforeitoverflowstopreventtheWatchdogTimerfromexecutingareset.Thisisdoneusingtheclearwatchdoginstructions.Iftheprogrammalfunctionsforwhateverreason,jumpstoanunknownlocation,orentersanendlessloop,theseclearinstructionswillnotbeexecutedinthecorrectmanner,inwhichcasetheWatchdogTimerwilloverflowandresetthedevice.Therearefivebits,WE4~WE0,intheWDTCregistertooffertheenable/disablecontrolandresetcontroloftheWatchdogTimer.TheWDTfunctionwillbedisabledwhentheWE4~WE0bitsaresettoavalueof10101BwhiletheWDTfunctionwillbeenablediftheWE4~WE0bitsareequalto01010B.IftheWE4~WE0bitsaresettoanyothervalues,otherthan01010Band10101B,itwillresetthedeviceafteradelaytime,tSRESET.Afterpoweronthesebitswillhaveavalueof01010B.

WE4 ~ WE0 Bits WDT Function10101B Disable01010B Enable

ny other vales Reset MCU

Watchdog Timer Enable/Disable Control

Undernormalprogramoperation,aWatchdogTimertime-outwill initialiseadeviceresetandsetthestatusbitTO.However,ifthesystemisintheSLEEPorIDLEMode,whenaWatchdogTimertime-outoccurs,theTObitinthestatusregisterwillbesetandonlytheProgramCounterandStackPointerwillbereset.Fourmethodscanbeadoptedtoclear thecontentsof theWatchdogTimer.ThefirstisaWDTreset,whichmeansacertainvalueexcept01010Band10101BwrittenintotheWE4~WE0bitfiled,thesecondisusingtheWatchdogTimersoftwareclearinstructionandthethirdisviaaHALTinstruction.Thelastisanexternalhardwarereset,whichmeansalowlevelontheexternalresetpiniftheexternalresetpinexistsbytheRSTCregister.

ThereisonlyonemethodofusingsoftwareinstructiontocleartheWatchdogTimer.Thatistousethesingle“CLRWDT”instructiontocleartheWDT.

Themaximumtimeoutperiod iswhenthe218divisionratio isselected.Asanexample,witha32kHzLIRCoscillatorasitssourceclock,thiswillgiveamaximumwatchdogperiodofaround8secondsforthe218divisionratio,andaminimumtimeoutof8msforthe28divisionration.

“CLR WDT”Instrction

8-stae Divider WDT Prescaler

WE4~WE0 bitsWDTC Reister Reset MCU

fLIRC

fLIRC/8

8-to-1 MUX

CLR

WS~WS0 WDT Time-ot(8/fLIRC ~ 18/fLIRC)

“HLT”Instrction

RES pin reset

Watchdog Timer

Rev. 1.00 46 st 1 01 Rev. 1.00 4 st 1 01



Reset and Initialisation Aresetfunctionisafundamentalpartofanymicrocontrollerensuringthat thedevicecanbesettosomepredeterminedcondition irrespectiveofoutsideparameters.Themost important resetconditionisafterpowerisfirstappliedtothemicrocontroller.Inthiscase, internalcircuitrywillensure that themicrocontroller,afterashortdelay,willbe inawell-definedstateandready toexecutethefirstprograminstruction.Afterthispower-onreset,certainimportantinternalregisterswillbesettodefinedstatesbeforetheprogramcommences.OneoftheseregistersistheProgramCounter,whichwillberesettozeroforcingthemicrocontrollertobeginprogramexecutionfromthelowestProgramMemoryaddress.

Inadditiontothepower-onreset,situationsmayarisewhereit isnecessarytoforcefullyapplyaresetconditionwhenthemicrocontrollerisalreadyrunning,theRESlineisforcefullypulledlow.Insuchacase,knownasanormaloperationreset,someof themicrocontrollerregistersremainunchangedallowingthemicrocontroller topreceedwithnormaloperationafter thereset line isallowedtoreturnhigh.

TheWatchdogTimeroverflowisoneofmanyresettypesandwillresetthemicrocontroller.AnotherresetexistsintheformofaLowVoltageReset,LVR,whereafullreset,similartotheRESresetisimplementedinsituationswherethepowersupplyvoltagefallsbelowacertainthreshold.Alltypesofresetoperationsresultindifferentregisterconditionsbeingsetup.

Reset FunctionsThereareseveralwaysinwhichamicrocontrollerresetcanoccur, througheventsoccurringbothinternallyandexternally.

Power-on Reset Themostfundamentalandunavoidablereset is theonethatoccursafterpowerisfirstappliedtothemicrocontroller.AswellasensuringthattheProgramMemorybeginsexecutionfromthefirstmemoryaddress,apower-onresetalsoensures thatcertainother registersarepreset toknownconditions.AlltheI/OportandportcontrolregisterswillpowerupinahighconditionensuringthatallI/Oportswillbefirstsettoinputs.

VDD

Power-on Reset

SST Time-ot

tRSTD

Power-On Reset Timing Chart

RES Pin ResetAstheresetpinissharedwithI/Opins,theresetfunctionmustbeselectedusingacontrolregister,RSTC.Althoughthemicrocontrollerhasan internalRCresetfunction, if theVDDpowersupplyrise timeisnotfastenoughordoesnotstabilisequicklyatpower-on, the internalresetfunctionmaybeincapableofprovidingproperresetoperation.For thisreasonit isrecommendedthatanexternalRCnetworkisconnectedtotheRESpin,whoseadditionaltimedelaywillensurethattheRESpinremainslowforanextendedperiodtoallowthepowersupplytostabilise.Duringthistimedelay,normaloperationofthemicrocontrollerwillbeinhibited.AftertheRESlinereachesacertainvoltagevalue,theresetdelaytime,tRSTD,isinvokedtoprovideanexteadelaytimeafterwhichthemicrocontrollerwillbeginnormaloperation.TheabbreviationSSTinthefiguresstandsforSystemStart-upTime.FormostapplicationsaresistorconnectedbetweenVDDandtheRESlineanda

Rev. 1.00 48 st 1 01 Rev. 1.00 49 st 1 01



capacitorconnectedbetweebVSSandtheRESpinwillprovideasuitableexternalresetcircuit.Anywiringconnectedto theRESpinshouldbekeptasshortaspossible tominimiseanystraynoiseinterference.ForapplicationsthatoperatewithinanenvironmentwheremorenoiseispresenttheEnhancedResetCircuitshownisrecommended.

VDD

VDD

RES

10kΩ~100kΩ

0.01µF**

1N4148*

VSS

0.1µF~1µF300Ω*

Note:“*”ItisrecommendedthatthiscomponentisaddedforaddedESDprotection.“**”Itisrecommendedthatthiscomponentisaddedinenvironmentswherepowerlinenoise

issignificant.External RES Circuit

PullingtheRESpinlowusingexternalhardwarewillalsoexecuteadevicereset.Inthiscase,asinthecaseofotherresets,theProgranCounterwillresettozeroandprogramexecutioninitiatedfromthispoint.

Internal Reset

tRSTD+tSST

RES

0.9VDD0.4VDD

RES Reset Timing Chart

There isan internal resetcontrol register,RSTC,which isused toselect theexternalRESpinfunctionandprovidearesetwhenthedeviceoperatesabnormallyduetotheenvironmentalnoiseinterference. If thecontentof theRSTCregister is set toanyvalueother than01010101Bor10101010B,itwillresetthedeviceafteradelaytime,tSRESET.Afterpowerontheregisterwillhaveavalueof01010101B.

RSTC7 ~ RSTC0 Bits Reset Function01010101B PB410101010B RES

ny other vale Reset MCU

Internal Reset Function Control

Rev. 1.00 48 st 1 01 Rev. 1.00 49 st 1 01



• RSTC Register

Bit 7 6 5 4 3 2 1 0Name RSTC RSTC6 RSTC RSTC4 RSTC3 RSTC RSTC1 RSTC0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 1 0 1 0 1 0 1

Bit7~0 RSTC7~RSTC0:Resetfunctioncontrol01010101:PB410101010:RESpinOthervalues:ResetMCU

Ifthesebitsarechangedduetoadverseenvironmentalconditions,themicrocontrollerwillbereset.Theresetoperationwillbeactivatedafteradelaytime,tSRESET,andtheRSTFbitintheRSTFCregisterwillbesetto1.Allresetswill reset thisregister toPORvalueexcept theWDTtimeouthardwarewarmreset.Note that if theregister isset to10101010toselect theRESpin, thisconfigurationhashigherprioritythanotherrelatedpin-sharedcontrols.

• RSTFC Register



0:Notoccurred1:Occurred

Thisbit isset to1by theRSTCcontrol registersoftwareresetandclearedby theapplicationprogram.Note that thisbitcanonlybecleared to0by theapplicationprogram.

Bit2 LVRF:LVRfunctionresetflagDescribedelsewhere

Bit1 Unimplemented,readas“0”Bit0 WRF:WDTcontrolregistersoftwareresetflag

Describedelsewhere

Low Voltage Reset – LVR Themicrocontrollercontainsalowvoltageresetcircuitinordertomonitorthesupplyvoltageofthedevice.TheLVRfunctionisalwaysenabledwithaspecificLVRvoltageVLVR.Ifthesupplyvoltageofthedevicedropstowithinarangeof0.9V~VLVRsuchasmightoccurwhenchangingthebattery,theLVRwillautomaticallyresetthedeviceinternallyandtheLVRFbitintheRSTFCregisterwillalsobesethigh.ForavalidLVRsignal,alowsupplyvoltage,i.e.,avoltageintherangebetween0.9V~VLVRmustexist fora timegreater than thatspecifiedby tLVR in theLVD/LVRElectricalCharacteristics.Ifthelowsupplyvoltagestatedoesnotexceedthisvalue,theLVRwillignorethelowsupplyvoltageandwillnotperformaresetfunction.TheactualVLVRvalueisfixedat2.1V.NotethattheLVRfunctionwillbeautomaticallydisabledwhenthedeviceenterstheIDLE/SLEEPmode.

LVR

Internal Reset

tRSTD + tSST

Low Voltage Reset Timing Chart

Rev. 1.00 0 st 1 01 Rev. 1.00 1 st 1 01



• RSTFC Register



DescribedelsewhereBit2 LVRF:LVRfunctionresetflag

0:Notoccur1:Occurred

ThisbitissethighwhenaspecificLowVoltageResetsituationconditionoccurs.Thisbitcanonlybeclearedtozerobytheapplicationprogram.

Bit1 Unimplemented,readas“0”Bit0 WRF:WDTControlregistersoftwareresetflag

Describedelsewhere

Watchdog Time-out Reset during Normal Operation TheWatchdogtime-outResetduringnormaloperationis thesameashardwarelowvoltageresetexceptthattheWatchdogtime-outflagTOwillbesethigh.

WDT Time-ot

Internal Reset

tRSTD + tSST

WDT Time-out Reset during Normal Operation Timing Chart

Watchdog Time-out Reset during SLEEP or IDLE Mode TheWatchdogtime-outResetduringSLEEPorIDLEModeisa littledifferentfromotherkindsofreset.MostoftheconditionsremainunchangedexceptthattheProgramCounterandtheStackPointerwillbeclearedtozeroandtheTOflagwillbesethigh.RefertotheSystemStartUpTimeCharacteristicsfortSSTdetails.

WDT Time-ot

Internal Reset

tSST

WDT Time-out Reset during Sleep or IDLE Mode Timing Chart

Reset Initial Conditions Thedifferent typesofresetdescribedaffect theresetflagsindifferentways.Theseflags,knownasPDFandTOare located in thestatus registerandarecontrolledbyvariousmicrocontrolleroperations,suchas theSLEEPorIDLEModefunctionorWatchdogTimer.Thereset flagsareshowninthetable:

Rev. 1.00 0 st 1 01 Rev. 1.00 1 st 1 01



TO PDF Reset Conditions0 0 Power-on reset RES or LVR reset drin FST or SLOW Mode operation1 WDT time-ot reset drin FST or SLOW Mode operation1 1 WDT time-ot reset drin IDLE or SLEEP Mode operation

“” stands for nchanedThefollowingtableindicatesthewayinwhichthevariouscomponentsofthemicrocontrollerareaffectedafterapower-onresetoccurs.

Item Condition after ResetProram Conter Reset to zeroInterrpts ll interrpts will be disabledWDT Time Bases Clear after reset WDT beins continTimer Modles Timer Modles will be trned offInpt/Otpt Ports I/O ports will be setp as inptsStack Pointer Stack Pointer will point to the top of the stack

Thedifferentkindsofresetsallaffecttheinternalregistersofthemicrocontrollerindifferentways.Toensurereliablecontinuationofnormalprogramexecutionafteraresetoccurs,itisimportanttoknowwhatconditionthemicrocontroller is inafteraparticularresetoccurs.Thefollowingtabledescribeshoweachtypeofresetaffectseachof themicrocontroller internalregisters.Note thatwheremorethanonepackagetypeexiststhetablewillreflectthesituationforthelargerpackagetype.

Register Reset (Power On)

RES Reset(Normal Operation)

LVR Reset(Normal Operation)

WDT Time-out (Normal Operation)

WDT Time-out (IDLE/SLEEP)

IR0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MP0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IR1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MP1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BP - - - - - - - 0 - - - - - - - 0 - - - - - - - 0 - - - - - - - 0 - - - - - - - CC x x x x x x x x x x x x x x x x PCL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TBLP x x x x x x x x x x x x x x x x TBLH - x x x x x x x - x x x x x x x - - - TBHP - - - - - x x x - - - - - x x x - - - - - - - - - - - - - - - STTUS - - 0 0 x x x x - - - - - - 1 - - 1 1 RSTFC - - - - 0 x - 0 - - - - - - - - - 1 - - - - - - - - - - - INTEG - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - INTC0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - INTC1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PPU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCC 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 - - - HIRCC - - - - 0 0 0 1 - - - - 0 0 0 1 - - - - 0 0 0 1 - - - - 0 0 0 1 - - - - WDTC 0 1 0 1 0 0 11 0 1 0 1 0 0 11 0 1 0 1 0 0 11 0 1 0 1 0 0 11 TB0C 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 - - - - TB1C 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 - - - -

Rev. 1.00 st 1 01 Rev. 1.00 3 st 1 01



Register Reset (Power On)

RES Reset(Normal Operation)

LVR Reset(Normal Operation)

WDT Time-out (Normal Operation)

WDT Time-out (IDLE/SLEEP)

PSCR - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - EE - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - EED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDOL x x x x - - - - x x x x - - - - x x x x - - - - x x x x - - - -

- - - -(DRFS=0) (DRFS=1)

SDOH x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x

(DRFS=0)- - - - (DRFS=1)

SDC0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDC1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVDC - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - RSTC 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 STM0C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STM0C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STM0DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STM0DH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - STM0L 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STM0H - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - PB - 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 - PBC - 1 0 1 1 1 1 1 - 1 0 1 1 1 1 1 - 1 0 1 1 1 1 1 - 1 0 1 1 1 1 1 - PBPU - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - STM1C0 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - - - -STM1C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STM1DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STM1DH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STM1L 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STM1H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STM1PR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS0 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - - - - -PS1 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - - -PBS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EEC - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - -

Note:“u”standsforunchanged“x”standsforunknown“-”standsforunimplemented

Rev. 1.00 st 1 01 Rev. 1.00 3 st 1 01



Input/Output Ports Themicrocontrollersofferconsiderable flexibilityon their I/Oports.With the inputoroutputdesignationofeverypinfullyunderuserprogramcontrol,pull-highselectionsforallportsandwake-upselectionsoncertainpins,theuserisprovidedwithanI/Ostructuretomeettheneedsofawiderangeofapplicationpossibilities.

Thedeviceprovidesbidirectional input/output lines labeledwithportnamesPA~PB.TheseI/OportsaremappedtotheRAMDataMemorywithspecificaddressesasshownintheSpecialPurposeDataMemorytable.Allof theseI/Oportscanbeusedforinputandoutputoperations.Forinputoperation,theseportsarenon-latching,whichmeanstheinputsmustbereadyattheT2risingedgeofinstruction“MOVA,[m]”,wheremdenotestheportaddress.Foroutputoperation,allthedataislatchedandremainsunchangeduntiltheoutputlatchisrewritten.

Register Name

Bit

7 6 5 4 3 2 1 0P P P6 P P4 P3 P P1 P0

PC PC PC PC PC4 PC3 PC PC1 PC0PPU PPU PPU4 PPU PPU4 PPU3 PPU PPU1 PPU0PWU PWU PWU6 PWU PWU4 PWU3 PWU PWU1 PWU0

PB — PB6 PB PB4 PB3 PB PB1 PB0PBC — PBC6 PBC PBC4 PBC3 PBC PBC1 PBC0

PBPU — PBPU6 PBPU PBPU4 PBPU3 PBPU PBPU1 PBPU0

“—”: nimplementedI/O Logic Function Registers List

Pull-high ResistorsManyproductapplicationsrequirepull-highresistorsfortheirswitchinputsusuallyrequiringtheuseofanexternal resistor.Toeliminate theneedfor theseexternal resistors,all I/Opins,whenconfiguredasaninputhavethecapabilityofbeingconnectedtoaninternalpull-highresistor.Thesepull-highresistorsareselectedusingthePAPU~PBPUregisters,andareimplementedusingweakPMOStransistors.

Notethatthepull-highresistorcanbecontrolledbytherelevantpull-highcontrolregisteronlywhenthepin-sharedfunctionalpinisselectedasadigitalinputorNMOSoutput.Otherwise,thepull-highresistorscannotbeenabled.

PAPU Register

Bit 7 6 5 4 3 2 1 0Name PPU PPU4 PPU PPU4 PPU3 PPU PPU1 PPU0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 PAPU7~PAPU0:I/OPortPA7~PA0PinPull-highFunctionControl0:Disable1:Enable

Rev. 1.00 4 st 1 01 Rev. 1.00 st 1 01



PBPU Register

Bit 7 6 5 4 3 2 1 0Name — PBPU6 PBPU PBPU4 PBPU3 PBPU PBPU1 PBPU0R/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 0 0 0 0 0

Bit7 Unimplemented,readas“0”Bit6~5 PBPU6~PBPU5:Un-bondedI/OLinePB6~PB5Pull-highControll

0:Disable1:Enable

Note:ThePB5andPB6linesoftheMCUareinternallyconncetedwiththeTXandRXlinesofthepowerlinedatatransceiver.Howevertheirpull-highfunctionscanstillbecontrolledbythesebits.

Bit4~0 PBPU4~PBPU0:I/OPortPB4~PB0PinPull-highControl0:Disable1:Enable

Port A Wake-upTheHALTinstructionforcesthemicrocontrollerintotheSLEEPorIDLEModewhichpreservespower,afeature that is importantforbatteryandother low-powerapplications.Variousmethodsexisttowake-upthemicrocontroller,oneofwhichistochangethelogicconditionononeofthePortApinsfromhightolow.Thisfunctionisespeciallysuitableforapplicationsthatcanbewokenupviaexternalswitches.EachpinonPortAcanbeselectedindividuallytohavethiswake-upfeatureusingthePAWUregister.

Note that thewake-upfunctioncanbecontrolledby thewake-upcontrol registersonlywhenthepin-sharedfunctionalpinisselectedasgeneralpurposeinput/outputandtheMCUenters theSLEEP/IDLEmode.

PAWU Register

Bit 7 6 5 4 3 2 1 0Name PWU PWU6 PWU PWU4 PWU3 PWU PWU1 PWU0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 PAWU7~PAWU0:PortAPinWake-upControl0:Disable1:Enable

I/O Port Control RegistersEachI/Oporthas itsowncontrol registerwhichcontrols the input/outputconfiguration.Withthiscontrolregister,eachCMOSoutputorinputcanbereconfigureddynamicallyundersoftwarecontrol.EachpinoftheI/Oportsisdirectlymappedtoabitinitsassociatedportcontrolregister.FortheI/Opintofunctionasaninput,thecorrespondingbitofthecontrolregistermustbewrittenasa“1”.Thiswill thenallowthelogicstateof the inputpintobedirectlyreadbyinstructions.Whenthecorrespondingbitofthecontrolregisteriswrittenasa“0”,theI/OpinwillbesetupasaCMOSoutput.Ifthepiniscurrentlysetupasanoutput,instructionscanstillbeusedtoreadtheoutputregister.However,itshouldbenotedthattheprogramwillinfactonlyreadthestatusoftheoutputdatalatchandnottheactuallogicstatusoftheoutputpin.

Rev. 1.00 4 st 1 01 Rev. 1.00 st 1 01



PAC Register

Bit 7 6 5 4 3 2 1 0Name PC PC PC PC4 PC3 PC PC1 PC0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 1 1 1 1 1 1 1 1

Bit7~0 PAC7~PAC0:I/OPortPA7~PA0PinTypeSelection0:Output1:Input

PBC Register

Bit 7 6 5 4 3 2 1 0Name — PBC6 PBC PBC4 PBC3 PBC PBC1 PBC0R/W — R/W R/W R/W R/W R/W R/W R/WPOR — 1 0 1 1 1 1 1

Bit7 Unimplemented,readas“0”Bit6 PBC6:Un-bondedPB6I/OLineType

As thePB6 line is internallyconnectedwith theRX lineof thepower linedatatransceiver,thisbitshouldbefixedat“1”toselecttheinputtype.

Bit5 PBC5:Un-bondedPB5I/OLineTypeAs thePB5 line is internallyconnectedwith theTX lineof thepower linedatatransceiver,thisbitshouldbefixedat“0”toselecttheoutputtype.

Bit4~0 PBC4~PBC0:I/OPortPB4~PB0Input/OutputControl0:Output1:Input

Pin-shared FunctionsTheflexibilityofthemicrocontrollerrangeisgreatlyenhancedbytheuseofpinsthathavemorethanonefunction.Limitednumbersofpinscanforceseriousdesignconstraintsondesignersbutbysupplyingpinswithmulti-functions,manyofthesedifficultiescanbeovercome.Forthesepins,thedesiredfunctionofthemulti-functionI/Opinsisselectedbyaseriesofregistersviatheapplicationprogramcontrol.

Pin-shared Function Selection RegistersThelimitednumberofsuppliedpinsinapackagecanimposerestrictionsontheamountoffunctionsacertaindevicecancontain.Howeverbyallowingthesamepinstoshareseveraldifferentfunctionsandprovidingameansoffunctionselection,awiderangeofdifferentfunctionscanbeincorporatedintoevenrelativelysmallpackagesizes.Thedevice includesPort“x”outputfunctionSelectionregister“n”,labeledasPxSn,whichcanselectthedesiredfunctionsofthemulti-functionpin-sharedpins.

When thepin-shared input function isselected tobeused, thecorresponding inputandoutputfunctionsselectionshouldbeproperlymanaged.However, if theexternal interrupt function isselectedtobeused,therelevantoutputpin-sharedfunctionshouldbeselectedasanI/Ofunctionandtheinterruptinputsignalshouldbeselected.

Themostimportantpoint tonoteis tomakesurethat thedesiredpin-sharedfunctionisproperlyselectedandalsodeselected.Formostpin-sharedfunctions,toselectthedesiredpin-sharedfunction,thepin-sharedfunctionshouldfirstbecorrectlyselectedusingthecorrespondingpin-sharedcontrolregister.After that thecorrespondingperipheralfunctionalsettingshouldbeconfiguredandthentheperipheralfunctioncanbeenabled.However,specialpointmustbenotedforsomedigitalinputpins,suchasINT,STCKn,etc,whichsharethesamepin-sharedcontrolconfigurationwiththeir

Rev. 1.00 6 st 1 01 Rev. 1.00 st 1 01



correspondinggeneralpurposeI/Ofunctionswhensettingtherelevantfunctions,inadditiontothenecessarypin-sharedcontrolandperipheral functionalsetupaforementioned, theymustalsobesetupasinputbysettingthecorrespondingbitintheI/Oportcontrolregister.Tocorrectlydeselectthepin-sharedfunction,theperipheralfunctionshouldfirstbedisabledandthenthecorrespondingpin-sharedfunctioncontrolregistercanbemodifiedtoselectotherpin-sharedfunctions.

Register Name

Bit

7 6 5 4 3 2 1 0PS0 PS0 PS06 — — PS03 PS0 — —PS1 PS1 PS16 PS1 PS14 PS13 PS1 — —PBS0 PBS0 PBS06 PBS0 PBS04 PBS03 PBS0 PBS01 PBS00

Pin-shared Function Selection Registers List

• PAS0 Register

Bit 7 6 5 4 3 2 1 0Name PS0 PS06 — — PS03 PS0 — —R/W R/W R/W — — R/W R/W — —POR 0 0 — — 0 0 — —

Bit7~6 PAS07~PAS06:PA3pin-sharedfunctionselection00/10/11:PA3/STCK001:AN4

Bit5~4 Unimplemented,readas“0”Bit3~2 PAS03~PAS02:PA1pin-sharedfunctionselection

00/11:PA101:STP010:VREF

Bit1~0 Unimplemented,readas“0”

• PAS1 Register

Bit 7 6 5 4 3 2 1 0Name PS1 PS16 PS1 PS14 PS13 PS1 — —R/W R/W R/W R/W R/W R/W R/W — —POR 0 0 0 0 0 0 — —

Bit7~6 PAS17~PAS16:PA7pin-sharedfunctionselection00/10/11:PA701:AN7

Bit5~4 PAS15~PAS14:PA6pin-sharedfunctionselection00/10/11:PA601:AN6

Bit3~2 PAS13~PAS12:PA5pin-sharedfunctionselection00/10/11:PA5/STP0I01:AN5


Rev. 1.00 6 st 1 01 Rev. 1.00 st 1 01



• PBS0 Register

Bit 7 6 5 4 3 2 1 0Name PBS0 PBS06 PBS0 PBS04 PBS03 PBS0 PBS01 PBS00R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 PBS07~PBS06:PB3pin-sharedfunctionselection00/10/11:PB301:AN3

Bit5~4 PBS05~PBS04:PB2pin-sharedfunctionselection00/10/11:PB2/STP1I01:AN2

Bit3~2 PBS03~PBS02:PB1pin-sharedfunctionselection00/10/11:PB1/STCK101:AN1

Bit1~0 PBS01~PBS00:PB0pin-sharedfunctionselection00/11:PB001:STP110:AN0

I/O Pin StructuresTheaccompanyingdiagramillustratestheinternalstructuresoftheI/Ologicfunction.Astheexactlogicalconstructionof theI/Opinwilldifferfromthisdiagram,it issuppliedasaguideonlytoassistwiththefunctionalunderstandingofthelogicfunctionI/Opins.Thewiderangeofpin-sharedstructuresdoesnotpermitalltypestobeshown.

MUX

VDD

Control Bit

Data Bit

Data Bs

Write Control Reister

Chip Reset

Read Control Reister

Read Data Reister

Write Data Reister

System Wake-p wake-p Select

I/O pin

WeakPll-p

Pll-hihReisterSelect

Q

D

CK

Q

D

CK

Q

QS

S

P only

Logic Function Input/Output Structure

Rev. 1.00 8 st 1 01 Rev. 1.00 9 st 1 01



Programming Considerations Withintheuserprogram,oneof thethingsfirst toconsider isport initialisation.Afterareset,allof theI/Odataandportcontrolregisterswillbeset tohigh.ThismeansthatallI/Opinswillbedefaultedtoaninputstate,thelevelofwhichdependsontheotherconnectedcircuitryandwhetherpull-highselectionshavebeenchosen.If theportcontrolregistersarethenprogrammedtosetupsomepinsasoutputs,theseoutputpinswillhaveaninitialhighoutputvalueunlesstheassociatedportdataregistersarefirstprogrammed.Selectingwhichpinsareinputsandwhichareoutputscanbeachievedbyte-widebyloadingthecorrectvalues into theappropriateportcontrolregisterorbyprogrammingindividualbitsintheportcontrolregisterusingthe“SET[m].i”and“CLR[m].i”instructions.Notethatwhenusingthesebitcontrolinstructions,aread-modify-writeoperationtakesplace.Themicrocontrollermustfirstreadinthedataontheentireport,modifyittotherequirednewbitvaluesandthenrewritethisdatabacktotheoutputports.

PortAhas theadditionalcapabilityofprovidingwake-upfunctions.When thedevice is in theSLEEPorIDLEMode,variousmethodsareavailabletowakethedeviceup.OneoftheseisahightolowtransitionofanyofthePortApins.SingleormultiplepinsonPortAcanbesetuptohavethisfunction.

Timer Modules – TMOneofthemostfundamentalfunctionsinanymicrocontrollerdevicesistheabilitytocontrolandmeasure time.To implement timerelatedfunctions thedevice includesseveralTimerModules,generallyabbreviatedtothenameTM.TheTMsaremulti-purposetimingunitsandservetoprovideoperationssuchasTimer/Counter,InputCapture,CompareMatchOutputandSinglePulseOutputaswellasbeingthefunctionalunitforthegenerationofPWMsignals.EachoftheTMshastwointerrupts.TheadditionofinputandoutputpinsforeachTMensuresthatusersareprovidedwithtimingunitswithawideandflexiblerangeoffeatures.

IntroductionThedevicecontains twoTMsandeach individualTMcanbecategorisedasacertain type,namelyStandardTypeTM.Althoughsimilarinnature,thedifferentTMtypesvaryintheirfeaturecomplexity.ThecommonfeaturestotheStandardtypeTMswillbedescribedinthissectionandthedetailedoperationwillbedescribedintheStandardTypeTMsection.

TM Function STMTimer/Conter √Inpt Captre √Compare Match Otpt √PWM Channels 1Sinle Plse Otpt 1PWM linment EdePWM djstment Period & Dty Dty or Period

TM Function Summary

TM OperationThedifferenttypesofTMofferadiverserangeoffunctions,fromsimpletimingoperationstoPWMsignalgeneration.ThekeytounderstandinghowtheTMoperates is tosee it in termsofafreerunningcount-upcounterwhosevalueisthencomparedwiththevalueofpre-programmedinternalcomparators.Whenthefreerunningcount-upcounterhasthesamevalueasthepre-programmedcomparator,knownasacomparematchsituation,aTMinterruptsignalwillbegeneratedwhich

Rev. 1.00 8 st 1 01 Rev. 1.00 9 st 1 01



canclearthecounterandperhapsalsochangetheconditionoftheTMoutputpin.TheinternalTMcounterisdrivenbyauserselectableclocksource,whichcanbeaninternalclockoranexternalpin.

TM Clock SourceTheclocksourcewhichdrivesthemaincounterineachTMcanoriginatefromvarioussources.TheselectionoftherequiredclocksourceisimplementedusingtheSTnCK2~STnCK0bitsintheSTMncontrolregisters,where“n”standsforthespecificTMserialnumber.Theclocksourcecanbearatioofthesystemclock,fSYS,ortheinternalhighclock,fH,thefSUBclocksourceortheexternalSTCKnpin.TheSTCKnpinclocksourceisusedtoallowanexternalsignaltodrivetheTMasanexternalclocksourceforeventcounting.

TM InterruptsTheStandard typeTMhas two internal interrupt,oneforeachof the internalcomparatorAorcomparatorP,whichgenerateaTMinterruptwhenacomparematchconditionoccurs.WhenaTMinterrupt isgenerated, itcanbeusedtoclear thecounterandalsotochangethestateof theTMoutputpin.

TM External PinsEachoftheTMshastwoTMinputpins,withthelabelSTCKnandSTPnI.TheSTMninputpin,STCKn,isessentiallyaclocksourcefortheSTMnandisselectedusingtheSTnCK2~STnCK0bitsintheSTMnC0register.ThisexternalTMinputpinallowsanexternalclocksourcetodrivetheinternalTM.TheSTCKninputpincanbechosentohaveeitherarisingorfallingactiveedge.TheSTCKnpinisalsousedastheexternaltriggerinputpininsinglepulseoutputmodefortheSTM.

Another inputpin,STPnI, is thecapture inputwhoseactiveedgecanbearisingedge,afallingedgeorboth risingandfallingedgesand theactiveedge transition type is selectedusing theSTnIO1~STnIO0bitsintheSTMnC1register.

TheTMseachhas anTMoutput pin,STPn.TheTMoutput pin canbe selectedusing thecorrespondingpin-sharedfunctionselectionbitsdescribedinthePin-sharedFunctionsection.WhentheTMisintheCompareMatchOutputMode,thesepinscanbecontrolledbytheTMtoswitchtoahighorlowlevelortotogglewhenacomparematchsituationoccurs.TheexternalSTPnoutputpinisalsothepinwheretheTMgeneratesthePWMoutputwaveform.AstheTMoutputpinsarepin-sharedwithotherfunctions,theTMoutputfunctionmustfirstbesetupusingrelevantpin-sharedfunctionselectionregister.

TM Input/Output Pin SelectionSelectingtohaveaTMinput/outputorwhethertoretainitsothersharedfunctionisimplementedusingtherelevantpin-sharedfunctionselectionregisters,withthecorrespondingselectionbits ineachpin-sharedfunctionregistercorrespondingtoaTMinput/outputpin.ConfiguringtheselectionbitscorrectlywillsetupthecorrespondingpinasaTMinput/output.Thedetailsofthepin-sharedfunctionselectionaredescribedinthepin-sharedfunctionsection.

Rev. 1.00 60 st 1 01 Rev. 1.00 61 st 1 01



STMn

STCKn

STPn

STPnICCR captre inpt

CCR otpt

Clock inpt

STM Function Pin Control Block Diagram (n=0~1)

Programming ConsiderationsTheTMCounterRegistersandtheCapture/CompareCCRAregister,allhavealowandhighbytestructure.Thehighbytescanbedirectlyaccessed,butasthelowbytescanonlybeaccessedviaaninternal8-bitbuffer,readingorwritingtotheseregisterpairsmustbecarriedoutinaspecificway.Theimportantpointtonoteisthatdatatransfertoandfromthe8-bitbufferanditsrelatedlowbyteonlytakesplacewhenawriteorreadoperationtoitscorrespondinghighbyteisexecuted.

AstheCCRAregister is implementedinthewayshowninthefollowingdiagramandaccessingthese registerpairs iscarriedout ina specificwayasdescribedabove, it is recommended touse the“MOV”instruction toaccess theCCRAlowbyteregisters,namedSTMnAL,using thefollowingaccessprocedures.AccessingtheCCRAlowbyteregisterswithoutfollowingtheseaccessprocedureswillresultinunpredictablevalues.

Data Bs

8-bit Bffer

STMnDHSTMnDL

STMnHSTMnL

STMn Conter Reister (Read only)

STMn CCR Reister (Read/Write)

Thefollowingstepsshowthereadandwriteprocedures:

• WritingDatatoCCRA♦ Step1.WritedatatoLowByteSTMnAL

– Notethatheredataisonlywrittentothe8-bitbuffer.♦ Step2.WritedatatoHighByteSTMnAH

– Heredataiswrittendirectlytothehighbyteregistersandsimultaneouslydatais latchedfromthe8-bitbuffertotheLowByteregisters.

• ReadingDatafromtheCounterRegistersandCCRA♦ Step1.ReaddatafromtheHighByteSTMnDH,STMnAH

– HeredataisreaddirectlyfromtheHighByteregistersandsimultaneouslydataislatchedfromtheLowByteregisterintothe8-bitbuffer.

♦ Step2.ReaddatafromtheLowByteSTMnDL,STMnAL– Thisstepreadsdatafromthe8-bitbuffer.

Rev. 1.00 60 st 1 01 Rev. 1.00 61 st 1 01



Standard Type TM – STMTheStandardTypeTMcontainsfiveoperatingmodes,whichareCompareMatchOutput,Timer/EventCounter,CaptureInput,SinglePulseOutputandPWMOutputmodes.TheStandardTMcanalsobecontrolledwithtwoexternalinputpinsandcandriveoneexternaloutputpin.

STM Core STM Input Pins STM Output Pin10-bit STM (STM0) STCK0 STP0I STP016-bit STM (STM1) STCK1 STP1I STP1

fSYS

fSYS/4

fH/64fH/16

fSUB

STCKn

000001010011100101110111

STnCK~STnCK0

10-bit Cont-p Conter

3-bit Comparator P

CCRP

b~b9

b0~b9

10-bit Comparator

STnONSTnPU

Comparator Match

Comparator P Match

Conter Clear 01

OtptControl

Polarity Control STPn

STnOC

STnM1 STnM0STnIO1 STnIO0

STMnF Interrpt

STMnPF Interrpt

STnPOL

CCR

STnCCLR

EdeDetector STPnI

STnIO1 STnIO0

fH/8

PinControl

STnCP

10-bit Standard Type TM Block Diagram (n=0)

fSYS

fSYS/4

fH/64fH/16

fSUB

STCKn

000001010011100101110111

STnCK~STnCK0

16-bit Cont-p Conter

8-bit Comparator P

CCRP

b8~b1

b0~b1

16-bit Comparator

STnONSTnPU

Comparator Match

Comparator P Match

Conter Clear 01

OtptControl

Polarity Control STPn

STnOC

STnM1 STnM0STnIO1 STnIO0

STMnF Interrpt

STMnPF Interrpt

STnPOL

CCR

STnCCLR

EdeDetector STPnI

STnIO1 STnIO0

fH/8

PinControl

STnCP

16-bit Standard Type TM Block Diagram (n=1)

Standard Type TM OperationThesizeofStandardTMis10-/16-bitwideanditscoreisa10-/16-bitcount-upcounterwhichisdrivenbyauserselectableinternalorexternalclocksource.Therearealsotwointernalcomparatorswiththenames,ComparatorAandComparatorP.ThesecomparatorswillcomparethevalueinthecounterwithCCRPandCCRAregisters.TheCCRPcomparator is3-/8-bitwidewhosevalueiscomparedthewithhighest3or8bitsinthecounterwhiletheCCRAisthe10/16bitsandthereforecomparesallcounterbits.

Theonlywayofchangingthevalueofthe10-/16-bitcounterusingtheapplicationprogram,istoclearthecounterbychangingtheSTnONbitfromlowtohigh.Thecounterwillalsobeclearedautomaticallybyacounteroverfloworacomparematchwithoneof itsassociatedcomparators.

Rev. 1.00 6 st 1 01 Rev. 1.00 63 st 1 01



Whentheseconditionsoccur,aSTMninterruptsignalwillalsousuallybegenerated.TheStandardTypeTMcanoperateinanumberofdifferentoperationalmodes,canbedrivenbydifferentclocksourcesincludinganinputpinandcanalsocontrolanoutputpin.Alloperatingsetupconditionsareselectedusingrelevantinternalregisters.

Standard Type TM Register DescriptionOveralloperationoftheStandardTMiscontrolledusingaseriesofregisters.Areadonlyregisterpairexists tostoretheinternalcounter10-/16-bitvalue,whilearead/writeregisterpairexists tostoretheinternal10-/16-bitCCRAvalue.TheSTMnRPregisterforthe16-bitSTMisusedtostorethe8-bitCCRPvalue.Theremainingtworegistersarecontrolregisterswhichsetupthedifferentoperatingandcontrolmodes.

RegisterName

Bit

7 6 5 4 3 2 1 0STMnC0 STnPU STnCK STnCK1 STnCK0 STnON STnRP STnRP1 STnRP0STMnC1 STnM1 STnM0 STnIO1 STnIO0 STnOC STnPOL STnDPX STnCCLRSTMnDL D D6 D D4 D3 D D1 D0STMnDH — — — — — — D9 D8STMnL D D6 D D4 D3 D D1 D0STMnH — — — — — — D9 D8

10-bit Standard Type TM Registers List (n=0)

RegisterName

Bit

7 6 5 4 3 2 1 0STMnC0 STnPU STnCK STnCK1 STnCK0 STnON — — —STMnC1 STnM1 STnM0 STnIO1 STnIO0 STnOC STnPOL STnDPX STnCCLRSTMnDL D D6 D D4 D3 D D1 D0STMnDH D1 D14 D13 D1 D11 D10 D9 D8STMnL D D6 D D4 D3 D D1 D0STMnH D1 D14 D13 D1 D11 D10 D9 D8STMnRP D D6 D D4 D3 D D1 D0

16-bit Standard Type TM Registers List (n=1)

STMnDL Register (n=0~1)

Bit 7 6 5 4 3 2 1 0Name D D6 D D4 D3 D D1 D0R/W R R R R R R R RPOR 0 0 0 0 0 0 0 0

Bit7~0 STMnCounterLowByteRegisterbit7~bit0STMn10-/16-bitCounterbit7~bit0

STMnDH Register (n=0)

Bit 7 6 5 4 3 2 1 0Name — — — — — — D9 D8R/W — — — — — — R RPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas“0”Bit1~0 STMnCounterHighByteRegisterbit1~bit0

STMn10-bitCounterbit9~bit8

Rev. 1.00 6 st 1 01 Rev. 1.00 63 st 1 01



STMnDH Register (n=1)

Bit 7 6 5 4 3 2 1 0Name D1 D14 D13 D1 D11 D10 D9 D8R/W R R R R R R R RPOR 0 0 0 0 0 0 0 0

Bit7~0 STMnCounterHighByteRegisterbit7~bit0STMn16-bitCounterbit15~bit8

STMnAL Register (n=0~1)


Bit7~0 STMnCCRALowByteRegisterbit7~bit0STMn10-/16-bitCCRAbit7~bit0

STMnAH Register (n=0)

Bit 7 6 5 4 3 2 1 0Name — — — — — — D9 D8R/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas“0”Bit1~0 STMnCCRAHighByteRegisterbit1~bit0

STMn10-bitCCRAbit9~bit8

STMnAH Register (n=1)

Bit 7 6 5 4 3 2 1 0Name D1 D14 D13 D1 D11 D10 D9 D8R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 STMnCCRAHighByteRegisterbit7~bit0STMn16-bitCCRAbit15~bit8

STMnRP Register (n=1)


Bit7~0 D7~D0:STMnCCRP8-bitregister,comparedwiththeSTMncounterbit15~bit8ComparatorPmatchperiod=0:65536STMnclocks1~255:(1~255)×256STMnclocks

TheseeightbitsareusedtosetupthevalueontheinternalCCRP8-bitregister,whichare thencomparedwith the internalcounter'shighesteightbits.Theresultof thiscomparisoncanbeselectedtocleartheinternalcounteriftheSTnCCLRbitissettozero.SettingtheSTnCCLRbittozeroensuresthatacomparematchwiththeCCRPvalueswillreset theinternalcounter.AstheCCRPbitsareonlycomparedwiththehighesteightcounterbits, thecomparevaluesexist in256clockcyclemultiples.Clearingalleightbits tozero is ineffectallowing thecounter tooverflowat itsmaximumvalue.

Rev. 1.00 64 st 1 01 Rev. 1.00 6 st 1 01



STMnC0 Register (n=0)

Bit 7 6 5 4 3 2 1 0Name STnPU STnCK STnCK1 STnCK0 STnON STnRP STnRP1 STnRP0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 STnPAU:STMnCounterPausecontrol0:Run1:Pause

Thecountercanbepausedbysettingthisbithigh.Clearingthebit tozerorestoresnormalcounteroperation.WheninaPauseconditiontheSTMnwillremainpoweredupandcontinuetoconsumepower.Thecounterwillretainitsresidualvaluewhenthisbitchangesfromlowtohighandresumecountingfromthisvaluewhenthebitchangestoalowvalueagain.

Bit6~4 STnCK2~STnCK0:SelectSTMnCounterclock000:fSYS/4001:fSYS

010:fH/16011:fH/64100:fSUB

101:fSUB

110:STCKnrisingedgeclock111:STCKnfallingedgeclock

Thesethreebitsareusedtoselect theclocksourcefor theSTMn.Theexternalpinclocksourcecanbechosentobeactiveontherisingorfallingedge.TheclocksourcefSYSisthesystemclock,whilefHandfSUBareotherinternalclocks,thedetailsofwhichcanbefoundintheoscillatorsection.

Bit3 STnON:STMnCounterOn/Offcontrol0:Off1:On

Thisbitcontrolstheoverallon/offfunctionoftheSTMn.SettingthebithighenablesthecountertorunwhileclearingthebitdisablestheSTMn.ClearingthisbittozerowillstopthecounterfromcountingandturnofftheSTMnwhichwillreduceitspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillbereset tozero,howeverwhenthebitchangesfromhighto low, the internalcounterwillretainitsresidualvalueuntilthebitreturnshighagain.IftheSTMnisintheCompareMatchOutputModethentheSTMnoutputpinwillberesettoitsinitialcondition,asspecifiedbytheSTnOCbit,whentheSTnONbitchangesfromlowtohigh.

Bit2~0 STnRP2~STnRP0:STMnCCRP3-bitregister,comparedwiththeSTMnCounterbit9~bit7ComparatorPMatchPeriod000:1024STMnclocks001:128STMnclocks010:256STMnclocks011:384STMnclocks100:512STMnclocks101:640STMnclocks110:768STMnclocks111:896STMnclocks

ThesethreebitsareusedtosetupthevalueontheinternalCCRP3-bitregister,whichare thencomparedwith the internalcounter'shighest threebits.Theresultof thiscomparisoncanbeselectedtocleartheinternalcounteriftheSTnCCLRbitissettozero.SettingtheSTnCCLRbittozeroensuresthatacomparematchwiththeCCRPvalueswillreset theinternalcounter.AstheCCRPbitsareonlycomparedwiththe

Rev. 1.00 64 st 1 01 Rev. 1.00 6 st 1 01



highest threecounterbits, thecomparevaluesexist in128clockcyclemultiples.Clearingall threebits tozero is ineffectallowing thecounter tooverflowat itsmaximumvalue.

STMnC0 Register (n=1)

Bit 7 6 5 4 3 2 1 0Name STnPU STnCK STnCK1 STnCK0 STnON — — —R/W R/W R/W R/W R/W R/W — — —POR 0 0 0 0 0 — — —

Bit7 STnPAU:STMnCounterPausecontrol0:Run1:Pause

Thecountercanbepausedbysettingthisbithigh.Clearingthebit tozerorestoresnormalcounteroperation.WheninaPauseconditiontheSTMnwillremainpoweredupandcontinuetoconsumepower.Thecounterwillretainitsresidualvaluewhenthisbitchangesfromlowtohighandresumecountingfromthisvaluewhenthebitchangestoalowvalueagain.

Bit6~4 STnCK2~STnCK0:SelectSTMnCounterclock000:fSYS/4001:fSYS

010:fH/16011:fH/64100:fSUB

101:fSUB

110:STCKnrisingedgeclock111:STCKnfallingedgeclock

Thesethreebitsareusedtoselect theclocksourcefor theSTMn.Theexternalpinclocksourcecanbechosentobeactiveontherisingorfallingedge.TheclocksourcefSYSisthesystemclock,whilefHandfSUBareotherinternalclocks,thedetailsofwhichcanbefoundintheoscillatorsection.

Bit3 STnON:STMnCounterOn/Offcontrol0:Off1:On

Thisbitcontrolstheoverallon/offfunctionoftheSTMn.SettingthebithighenablesthecountertorunwhileclearingthebitdisablestheSTMn.ClearingthisbittozerowillstopthecounterfromcountingandturnofftheSTMnwhichwillreduceitspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillbereset tozero,howeverwhenthebitchangesfromhighto low, the internalcounterwillretainitsresidualvalueuntilthebitreturnshighagain.IftheSTMnisintheCompareMatchOutputModethentheSTMnoutputpinwillberesettoitsinitialcondition,asspecifiedbytheSTnOCbit,whentheSTnONbitchangesfromlowtohigh.


Rev. 1.00 66 st 1 01 Rev. 1.00 6 st 1 01



STMnC1 Register (n=0~1)

Bit 7 6 5 4 3 2 1 0Name STnM1 STnM0 STnIO1 STnIO0 STnOC STnPOL STnDPX STnCCLRR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 STnM1~STnM0:SelectSTMnOperatingMode00:CompareMatchOutputMode01:CaptureInputMode10:PWMOutputModeorSinglePulseOutputMode11:Timer/CounterMode

Thesebits setup the requiredoperatingmode for theSTMn.Toensure reliableoperation theSTMnshouldbeswitchedoffbeforeanychangesaremade to theSTnM1andSTnM0bits.IntheTimer/CounterMode, theSTMnoutputpincontrolwillbedisabled.

Bit5~4 STnIO1~STnIO0:SelectSTMnexternalpinSTPnfunctionCompareMatchOutputMode00:Nochange01:Outputlow10:Outputhigh11:Toggleoutput

PWMOutputMode/SinglePulseOutputMode00:PWMoutputinactivestate01:PWMoutputactivestate10:PWMoutput11:SinglePulseOutput

CaptureInputMode00:InputcaptureatrisingedgeofSTPnI01:InputcaptureatfallingedgeofSTPnI10:Inputcaptureatrising/fallingedgeofSTPnI11:Inputcapturedisabled

Timer/CounterModeUnused

ThesetwobitsareusedtodeterminehowtheSTMnoutputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodetheSTMnisrunning.IntheCompareMatchOutputMode,theSTnIO1andSTnIO0bitsdeterminehowtheSTMnoutputpinchangesstatewhenacomparematchoccursfromtheComparatorA.TheTMoutputpincanbesetuptoswitchhigh,switchlowortotoggleitspresentstatewhenacomparematchoccursfromtheComparatorA.Whenthebitsarebothzero, thennochangewill takeplaceon theoutput.The initialvalueof theSTMnoutputpinshouldbesetupusingtheSTnOCbit in theSTMnC1register.Note thattheoutputlevelrequestedbytheSTnIO1andSTnIO0bitsmustbedifferentfromtheinitialvaluesetupusingtheSTnOCbitotherwisenochangewilloccurontheSTMnoutputpinwhenacomparematchoccurs.AftertheSTMnoutputpinchangesstate,itcanberesettoitsinitiallevelbychangingtheleveloftheSTnONbitfromlowtohigh.InthePWMOutputMode, theSTnIO1andSTnIO0bitsdeterminehowtheSTMnoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWMoutputfunctionismodifiedbychangingthesetwobits.ItisnecessarytoonlychangethevaluesoftheSTnIO1andSTnIO0bitsonlyaftertheSTMnhasbeenswitchedoff.UnpredictablePWMoutputswilloccurif theSTnIO1andSTnIO0bitsarechangedwhentheSTMnisrunning.

Rev. 1.00 66 st 1 01 Rev. 1.00 6 st 1 01



Bit3 STnOC:STMnSTPnOutputcontrolCompareMatchOutputMode0:Initiallow1:Initialhigh

PWMOutputMode/SinglePulseOutputMode0:Activelow1:Activehigh

This is theoutputcontrolbit for theSTMnoutputpin.ItsoperationdependsuponwhetherSTMisbeingused in theCompareMatchOutputModeor in thePWMOutputMode/SinglePulseOutputMode.IthasnoeffectiftheSTMisintheTimer/CounterMode. In theCompareMatchOutputMode itdetermines the logic leveloftheSTMoutputpinbeforeacomparematchoccurs.InthePWMoutputModeitdeterminesifthePWMsignalisactivehighoractivelow.IntheSinglePulseOutputMode itdetermines the logic levelof theSTMnoutputpinwhen theSTnONbitchangesfromlowtohigh.

Bit2 STnPOL:STMnSTPnOutputpolaritycontrol0:Non-inverted1:Inverted

Thisbitcontrols thepolarityof theSTPnoutputpin.Whenthebit issethigh theSTMnoutputpinwillbeinvertedandnotinvertedwhenthebitiszero.IthasnoeffectiftheSTMnisintheTimer/CounterMode.

Bit1 STnDPX:STMnPWMduty/periodcontrol0:CCRP–period;CCRA–duty1:CCRP–duty;CCRA–period

ThisbitdetermineswhichoftheCCRAandCCRPregistersareusedforperiodanddutycontrolofthePWMwaveform.

Bit0 STnCCLR:STMnCounterClearconditionselection0:ComparatorPmatch1:ComparatorAmatch

Thisbit isused toselect themethodwhichclears thecounter.Remember that theStandardTypeTMcontainstwocomparators,ComparatorAandComparatorP,eitherofwhichcanbeselectedtocleartheinternalcounter.WiththeSTnCCLRbitsethigh,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorA.Whenthebitislow,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorPorwithacounteroverflow.AcounteroverflowclearingmethodcanonlybeimplementediftheCCRPbitsareallclearedtozero.TheSTnCCLRbitisnotusedinthePWMOutput,SinglePulseOutputorCaptureInputMode.

Rev. 1.00 68 st 1 01 Rev. 1.00 69 st 1 01



Standard Type TM Operation ModesTheStandardTypeTMcanoperateinoneoffiveoperatingmodes,CompareMatchOutputMode,PWMOutputMode,SinglePulseOutputMode,CaptureInputModeorTimer/CounterMode.TheoperatingmodeisselectedusingtheSTnM1andSTnM0bitsintheSTMnC1register.

Compare Match Output ModeTo select thismode, bitsSTnM1andSTnM0 in theSTMnC1 register, shouldbe set to00respectively. In thismodeonce thecounter isenabledand running itcanbeclearedby threemethods.Theseareacounteroverflow,acomparematchfromComparatorAandacomparematchfromComparatorP.WhentheSTnCCLRbitislow,therearetwowaysinwhichthecountercanbecleared.OneiswhenacomparematchfromComparatorP,theotheriswhentheCCRPbitsareallzerowhichallowsthecountertooverflow.HerebothSTMnAFandSTMnPFinterruptrequestflagsforComparatorAandComparatorPrespectively,willbothbegenerated.

IftheSTnCCLRbitintheSTMnC1registerishighthenthecounterwillbeclearedwhenacomparematchoccursfromComparatorA.However,hereonly theSTMnAFinterrupt request flagwillbegeneratedevenifthevalueoftheCCRPbitsislessthanthatoftheCCRAregisters.ThereforewhenSTnCCLRishighnoSTMnPFinterruptrequestflagwillbegenerated.IntheCompareMatchOutputMode,theCCRAcannotbesetto“0”.

Asthenameofthemodesuggests,afteracomparisonismade,theSTMnoutputpin,willchangestate.TheSTMnoutputpinconditionhoweveronlychangesstatewhenaSTMnAFinterruptrequestflagisgeneratedafteracomparematchoccursfromComparatorA.TheSTMnPFinterruptrequestflag,generatedfromacomparematchoccursfromComparatorP,willhavenoeffectontheSTMnoutputpin.ThewayinwhichtheSTMnoutputpinchangesstatearedeterminedbytheconditionoftheSTnIO1andSTnIO0bitsintheSTMnC1register.TheSTMnoutputpincanbeselectedusingtheSTnIO1andSTnIO0bitstogohigh,togolowortotogglefromitspresentconditionwhenacomparematchoccursfromComparatorA.TheinitialconditionoftheSTMnoutputpin,whichissetupaftertheSTnONbitchangesfromlowtohigh,issetupusingtheSTnOCbit.NotethatiftheSTnIO1andSTnIO0bitsarezerothennopinchangewilltakeplace.

Rev. 1.00 68 st 1 01 Rev. 1.00 69 st 1 01



Conter Vale

0x3FF/0xFFFF

CCRP

CCR

STnON

STnPU

STnPOL

CCRP Int. fla STMnPF

CCR Int. fla STMnF

STMnO/P Pin

Time

CCRP=0

CCRP > 0

Conter overflowCCRP > 0

Conter cleared by CCRP vale

Pase

Resme

Stop

Conter Restart

STnCCLR = 0; STnM [1:0] = 00

Otpt pin set to initial Level Low if STnOC=0

Otpt Tole with STMnF fla

Note STnIO [1:0] = 10 ctive Hih Otpt selectHere STnIO [1:0] = 11

Tole Otpt select

Otpt not affected by STMnF fla. Remains Hih ntil reset by STnON bit

Otpt PinReset to Initial vale

Otpt controlled by other pin-shared fnction

Otpt Invertswhen STnPOL is hih

Compare Match Output Mode – STnCCLR = 0Note:1.WithSTnCCLR=0aComparatorPmatchwillclearthecounter

2.TheSTMnoutputpiniscontrolledonlybytheSTMnAFflag3.TheoutputpinisresettoitsinitialstatebyaSTnONbitrisingedge4.n=0for10-bitSTMwhilen=1for16-bitSTM

Rev. 1.00 0 st 1 01 Rev. 1.00 1 st 1 01



Conter Vale

0x3FF/0xFFFF

CCRP

CCR

STnON

STnPU

STnPOL


CCR Int. fla STMnF

STMn O/P Pin

Time

CCR=0

CCR = 0Conter overflowCCR > 0 Conter cleared by CCR vale

Pase

Resme

Stop Conter Restart

STnCCLR = 1; STnM [1:0] = 00

Otpt pin set to initial Level Low if STnOC=0

Otpt Tole with STMnF fla

Note STnIO [1:0] = 10 ctive Hih Otpt selectHere STnIO [1:0] = 11

Tole Otpt select

Otpt not affected by STMnF fla. Remains Hih ntil reset by STnON bit

Otpt PinReset to Initial vale

Otpt controlled by other pin-shared fnction

Otpt Invertswhen STnPOL is hih

STMnPF not enerated

No STMnF fla enerated on CCR overflow

Otpt does not chane

Compare Match Output Mode – STnCCLR = 1Note:1.WithSTnCCLR=1aComparatorAmatchwillclearthecounter

2.TheSTMnoutputpiniscontrolledonlybytheSTMnAFflag3.TheoutputpinisresettoitsinitialstatebyaSTnONbitrisingedge4.ASTMnPFflagisnotgeneratedwhenSTnCCLR=15.n=0for10-bitSTMwhilen=1for16-bitSTM

Rev. 1.00 0 st 1 01 Rev. 1.00 1 st 1 01



Timer/Counter ModeTo select thismode, bitsSTnM1andSTnM0 in theSTMnC1 register shouldbe set to 11respectively.TheTimer/CounterModeoperatesinanidenticalwaytotheCompareMatchOutputModegenerating thesameinterruptflags.Theexception is that in theTimer/CounterModetheSTMnoutputpinisnotused.ThereforetheabovedescriptionandTimingDiagramsfortheCompareMatchOutputModecanbeusedtounderstanditsfunction.AstheSTMnoutputpinisnotusedinthismode,thepincanbeusedasanormalI/Opinorotherpin-sharedfunction.

PWM Output ModeToselectthismode,bitsSTnM1andSTnM0intheSTMnC1registershouldbesetto10respectivelyandalsotheSTnIO1andSTnIO0bitsshouldbesetto10respectively.ThePWMfunctionwithintheSTMnisusefulforapplicationswhichrequirefunctionssuchasmotorcontrol,heatingcontrol,illuminationcontroletc.ByprovidingasignaloffixedfrequencybutofvaryingdutycycleontheSTMnoutputpin,asquarewaveACwaveformcanbegeneratedwithvaryingequivalentDCRMSvalues.

AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgeneratedwaveformisextremelyflexible.InthePWMOutputMode,theSTnCCLRbithasnoeffectasthePWMperiod.BothoftheCCRAandCCRPregistersareusedtogeneratethePWMwaveform,oneregisterisusedtocleartheinternalcounterandthuscontrolthePWMwaveformfrequency,whiletheotheroneisusedtocontrol thedutycycle.Whichregister isusedtocontroleitherfrequencyordutycycleisdeterminedusingtheSTnDPXbit intheSTMnC1register.ThePWMwaveformfrequencyanddutycyclecanthereforebecontrolledbythevaluesintheCCRAandCCRPregisters.

Aninterruptflag,oneforeachoftheCCRAandCCRP,willbegeneratedwhenacomparematchoccursfromeitherComparatorAorComparatorP.TheSTnOCbitintheSTMnC1registerisusedtoselecttherequiredpolarityofthePWMwaveformwhilethetwoSTnIO1andSTnIO0bitsareusedtoenablethePWMoutputortoforcetheSTMnoutputpintoafixedhighorlowlevel.TheSTnPOLbitisusedtoreversethepolarityofthePWMoutputwaveform.

Rev. 1.00 st 1 01 Rev. 1.00 3 st 1 01



• 10-bit STM, PWM Output Mode, Edge-aligned Mode, STnDPX=0

CCRP 1~7 0Period CCRP × 18 104Dty CCR

IffSYS=4MHz,STMclocksourceisfSYS/4,CCRP=2andCCRA=128,

TheSTMPWMoutputfrequency=(fSYS/4)/(2×128)=fSYS/1024=4kHz,duty=128/(2×128)=50%.

IftheDutyvaluedefinedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthePWMoutputdutyis100%.


CCRP 1~7 0Period CCRDty CCRP×18 104

ThePWMoutputperiodisdeterminedbytheCCRAregistervaluetogetherwiththeSTMnclockwhilethePWMdutycycleisdefinedbytheCCRPregistervalueexceptwhentheCCRPvalueisequalto0.


CCRP 1~255 0Period CCRP × 6 636Dty CCR

IffSYS=4MHz,STMclocksourceisfSYS/4,CCRP=2andCCRA=128,

TheSTMPWMoutputfrequency=(fSYS/4)/(2×256)=fSYS/2048=2kHz,duty=128/(2×256)=25%.

IftheDutyvaluedefinedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthePWMoutputdutyis100%.


CCRP 1~255 0Period CCRDty CCRP×6 636

ThePWMoutputperiodisdeterminedbytheCCRAregistervaluetogetherwiththeSTMnclockwhilethePWMdutycycleisdefinedbytheCCRPregistervalueexceptwhentheCCRPvalueisequalto0.

Rev. 1.00 st 1 01 Rev. 1.00 3 st 1 01



Conter Vale

CCRP

CCR

STnON

STnPU

STnPOL


CCR Int. fla STMnF

STMn O/P Pin(STnOC=1)

Time

Conter cleared by CCRP

Pase Resme Conter Stop if STnON bit low

Conter Reset when STnON retrns hih

STnDPX = 0; STnM [1:0] = 10

PWM Dty Cycle set by CCR

PWM resmes operation

Otpt controlled by other pin-shared fnction Otpt Inverts

when STnPOL = 1PWM Period set by CCRP


PWM Output Mode – STnDPX = 0Note:1.HereSTnDPX=0–CounterclearedbyCCRP

2.AcounterclearsetsthePWMPeriod3.TheinternalPWMfunctioncontinuesrunningevenwhenSTnIO[1:0]=00or014.TheSTnCCLRbithasnoinfluenceonPWMoperation5.n=0for10-bitSTMwhilen=1for16-bitSTM

Rev. 1.00 4 st 1 01 Rev. 1.00 st 1 01



Conter Vale

CCRP

CCR

STnON

STnPU

STnPOL


CCR Int. fla STMnF

STMn O/P Pin (STnOC=1)

Time

Conter cleared by CCR

Pase Resme Conter Stop if STnON bit low

STnDPX = 1; STnM [1:0] = 10

PWM Dty Cycle set by CCRP

PWM resmes operation

Otpt controlled by other pin-shared fnction Otpt Inverts

when STnPOL = 1PWM Period set by CCR

STMn O/P Pin (STnOC=0)


PWM Output Mode – STnDPX = 1Note:1.HereSTnDPX=1–CounterclearedbyCCRA

2.AcounterclearsetsthePWMPeriod3.TheinternalPWMfunctioncontinuesevenwhenSTnIO[1:0]=00or014.TheSTnCCLRbithasnoinfluenceonPWMoperation5.n=0for10-bitSTMwhilen=1for16-bitSTM

Rev. 1.00 4 st 1 01 Rev. 1.00 st 1 01



Single Pulse Output ModeTo select thismode, bitsSTnM1andSTnM0 in theSTMnC1 register shouldbe set to 10respectivelyandalsotheSTnIO1andSTnIO0bitsshouldbesetto11respectively.TheSinglePulseOutputMode,asthenamesuggests,willgenerateasingleshotpulseontheSTMnoutputpin.

ThetriggerforthepulseoutputleadingedgeisalowtohightransitionoftheSTnONbit,whichcanbeimplementedusingtheapplicationprogram.HoweverintheSinglePulseOutputMode,theSTnONbitcanalsobemadetoautomaticallychangefromlowtohighusingtheexternalSTCKnpin,whichwill inturninitiatetheSinglePulseoutput.WhentheSTnONbittransitionstoahighlevel, thecounterwillstartrunningandthepulseleadingedgewillbegenerated.TheSTnONbitshouldremainhighwhenthepulseisinitsactivestate.ThegeneratedpulsetrailingedgewillbegeneratedwhentheSTnONbitisclearedtozero,whichcanbeimplementedusingtheapplicationprogramorwhenacomparematchoccursfromComparatorA.

HoweveracomparematchfromComparatorAwillalsoautomaticallycleartheSTnONbitandthusgeneratetheSinglePulseoutputtrailingedge.InthiswaytheCCRAvaluecanbeusedtocontrolthepulsewidth.AcomparematchfromComparatorAwillalsogenerateaSTMninterrupt.ThecountercanonlyberesetbacktozerowhentheSTnONbitchangesfromlowtohighwhenthecounterrestarts.IntheSinglePulseOutputModeCCRPisnotused.TheSTnCCLRandSTnDPXbitsarenotusedinthisMode.

STnON bit0 → 1

S/W Command SET“STnON”

orSTCKn Pin

Transition

STnON bit1 → 0

CCR Trailin Ede

S/W Command CLR“STnON”

orCCR Compare Match

STPn Otpt Pin

Plse Width = CCR Vale

CCR Leadin Ede

Single Pulse Generation

Rev. 1.00 6 st 1 01 Rev. 1.00 st 1 01



Conter Vale

CCRP

CCR

STnON

STnPU

STnPOL

CCRP Int. Fla STMnPF

CCR Int. Fla STMnF


Time

Conter stopped by CCR

PaseResme Conter Stops by

software


STnM [1:0] = 10 ; STnIO [1:0] = 11

Plse Width set by CCR

Otpt Invertswhen STnPOL = 1

No CCRP Interrpts enerated


STCKn pin

Software Trier

Cleared by CCR match

STCKn pin Trier

to. set by STCKn pin

Software Trier

Software Clear

Software TrierSoftware

Trier

Single Pulse Output ModeNote:1.CounterstoppedbyCCRA

2.CCRPisnotused3.ThepulsetriggeredbytheSTnCKpinorbysettingtheSTnONbithigh4.ASTCKnpinactiveedgewillautomaticallysettheSTnONbithigh.5.IntheSinglePulseOutputMode,STnIO[1:0]mustbesetto“11”andcannotbechanged.6.n=0for10-bitSTMwhilen=1for16-bitSTM

Rev. 1.00 6 st 1 01 Rev. 1.00 st 1 01



Capture Input ModeToselectthismodebitsSTnM1andSTnM0intheSTMnC1registershouldbesetto01respectively.Thismodeenablesexternalsignals tocaptureandstore thepresentvalueof theinternalcounterandcanthereforebeusedforapplicationssuchaspulsewidthmeasurements.TheexternalsignalissuppliedontheSTPnIpin,whoseactiveedgecanbearisingedge,afallingedgeorbothrisingandfallingedges;theactiveedgetransitiontypeisselectedusingtheSTnIO1andSTnIO0bitsintheSTMnC1register.ThecounterisstartedwhentheSTnONbitchangesfromlowtohighwhichisinitiatedusingtheapplicationprogram.

WhentherequirededgetransitionappearsontheSTPnIpinthepresentvalueinthecounterwillbelatchedintotheCCRAregistersandaSTMninterruptgenerated.IrrespectiveofwhateventsoccurontheSTPnIpinthecounterwillcontinuetofreerununtil theSTnONbitchangesfromhightolow.WhenaCCRPcomparematchoccursthecounterwillresetbacktozero;inthiswaytheCCRPvaluecanbeusedtocontrolthemaximumcountervalue.WhenaCCRPcomparematchoccursfromComparatorP,aSTMninterruptwillalsobegenerated.CountingthenumberofoverflowinterruptsignalsfromtheCCRPcanbeausefulmethodinmeasuringlongpulsewidths.TheSTnIO1andSTnIO0bitscanselecttheactivetriggeredgeontheSTPnIpintobearisingedge,fallingedgeorbothedgetypes.IftheSTnIO1andSTnIO0bitsarebothsethigh,thennocaptureoperationwilltakeplaceirrespectiveofwhathappensontheSTPnIpin,howeveritmustbenotedthatthecounterwillcontinuetorun.TheSTnCCLRandSTnDPXbitsarenotusedinthisMode.

Rev. 1.00 8 st 1 01 Rev. 1.00 9 st 1 01



Conter Vale

YY

CCRP

STnON

STnPU

CCRP Int. Fla STMnPF

CCR Int. Fla STMnF

CCR Vale

Time

Conter cleared by CCRP

PaseResme

Conter Reset

STnM [1:0] = 01

STMn captre pin STPnI

XX

Conter Stop

STnIO [1:0] Vale

XX YY XX YY

ctive ede ctive

edective ede

00 – Risin ede 01 – Fallin ede 10 – Both edes 11 – Disable Captre

Capture Input ModeNote:1.STnM[1:0]=01andactiveedgesetbytheSTnIO[1:0]bits

2.ASTMnCaptureinputpinactiveedgetransfersthecountervaluetoCCRA3.STnCCLRbitnotused4.Nooutputfunction–STnOCandSTnPOLbitsarenotused5.CCRPdeterminesthecountervalueandthecounterhasamaximumcountvaluewhenCCRPisequaltozero.

6.n=0for10-bitSTMwhilen=1for16-bitSTM

Rev. 1.00 8 st 1 01 Rev. 1.00 9 st 1 01



Analog to Digital ConverterTheneedtointerfacetorealworldanalogsignals isacommonrequirementformanyelectronicsystems.However, toproperlyprocess these signalsbyamicrocontroller, theymust firstbeconverted intodigitalsignalsbyA/Dconverters.By integrating theA/Dconversionelectroniccircuitryintothemicrocontroller,theneedforexternalcomponentsisreducedsignificantlywiththecorrespondingfollow-onbenefitsoflowercostsandreducedcomponentspacerequirements.

A/D OverviewThedevicecontainsamulti-channelanalog todigitalconverterwhichcandirectly interface toexternalanalogsignals,suchasthatfromsensorsorothercontrolsignalsandconvertthesesignalsdirectly intoa12-bitdigitalvalue. Italsocanconvert the internalsignals, suchas the internalreferencevoltage,intoa12-bitdigitalvalue.TheexternalorinternalanalogsignaltobeconvertedisdeterminedbytheSAINSandSACSbitfields.MoredetailedinformationabouttheA/Dinputsignalselectionwillbedescribedinthe“A/DConverterInputSignals”section.

TheaccompanyingblockdiagramshowstheoverallinternalstructureoftheA/Dconverter,togetherwithitsassociatedregistersandcontrolbits.

External Input Channels Internal Input Signal A/D Signal Select

N0~N VBGSINS~SINS0SCS3~SCS0

Pin-shared Control bits SCS3~SCS0

/D Converter

STRT DBZ DCEN

VSS/D Clock

÷ N

(N=0~)

fSYS

SCKS~SCKS0

VDD

DCEN

SDOL

SDOH

N0N1

/D DataReisters

N

SINS~SINS0

VBG

/D Reference Voltae

VDD

SVRS1~SVRS0VREF Pin-shared

Selection

DRFS

A/D Converter Structure

Rev. 1.00 80 st 1 01 Rev. 1.00 81 st 1 01



Registers DescriptionsOveralloperationoftheA/Dconverteriscontrolledusingfourregisters.Areadonlyregisterpairexists tostore theA/DConverterdata12-bitvalue.Tworegisters,SADC0andSADC1,are thecontrolregisterswhichsetuptheoperatingconditionsandcontrolfunctionoftheA/Dconverter.

Register NameBit

7 6 5 4 3 2 1 0SDOL (DRFS=0) D3 D D1 D0 — — — —SDOL (DRFS=1) D D6 D D4 D3 D D1 D0SDOH (DRFS=0) D11 D10 D9 D8 D D6 D D4SDOH (DRFS=1) — — — — D11 D10 D9 D8SDC0 STRT DBZ DCEN DRFS SCS3 SCS SCS1 SCS0SDC1 SINS SINS1 SINS0 SVRS1 SVRS0 SCKS SCKS1 SCKS0

A/D Converter Registers List

A/D Converter Data Registers – SADOL, SADOHAsthedevicecontainsaninternal12-bitA/Dconverter, itrequirestwodataregisterstostoretheconvertedvalue.Theseareahighbyteregister,knownasSADOH,andalowbyteregister,knownasSADOL.After theconversionprocess takesplace, theseregisterscanbedirectlyreadbythemicrocontrollertoobtainthedigitisedconversionvalue.Asonly12bitsofthe16-bitregisterspaceisutilised, theformat inwhichthedata isstorediscontrolledbytheADRFSbit in theSADC0registerasshownin theaccompanying table.D0~D11are theA/Dconversionresultdatabits.Anyunusedbitswillbereadaszero.TheA/DdataregisterscontentswillbeunchangediftheA/Dconverterisdisabled.

ADRFSSADOH SADOL

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 00 D11 D10 D9 D8 D D6 D D4 D3 D D1 D0 0 0 0 01 0 0 0 0 D11 D10 D9 D8 D D6 D D4 D3 D D1 D0

A/D Converter Data Registers

A/D Converter Control Registers – SADC0, SADC1TocontrolthefunctionandoperationoftheA/Dconverter,twocontrolregistersknownasSADC0andSADC1areprovided.These8-bit registersdefinefunctionssuchas theselectionofwhichanalogsignal isconnectedtotheinternalA/Dconverter, thedigitiseddataformat, theA/DclocksourceaswellascontrollingthestartfunctionandmonitoringtheA/Dconverterbusystatus.Asthedevicecontainsonlyoneactualanalogtodigitalconverterhardwarecircuit,eachof theexternalandinternalanalogsignalsmustberoutedtotheconverter.TheSAINSfieldintheSADC1registerandSACSfieldintheSADC0registerareusedtodeterminewhichanalogsignalderivedfromtheexternalorinternalsignalswillbeconnectedtotheA/Dconverter.

Therelevantpin-sharedfunctionselectionbitsdeterminewhichpinsonI/OPortsareusedasanaloginputsfortheA/Dconverterinputandwhichpinsarenot.WhenthepinisselectedtobeanA/Dinput, itsoriginalfunctionwhether it isanI/Oorotherpin-sharedfunctionwillberemoved.Inaddition,anyinternalpull-highresistorconnectedtothepinwillbeautomaticallyremovedifthepinisselectedtobeanA/Dconverterinput.

Rev. 1.00 80 st 1 01 Rev. 1.00 81 st 1 01



• SADC0 Register

Bit 7 6 5 4 3 2 1 0Name STRT DBZ DCEN DRFS SCS3 SCS SCS1 SCS0R/W R/W R R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 START:StarttheA/DConversion0→1→0:Start

ThisbitisusedtoinitiateanA/Dconversionprocess.Thebitisnormallylowbutifsethighandthenclearedlowagain,theA/Dconverterwillinitiateaconversionprocess.

Bit6 ADBZ:A/DConverterbusyflag0:NoA/Dconversionisinprogress1:A/Dconversionisinprogress

ThisreadonlyflagisusedtoindicatewhethertheA/Dconversionis inprogressornot.WhentheSTARTbitissetfromlowtohighandthentolowagain,theADBZflagwillbesetto1toindicatethattheA/Dconversionisinitiated.TheADBZflagwillbeclearedto0aftertheA/Dconversioniscomplete.

Bit5 ADCEN:A/DConverterfunctionenablecontrol0:Disable1:Enable

Thisbitcontrols theA/Dinternal function.Thisbitshouldbeset toone toenabletheA/Dconverter.If thebit isset low,thentheA/Dconverterwillbeswitchedoffreducingthedevicepowerconsumption.WhentheA/Dconverterfunctionisdisabled,thecontentsof theA/Ddata registerpairknownasSADOHandSADOLwillbeunchanged.

Bit4 ADRFS:A/Dconversiondataformatselect0:A/Dconverterdataformat→SADOH=D[11:4];SADOL=D[3:0]1:A/Dconverterdataformat→SADOH=D[11:8];SADOL=D[7:0]

Thisbitcontrols theformatof the12-bitconvertedA/Dvaluein thetwoA/Ddataregisters.DetailsareprovidedintheA/Dconverterdataregistersection.

Bit3~0 SACS3~SACS0:A/Dconverterexternalanaloginputchannelselect0000:ExternalAN0input0001:ExternalAN1input0010:ExternalAN2input0011:ExternalAN3input0100:ExternalAN4input0101:ExternalAN5input0110:ExternalAN6input0111:ExternalAN7input1xxx:Non-existedchannel,theinputwillbefloatingifselected.

Thesebitsareusedtoselectwhichexternalanaloginputchannelistobeconverted.Whentheexternalanaloginputchannel isselected, theSAINSbitfieldmustset to“000”,“101”or“11x”.Detailsaresummarizedinthe“A/DConverterInputSignalSelection”table.

Rev. 1.00 8 st 1 01 Rev. 1.00 83 st 1 01



• SADC1 Register

Bit 7 6 5 4 3 2 1 0Name SINS SINS1 SINS0 SVRS1 SVRS0 SCKS SCKS1 SCKS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~5 SAINS2~SAINS0:A/Dconverterinputsignalselect000:Externalsource–Externalanalogchannelintput,ANn001:Internalsource–InternalsignalderivedfromVBG

010:Internalsource–Unused,connectedtoground011:Internalsource–Unused,connectedtoground100:Internalsource–Unused,connectedtoground101:Externalsource–Externalanalogchannelintput,ANn11x:Externalsource–Externalanalogchannelintput,ANn

Caremustbetakenif theSAINS2~SAINS0bitsareset to“001”,“01x”and“100”toselecttheinternalanalogsignaltobecoverted.Whentheinternalanalogsignalisselectedtobeconverted,theexternalinputpinmustneverbeselectedastheA/DinputsignalbyproperlysettingtheSACS3~SACS0bitswithavaluefrom“1000”to“1111”.Otherwise, theexternalchannel inputwillbeconnected togetherwith the internalanalogsignal.Thiswill result inunpredictablesituationssuchasan irreversibledamage.

Bit4~3 SAVRS2~SAVRS0:A/Dconverterreferencevoltageselect00:ExternalVREFpin01:InternalA/Dconverterpower,AVDD

1x:ExternalVREFpinThesebitsareusedtoselecttheA/Dconverterreferencevoltage.CaremustbetakeniftheSAVRS1~SAVRS0bitsaresetto“01”toselecttheinternalA/Dconverterpowerasthereferencevoltagesource.WhentheinternalA/Dconverterpowerisselectedasthereferencevoltage,theVREFpincannotbeconfiguredasthereferencevoltageinputbyproperlyconfiguringthecorrespondingpin-sharedfunctioncontrolbits.Otherwise,the external input voltageonVREFpinwill be connected to the internalA/Dconverterpower.Thiswillresultinunpredictablesituations.

Bit2~0 SACKS2~SACKS0:A/Dconversionclocksourceselect000:fSYS

001:fSYS/2010:fSYS/4011:fSYS/8100:fSYS/16101:fSYS/32110:fSYS/64111:fSYS/128

ThesebitsareusedtoselecttheclocksourcefortheA/Dconverter.

A/D Converter Reference VoltageTheactualreferencevoltagesupplytotheA/DConvertercanbesuppliedfromthepositivepowersupplypin,AVDD,oranexternal referencesourcesuppliedonpinVREFdeterminedby theSAVRS1~SAVRS0bitsintheSADC1register.AstheVREFpinispin-sharedwithotherfunctions,whentheVREFpinisselectedasthereferencevoltagepin,theVREFpin-sharedfunctionselectionbits should firstbeproperlyconfigured todisableotherpin-shared functions.However, if theinternalreferencesignalisselectedasthereferencesource,theVREFpinmustnotbeconfiguredasthereferencevoltageinputtoavoidtheinternalconnectionbetweentheVREFpintoA/DconverterpowerAVDD.TheanaloginputvaluesmustnotbeallowedtoexceedthevalueoftheselectedA/Dreferencevoltage.

Rev. 1.00 8 st 1 01 Rev. 1.00 83 st 1 01



A/D Converter Input SignalsAlloftheexternalA/Danaloginputpinsarepin-sharedwiththeI/Opinsaswellasotherfunctions.Thecorrespondingpin-sharedfunctionselectionbits in thePxS1andPxS0registers,determinewhethertheexternalinputpinsaresetupasA/Dconverteranalogchannelinputsorwhethertheyhaveotherfunctions.IfthecorrespondingpinissetuptobeanA/Dconverteranalogchannelinput,theoriginalpinfunctionwillbedisabled.Inthisway,pinscanbechangedunderprogramcontroltochangetheirfunctionbetweenA/Dinputsandotherfunctions.Allpull-highresistors,whicharesetupthroughregisterprogramming,willbeautomaticallydisconnectedifthepinsaresetupasA/Dinputs.NotethatitisnotnecessarytofirstsetuptheA/DpinasaninputintheportcontrolregistertoenabletheA/DinputaswhentherelevantA/DinputfunctionselectionbitsenableanA/Dinput,thestatusoftheportcontrolregisterwillbeoverridden.

As thedevicecontainsonlyoneactualanalogtodigitalconverterhardwarecircuit,eachof theexternalandinternalanalogsignalsmustberoutedtotheconverter.TheSAINS2~SAINS0bitsintheSADC1registerareusedtodeterminethat theanalogsignal tobeconvertedcomesfromtheexternalchannelinputorinternalanalogsignal.TheSACS3~SACS0bitsintheSADC0registerareusedtodeterminewhichexternalchannelinputisselectedtobeconverted.IftheSAINS2~SAINS0bitsaresetto“000”or“101~111”,theexternalchannelinputwillbeselectedtobeconvertedandtheSACS3~SACS0bitscandeterminewhichexternalchannel isselected.If the internalanalogsignalisselectedtobeconverted,theSACS3~SACS0bitsmustbeconfiguredwithanappropriatevaluetoswitchofftheexternalanalogchannelinput.Otherwise,theinternalanalogsignalwillbeconnectedtogetherwiththeexternalchannelinput.Thiswillresultinunpredictablesituations.

SAINS[2:0] SACS[3:0] Input Signals Description

000 101~1110000~0111 N0~N External pin analo inpt1000~1111 — Un-existed channel, input is floating.

001 1000~1111 VBG Internal Bandap reference voltae010~100 1000~1111 GND Unsed connected to rond

A/D Converter Input Signal Selection

A/D OperationTheSTARTbitintheSADC0registerisusedtostarttheA/Dconversion.Whenthemicrocontrollersets thisbit fromlowtohighandthen lowagain,ananalog todigitalconversioncyclewillbeinitiated.

TheADBZbit intheSADC0registerisusedtoindicatewhethertheanalogtodigitalconversionprocessisinprogressornot.Thisbitwillbeautomaticallysetto1bythemicrocontrollerafteranA/Dconversionissuccessfullyinitiated.WhentheA/Dconversioniscomplete,theADBZbitwillbeclearedto0.Inaddition,thecorrespondingA/Dinterruptrequestflagwillbesetintheinterruptcontrolregister,andiftheinterruptsareenabled,aninternalinterruptsignalwillbegenerated.ThisA/Dinternal interruptsignalwilldirect theprogramflowtotheassociatedA/Dinternal interruptaddressforprocessing.If theA/Dinternal interrupt isdisabled, themicrocontrollercanpoll theADBZbitintheSADC0registertocheckwhetherithasbeenclearedasanalternativemethodofdetectingtheendofanA/Dconversioncycle.

TheclocksourcefortheA/Dconverter,whichoriginatesfromthesystemclockfSYS,canbechosentobeeither fSYSorasubdividedversionof fSYS.Thedivisionratiovalue isdeterminedby theSACKS2~SACKS0bits intheSADC1register.AlthoughtheA/DclocksourceisdeterminedbythesystemclockfSYSandbybitsSACKS2~SACKS0,therearesomelimitationsonthemaximumA/Dclocksourcespeedthatcanbeselected.AstherecommendedrangeofpermissibleA/Dclockperiod,tADCK,isfrom0.5μsto10μs,caremustbetakenforsystemclockfrequencies.Forexample,if

Rev. 1.00 84 st 1 01 Rev. 1.00 8 st 1 01



thesystemclockoperatesatafrequencyof4MHz,theSACKS2~SACKS0bitsshouldnotbesetto000,110or111.DoingsowillgiveA/DclockperiodsthatarelessthantheminimumorlargerthanthemaximumA/DclockperiodwhichmayresultininaccurateA/Dconversionvalues.Refertothefollowingtableforexamples,wherevaluesmarkedwithanasterisk*showwhere,dependinguponthedevice,specialcaremustbetaken,asthevaluesmaybelessthanorlargerthanthespecifiedA/DClockPeriod.

fSYS

A/D Clock Period (tADCK)SACKS

[2:0]=000(fSYS)

SACKS[2:0]=001

(fSYS/2)

SACKS[2:0]=010

(fSYS/4)

SACKS[2:0]=011

(fSYS/8)

SACKS[2:0]=100(fSYS/16)

SACKS[2:0]=101(fSYS/32)

SACKS[2:0]=110(fSYS/64)

SACKS[2:0]=111(fSYS/128)

1MHz 1μs 2μs 4μs 8μs 16μs * 32μs * 64μs * 128μs *MHz 00ns 1μs 2μs 4μs 8μs 16μs * 32μs * 64μs *4MHz 0ns * 00ns 1μs 2μs 4μs 8μs 16μs * 32μs *

A/D Clock Period Examples

Controlling thepoweron/off functionof theA/Dconvertercircuitry is implementedusing theADCENbitintheSADC0register.ThisbitmustbesethightopowerontheA/Dconverter.WhentheADCENbit issethigh topoweron theA/Dconverter internalcircuitryacertaindelay,asindicatedin the timingdiagram,mustbeallowedbeforeanA/Dconversionis initiated.EvenifnopinsareselectedforuseasA/Dinputs,iftheADCENbitishigh,thensomepowerwillstillbeconsumed.InpowerconsciousapplicationsitisthereforerecommendedthattheADCENissetlowtoreducepowerconsumptionwhentheA/Dconverterfunctionisnotbeingused.

Conversion Rate and Timing DiagramAcompleteA/Dconversioncontains twoparts,data samplinganddataconversion.ThedatasamplingwhichisdefinedastADStakes4A/Dclockcyclesandthedataconversiontakes12A/Dclockcycles.Thereforeatotalof16A/DclockcyclesforananalogsignalA/DconversionwhichisdefinedastADCarenecessary.

MaximumsingleA/Dconversionrate=A/Dclockperiod/16

Theaccompanyingdiagramshowsgraphicallythevariousstagesinvolvedinananalogtodigitalconversionprocessanditsassociatedtiming.AfteranA/Dconversionprocesshasbeeninitiatedby theapplicationprogram, themicrocontroller internalhardwarewillbegin tocarryout theconversion,duringwhichtimetheprogramcancontinuewithotherfunctions.ThetimetakenfortheA/Dconversionis16tADCKclockcycleswheretADCKisequaltotheA/Dclockperiod.

DCEN

STRT

DBZ

SCS[3:0]

off on off on

tONST

tDS

/D samplin timetDS

/D samplin time

Start of /D conversion Start of /D conversion Start of /D conversion

End of /D conversion

End of /D conversion

tDC/D conversion time



0011B 0010B 0000B 0001B

/D channel switch

(SINS[:0]=000)

A/D Conversion Timing

Summary of A/D Conversion Steps

Rev. 1.00 84 st 1 01 Rev. 1.00 8 st 1 01



ThefollowingsummarisestheindividualstepsthatshouldbeexecutedinordertoimplementanA/Dconversionprocess.

• Step1SelecttherequiredA/DconversionclockbycorrectlyprogrammingbitsSACKS2~SACKS0intheSADC1register.

• Step2EnabletheA/DconverterbysettingtheADCENbitintheSADC0registerto1.

• Step3SelectwhichsignalistobeconnectedtotheinternalA/DconverterbycorrectlyconfiguringtheSAINS2~SAINS0bitsSelecttheexternalchannelinputtobeconverted,gotoStep4.Selecttheinternalanalogsignaltobeconverted,gotoStep5.

• Step4IftheA/DinputsignalcomesfromtheexternalchannelinputselectedbyconfiguringtheSAINSbitfield,thecorrespondingpinsshouldbeconfiguredasA/Dinputfunctionbyconfiguringtherelevantpin-sharedfunctioncontrolbits.ThedesiredanalogchannelthenshouldbeselectedbyconfiguringtheSACSbitfield.Afterthisstep,gotoStep6.

• Step5BeforetheA/DinputsignalisselectedtocomefromtheinternalanalogsignalbyconfiguringtheSAINSbitfield,thecorrespondingexternalinputpinmustbeswitchedtoanon-existedchannelinputbyproperlyconfiguredtheSACS3~SACS0bits.ThedesiredinternalanalogsignalthencanbeselectedbyconfiguringtheSAINSbitfield.Afterthisstep,gotoStep6.

• Step6Select thereferencevoltagesourcebyconfiguring theSAVRS1~SAVRS0bits in theSADC1register.

• Step7SelectA/DconverteroutputdataformatbysettingtheADRFSbitintheSADC0register.

• Step8IfA/Dconversioninterruptisused,theinterruptcontrolregistersmustbecorrectlyconfiguredtoensuretheA/Dinterruptfunctionisactive.Themasterinterruptcontrolbit,EMI,andtheA/Dconversioninterruptcontrolbit,ADE,mustbothbesethighinadvance.

• Step9TheA/DconversionprocedurecannowbeinitializedbysettingtheSTARTbitfromlowtohighandthenlowagain.

• Step10IfA/Dconversion is inprogress, theADBZflagwillbesethigh.After theA/Dconversionprocess iscomplete, theADBZflagwillgo lowand then theoutputdatacanbe readfromSADOHandSADOLregisters.

Note:Whencheckingfortheendoftheconversionprocess,ifthemethodofpollingtheADBZbitintheSADC0registerisused,theinterruptenablestepabovecanbeomitted.

Rev. 1.00 86 st 1 01 Rev. 1.00 8 st 1 01



Programming ConsiderationsDuringmicrocontrolleroperationswhere theA/Dconverter isnotbeingused, theA/Dinternalcircuitrycanbeswitchedoff to reducepowerconsumption,bysettingbitADCENlow in theSADC0register.Whenthishappens, theinternalA/Dconvertercircuitswillnotconsumepowerirrespectiveofwhatanalogvoltageisappliedtotheirinputlines.IftheA/DconverterinputlinesareusedasnormalI/Os,thencaremustbetakenasiftheinputvoltageisnotatavalidlogiclevel,thenthismayleadtosomeincreaseinpowerconsumption.

A/D Transfer FunctionAsthedevicecontainsa12-bitA/Dconverter, itsfull-scaleconverteddigitisedvalueisequal toFFFH.Sincethefull-scaleanaloginputvalueisequaltotheactualA/Dconverterreferencevoltage,VREF,thisgivesasinglebitanaloginputvalueofreferencevoltagevaluedividedby4096.

1LSB=VREF÷4096

TheA/DConverterinputvoltagevaluecanbecalculatedusingthefollowingequation:

A/Dinputvoltage=A/Doutputdigitalvalue×VREF÷4096

Thediagramshowsthe ideal transferfunctionbetweentheanaloginputvalueandthedigitisedoutputvaluefor theA/Dconverter.Exceptfor thedigitisedzerovalue, thesubsequentdigitisedvalueswillchangeatapoint0.5LSBbelowwheretheywouldchangewithouttheoffset,andthelastfullscaledigitisedvaluewillchangeatapoint1.5LSBbelowtheVREFlevel.NotethatheretheVREFvoltageistheactualA/DconverterreferencevoltagedeterminedbytheSAVRSfield.

FFFH

FFEH

FFDH

03H

0H

01H

0 1 3 4093 4094 409 4096

VREF4096

Analog Input Voltage

A/D Conversion Result

1. LSB

0. LSB

Ideal A/D Transfer Function

Rev. 1.00 86 st 1 01 Rev. 1.00 8 st 1 01



A/D Programming ExamplesThefollowingtwoprogrammingexamplesillustratehowtosetupandimplementanA/Dconversion.Inthefirstexample, themethodofpollingtheADBZbit intheSADC0registerisusedtodetectwhentheconversioncycleiscomplete,whereasinthesecondexample,theA/Dinterruptisusedtodeterminewhentheconversioniscomplete.

Example: using an ADBZ polling method to detect the end of conversionclr ADE ; disable ADC interruptmov a,03Hmov SADC1,a ; select fSYS/8 as A/D clock set ADCENmov a,02h ;setupPBS0registertoconfigurepinAN0mov PBS0,amov a,20hmov SADC0,a ;enableandconnectAN0channeltoA/Dconverter:start_conversion:clr START ;highpulseonstartbittoinitiateconversionset START ;resetA/Dclr START ;startA/Dpolling_EOC:sz ADBZ ;polltheSADC0registerADBZbittodetectendofA/Dconversionjmp polling_EOC ;continuepollingmov a,SADOL ; read low byte conversion result valuemov SADOL_buffer,a ;saveresulttouserdefinedregistermov a,SADOH ; read high byte conversion result valuemov SADOH_buffer,a ;saveresulttouserdefinedregister::jmp start_conversion

Rev. 1.00 88 st 1 01 Rev. 1.00 89 st 1 01



Example: using the interrupt method to detect the end of conversionclr ADE ; disable ADC interruptmov a,03Hmov SADC1,a ; select fSYS/8 as A/D clock set ADCENmov a,02h ;setupPBS0registertoconfigurepinAN0mov PBS0,amov a,20hmov SADC0,a ;enableandconnectAN0channeltoA/DconverterStart_conversion:clr START ;highpulseonSTARTbittoinitiateconversionset START ;resetA/Dclr START ;startA/Dclr ADF ;clearADCinterruptrequestflagset ADE ; enable ADC interruptset EMI ;enableglobalinterrupt:: ; ADC interrupt service routineADC_ISR:mov acc_stack,a ;saveACCtouserdefinedmemorymov a,STATUSmov status_stack,a ;saveSTATUStouserdefinedmemory: :mov a,SADOL ; read low byte conversion result valuemov SADOL_buffer,a ;saveresulttouserdefinedregistermov a,SADOH ; read high byte conversion result valuemov SADOH_buffer,a ;saveresulttouserdefinedregister::EXIT_INT_ISR:mov a,status_stackmov STATUS,a ;restoreSTATUSfromuserdefinedmemorymov a,acc_stack ;restoreACCfromuserdefinedmemoryreti

Rev. 1.00 88 st 1 01 Rev. 1.00 89 st 1 01



Power Line Data Transceiver Thepowerlinedatatransceiverprovidesawaytotransmitandreceivedataonthecommonpowerlinesofaninterconnectedarrayofmicrocontrollerbasedsubsystems.Byhavinganpowerlinedatatransceiverinsideeachsubsystem,thesharedpoweranddatacablingcanbereducedtoasimpletwolinetype,offeringmajorinstallationcostreductions.

LDO3.3V

LVD5.25V

CEB

VDD

VDD

VDD

VCC

CN

TRX

IS

VSS

TX

RX

RPU

CMP

OPA

1.5V

+

–

+

–

Current Modulator

EN1

VBG=1.5V

EN1B

R

EN1B

Zener

5.6V

EN1B

10MΩ

EN

EN

CMP & OPA Enable

ENB

VDD

Power Line Data Transceiver Block Diagram

Rev. 1.00 90 st 1 01 Rev. 1.00 91 st 1 01



MasterController

Positive Power Spply Line

Grond Line

Power Line Data Transceiver

MCU


MCU


MCU

Sbsystem#1

Sbsystem#

Sbsystem#n

Power Line Data Transceiver System Block Diagram

Shared Power LineAllmicrocontrollerbased subsystemsare connected togethervia the same two linepowerconnection.Theground line ishardwired toeachsubsystemwhile thepositivepower line isconnectedtotheVINpinonthePowerLineDataTransceiver.AninternalLowDropoutVoltageRegulatorwithinthePowerLineDataTransceiverconverts this inputpowersupplyvoltagetoafixedvoltagelevelwhichissuppliedtothesubsystemmicrocontrollerandothercircuitcomponents.Inthiswaywhenthepowerlinevoltageischangedduetothetransmissionorreceptionofdatathesubsystemcircuitsstillcontinuetoreceivearegulatedpowersupply.

Data Transmission (From master controller to slave device)Refer to theapplicationcircuitwhenreading the followingdescription.Themastercontrollertransmitsthedatabymodulatethepositivepowerline(L+)voltage.UsingthismethodshouldbepayattentiontothenoisetoleranceofthedeviceoperatingvoltageandtheTRXpinreceivingdata.AsthePowerLineDataTransceiverincludesavoltageregulatorwhichisusedasthepowersupplytothesubsystemunits,thenthesubsystempowersupplyvoltagewillnotbeaffectedaslongastheregulatorminimumdropoutvoltageismaintained.ThenavoltagemodulationsignalwillbedetectedintheTRXpintomaketheTRXpinvoltagedroplowerthanthethresholdvoltage(VT).HoweverareductioninthepowersupplywillbedetectedbytheCMPinternalcomparator.TheoutputofthiscomparatorisconnectedtoRXlinecanbeconnectedtoamicrocontrollerinputforuseasadatasignal.

Rev. 1.00 90 st 1 01 Rev. 1.00 91 st 1 01



VTRX

VT

VRX

VVDD

VMRK

Data Reception (From slave device to master controller)Refer to theapplicationcircuitwhenreading the followingdescription.Theslavedevicecantransmitdata to themastercontrollerbymodulating thecurrenton thepowersupply line.TheslavedevicepullstheTXlinevoltagetoalowleveltoenabletheinternalcurrentmodulator.ThemodulatorwillprovideaconstantcurrentloadbythetransistorconnectedtotheinternalmodulatorOPAoutputNMOSterminal.TheconstantcurrentloadissuppliedbythepowerlinethroughtheTRXpin,andcanbeadjustedbytheRS resistorconnectedontheISpin.Therefore, thecurrentmodulationsignalscanbegeneratedon theTRXpinbycontrol theTXlinevoltage level.Thecurrentmodulationsignalcanreturntothemastercontrollerthrouththepowersupplyline.

VTX

VIS

IMC

VVDD

Rev. 1.00 9 st 1 01 Rev. 1.00 93 st 1 01



Current Modulator ThePowerLineDataTransceiverdevicecanmodulatepower linecurrentbyaddingadditionalconstantcurrentsourcewhichiscontrolledbyTXline.WhentheTXlineisconnectedtolowlevel,thiscurrentmodulationfunctionwillbeenabled.Themodulationcurrentcanbecalculatedbythefollowingformula:

IIS=1.5V/RS

Application ConsiderationsIt isenvisagedthat thePowerLineDataTransceiverwillbeusedtogetherwithmicrocontrollerbased subsystemswhichwillbe required toprovide two I/Opins fordata transmissionandreception.TheMCUI/OlineconnectedtotheTXlinemustbesetupasanoutputwhiletheMCUI/OlineconnectedtotheRXlinemustbesetupasaninput.

Powerimpedanceplaysanimportantroleinthepowerdatatransceiverapplications,soitmustbewelldefinedtobeusedinreliabledatatransmitandreceiveoperations.

Theexternalcomponentsconnectedto theTRXpinmustbecarefullyselectedtoensure thatanenoughpulsedurationtimeisoccuredontheRXline.Data transmissionontheRXlinecanbedetectedusingtheMCURXINTinterruptorbypollingthePB6lineinputstatus.

Commondecouplingprotectionmustbetakentoensurereliableoperation.

Power Line Data Transceiver Application Circuits

LDO3.3V

LVD5.25V

CEB

VDD

VDD

VDDVCC

CN

TRX

IS

VSS

TX

RX

MCU

104

100Ω

22u

1kΩ

104

100Ω

1N4148

1N40041N4004

L+

L-

1N4004 1N4004

RPU

CMP

OPA

1.5V

RS

+

–

+

–

Current Modulator

EN1

VBG=1.5V

EN1B

R

EN1B

Zener5.6V

EN1B10MΩ

EN

2MΩ

IIS = 1.5VRS

EN

CMP & OPA Enable

ENBVDD

Rev. 1.00 9 st 1 01 Rev. 1.00 93 st 1 01



InterruptsInterruptsarean importantpartofanymicrocontroller system.WhenanexternaleventoraninternalfunctionsuchasaTimerModulerequiresmicrocontrollerattention, theircorrespondinginterruptwillenforceatemporarysuspensionofthemainprogramallowingthemicrocontrollertodirectattentiontotheirrespectiveneeds.Thedevicecontainsseveralexternalinterruptandinternalinterruptfunctions.TheexternalinterruptisgeneratedbytheactionoftheexternalINTpin,whilethe internal interruptsaregeneratedbyvarious internal functionssuchas thePowerLineDataTransceiver,TimerModules(TMs),TimeBases,LowVoltageDetector(LVD),EEPROMandtheA/DConverter.

Interrupt RegistersOverall interrupt control,whichbasicallymeans the settingof request flagswhen certainmicrocontrollerconditionsoccurandthesettingofinterruptenablebitsbytheapplicationprogram,iscontrolledbyaseriesofregisters,locatedintheSpecialPurposeDataMemory.Theregistersfallintotwocategories.ThefirstistheINTC0~INTC2registerswhichsetuptheprimaryinterruptsandthesecondistheINTEGregisterwhichsetuptheexternalinterrupttriggeredgetypeandtheRXdatatransmissiondetectioninterrupttriggeredgetype.

Eachregistercontainsanumberofenablebitstoenableordisableindividualregistersaswellasinterrupt flags to indicate thepresenceofan interrupt request.Thenamingconventionof thesefollowsaspecificpattern.Firstislistedanabbreviatedinterrupttype,thenthe(optional)numberofthatinterruptfollowedbyeitheran“E”forenable/disablebitor“F”forrequestflag.

Function Enable Bit Request Flag NoteGlobal EMI — —INT Pin INTE INTF —RXINT RXINTE RXINTF —Time Base TBnE TBnF n=0~1LVD LVE LVF —/D Converter DE DF —EEPROM DEE DEF —

TMSTMnPE STMnPF

n=0~1STMnE STMnF

Interrupt Register Bit Naming Conventions

Register Name

Bit

7 6 5 4 3 2 1 0INTEG — — — — INT1S1 INT1S0 INT0S1 INT0S0INTC0 — LVF RXINTF INTF LVE RXINTE INTE EMIINTC1 STM0F STM0PF DEF DF STM0E STM0PE DEE DEINTC STM1F STM1PF TB1F TB0F STM1E STM1PE TB1E TB0E

Interrupt Registers List

Rev. 1.00 94 st 1 01 Rev. 1.00 9 st 1 01



INTEG Register

Bit 7 6 5 4 3 2 1 0Name — — — — INT1S1 INT1S0 INT0S1 INT0S0R/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0

Bit7~4 Unimplemented,readas“0”Bit3~2 INT1S1~INT1S0:InterruptEdgeControlforRXINTLine

00:Disable01:Risingedge10:Fallingedge11:Risingandfallingedges

Bit1~0 INT0S1~INT0S0:InterruptEdgeControlforINTPin00:Disable01:Risingedge10:Fallingedge11:Risingandfallingedges

INTC0 Register

Bit 7 6 5 4 3 2 1 0Name — LVF RXINTF INTF LVE RXINTE INTE EMIR/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 0 0 0 0 0

Bit7 Unimplemented,readas“0”Bit6 LVF:LVDInterruptRequestFlag

0:Norequest1:Interruptrequest

Bit5 RXINTF:RXINTInterruptRequestFlag0:Norequest1:Interruptrequest

Bit4 INTF:ExternalInterruptRequestFlag0:Norequest1:Interruptrequest

Bit3 LVE:LVDInterruptControl0:Disable1:Enable

Bit2 RXINTE:RXINTInterruptControl0:Disable1:Enable

Bit1 INTE:ExternalInterruptControl0:Disable1:Enable

Bit0 EMI:GlobalInterruptControl0:Disable1:Enable

Rev. 1.00 94 st 1 01 Rev. 1.00 9 st 1 01



INTC1 Register

Bit 7 6 5 4 3 2 1 0Name STM0F STM0PF DEF DF STM0E STM0PE DEE DER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 STM0AF:STM0ComparatorAMatchInterruptRequestFlag0:Norequest1:Interruptrequest

Bit6 STM0PF:STM0ComparatorPMatchInterruptRequestFlag0:Norequest1:Interruptrequest

Bit5 DEF:DataEEPROMInterruptRequestFlag0:Norequest1:Interruptrequest

Bit4 ADF:A/DConverterInterruptRequestFlag0:Norequest1:Interruptrequest

Bit3 STM0AE:STM0ComparatorAMatchInterruptControl0:Disable1:Enable

Bit2 STM0PE:STM0ComparatorPMatchInterruptControl0:Disable1:Enable

Bit1 DEE:DataEEPROMInterruptControl0:Disable1:Enable

Bit0 ADE:A/DConverterInterruptControl0:Disable1:Enable

INTC2 Register

Bit 7 6 5 4 3 2 1 0Name STM1F STM1PF TB1F TB0F STM1E STM1PE TB1E TB0ER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 STM1AF:STM1ComparatorAMatchInterruptRequestFlag0:Norequest1:Interruptrequest

Bit6 STM1PF:STM1ComparatorPMatchInterruptRequestFlag0:Norequest1:Interruptrequest

Bit5 TB1F:TimeBase1InterruptRequestFlag0:Norequest1:Interruptrequest

Bit4 TB0F:TimeBase0InterruptRequestFlag0:Norequest1:Interruptrequest

Bit3 STM1AE:STM1ComparatorAMatchInterruptControl0:Disable1:Enable

Rev. 1.00 96 st 1 01 Rev. 1.00 9 st 1 01



Bit2 STM1PE:STM1ComparatorPMatchInterruptControl0:Disable1:Enable

Bit1 TB1E:TimeBase1InterruptControl0:Disable1:Enable

Bit0 TB0E:TimeBase0InterruptControl0:Disable1:Enable

Interrupt OperationWhentheconditionsforaninterrupteventoccur,suchasaTMComparatorP,ComparatorAmatchoranEEPROMWritecycleendsetc., therelevantinterruptrequestflagwillbeset.Whethertherequestflagactuallygeneratesaprogramjumpto therelevant interruptvector isdeterminedbytheconditionoftheinterruptenablebit.Iftheenablebitissethighthentheprogramwilljumptoitsrelevantvector;iftheenablebitiszerothenalthoughtheinterruptrequestflagissetanactualinterruptwillnotbegeneratedandtheprogramwillnotjumptotherelevantinterruptvector.Theglobalinterruptenablebit,ifclearedtozero,willdisableallinterrupts.

Whenaninterruptisgenerated,theProgramCounter,whichstorestheaddressofthenextinstructiontobeexecuted,willbetransferredontothestack.TheProgramCounterwillthenbeloadedwithanewaddresswhichwillbethevalueofthecorrespondinginterruptvector.Themicrocontrollerwillthenfetchitsnextinstructionfromthisinterruptvector.Theinstructionatthisvectorwillusuallybea“JMP”whichwilljumptoanothersectionofprogramwhichisknownastheinterruptserviceroutine.Hereislocatedthecodetocontroltheappropriateinterrupt.Theinterruptserviceroutinemustbe terminatedwitha“RETI”,whichretrieves theoriginalProgramCounteraddressfromthestackandallowsthemicrocontrollertocontinuewithnormalexecutionatthepointwheretheinterruptoccurred.

Thevarious interruptenablebits, togetherwith theirassociatedrequest flags,areshownin theaccompanyingdiagramswiththeirorderofpriority.Onceaninterruptsubroutineisserviced,alltheother interruptswillbeblocked,as theglobal interruptenablebit,EMIbitwillbeclearedautomatically.Thiswillpreventanyfurther interruptnestingfromoccurring.However, ifotherinterruptrequestsoccurduringthisinterval,althoughtheinterruptwillnotbeimmediatelyserviced,therequestflagwillstillberecorded.

Ifaninterruptrequiresimmediateservicingwhiletheprogramisalreadyinanotherinterruptserviceroutine,theEMIbitshouldbesetafterenteringtheroutine,toallowinterruptnesting.Ifthestackisfull,theinterruptrequestwillnotbeacknowledged,eveniftherelatedinterruptisenabled,untiltheStackPointerisdecremented.Ifimmediateserviceisdesired,thestackmustbepreventedfrombecomingfull.Incaseofsimultaneousrequests,theaccompanyingdiagramshowstheprioritythatisapplied.Alloftheinterruptrequestflagswhensetwillwake-upthedeviceifit isinSLEEPorIDLEMode,however topreventawake-upfromoccurringthecorrespondingflagshouldbesetbeforethedeviceisinSLEEPorIDLEMode.

Rev. 1.00 96 st 1 01 Rev. 1.00 9 st 1 01



Interrupt Name

Request Flags

Enable Bits

Master Enable Vector

EMI auto disabled in ISR

Priority

High

Low

04HEMI

20HEMI

2CHEMI

STM0 Comp.A STM0AF STM0AE

28H

STM0 Comp.P STM0PF STM0PE

EMI

14HEMI

LVD LVF LVE

18H

A/D Converter ADF ADE

EMI

1CH

EEPROM DEF DEE

EMI

Time Base 1 TB1F TB1E

0CHEMI

10HEMI

24HEMI

Time Base 0 TB0F TB0E

INT Pin INTF INTE

Request Flag, auto reset in ISR

STM1 Comp.A STM1AF STM1AE

STM1 Comp.P STM1PF STM1PE

RXINT RXINTF RXINTE 08HEMI

Interrupt Structure

External InterruptTheexternal interrupt iscontrolledbysignal transitionson thepin INT.Anexternal interruptrequestwilltakeplacewhentheexternalinterruptrequestflag,INTF,isset,whichwilloccurwhenatransition,whosetypeischosenbytheedgeselectbits,appearsontheexternalinterruptpins.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andrespectiveexternalinterruptenablebit,INTE,mustfirstbeset.Additionallythecorrectinterruptedge typemustbeselectedusing the INTEGregister toenable theexternal interruptfunctionandtochoosethetriggeredgetype.Astheexternalinterruptpinsarepin-sharedwithI/Opins, theycanonlybeconfiguredasexternalinterruptpinsif theirexternalinterruptenablebit inthecorrespondinginterruptregisterhasbeensetandtheexternal interruptpinisselectedbythecorrespondingpin-sharedfunctionselectionbits.Thepinmustalsobesetupasaninputbysettingthecorrespondingbitintheportcontrolregister.

Whentheinterrupt isenabled, thestackisnotfullandthecorrect transitiontypeappearsontheexternalinterruptpin,asubroutinecall totheexternalinterruptvector,will takeplace.Whentheinterrupt isserviced, theexternal interruptrequestflag,INTF,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.Notethatanypull-highresistorselectionson theexternal interruptpinswill remainvalideven if thepin isusedasanexternalinterruptinput.TheINTEGregistercanbeusedtoselectthetypeofactiveedgethatwilltriggertheexternalinterrupt.Achoiceofeitherrisingorfallingorbothedgetypescanbechosentotriggeranexternalinterrupt.Notethat theINTEGregistercanalsobeusedtodisabletheexternalinterruptfunction.

Rev. 1.00 98 st 1 01 Rev. 1.00 99 st 1 01



RX Data Transmission Detection InterruptTheRXdata transmissiondetection interrupt, abbreviated to thenameRXINT interrupt, iscontrolledbysignaltransitionsontheRXline.AnRXINTInterruptrequestwill takeplacewhentheRXINTInterruptrequestflag,RXINTF, isset,whichoccurswhentheadata transmissionisdetectedontheRXlineofthePowerlinedatatransceiver.Toallowtheprogramtobranchtoitsrespective interruptvectoraddress, theglobal interruptenablebit,EMI,andRXINTInterruptenablebit,RXINTE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandalowvoltageconditionoccurs,asubroutinecalltotherespectiveInterruptvector,willtakeplace.WhentheInterruptisserviced,theRXINTFflagwillbeautomaticallycleared.TheEMIbitwillalsobeautomaticallyclearedtodisableotherinterrupts.

TheINTEGregistercanbeused toselect the typeofactiveedge thatwill trigger theRXINTinterrupt.Achoiceofeitherrisingorfallingorbothedgetypescanbechosentotriggeranexternalinterrupt.NotethattheINTEGregistercanalsobeusedtodisabletheRXINTinterruptfunction.

Timer Module InterruptsTheStandardtypeTMseachhastwointerrupts,onecomesfromthecomparatorAmatchsituationandtheothercomesfromthecomparatorPmatchsituation.ForalloftheTMtypestherearetwointerruptrequestflagsandtwoenablecontrolbits.ATMinterruptrequestwill takeplacewhenanyoftheTMrequestflagsareset,asituationwhichoccurswhenaTMcomparatorPorAmatchsituationhappens.

Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andrespectiveTMInterruptenablebit,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandaTMcomparatormatchsituationoccurs,asubroutinecalltotherelevantInterruptvector locations,will takeplace.WhentheTMinterrupt isserviced, theTMinterruptrequestflagswillbeautomaticallycleared.TheEMIbitwillalsobeautomaticallyclearedtodisableotherinterrupts.

LVD InterruptAnLVDInterruptrequestwill takeplacewhentheLVDInterruptrequestflag,LVF,isset,whichoccurswhentheLowVoltageDetectorfunctiondetectsalowpowersupplyvoltage.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andLowVoltageInterruptenablebit,LVE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandalowvoltageconditionoccurs,asubroutinecalltotherespectiveInterruptvector,willtakeplace.WhentheLowVoltageInterruptisserviced,theLVFflagwillbeautomaticallycleared.TheEMIbitwillalsobeautomaticallyclearedtodisableotherinterrupts.

EEPROM InterruptAnEEPROMInterruptrequestwilltakeplacewhentheEEPROMInterruptrequestflag,DEF,isset,whichoccurswhenanEEPROMWritecycleends.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress, theglobal interruptenablebit,EMI,andEEPROMInterruptenablebit,DEE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandanEEPROMWritecycleends,asubroutinecalltotherespectiveEEPROMInterruptvectorwilltakeplace.WhentheEEPROMInterruptisserviced,theDEFflagwillbeautomaticallycleared.TheEMIbitwillalsobeautomaticallyclearedtodisableotherinterrupts.

Rev. 1.00 98 st 1 01 Rev. 1.00 99 st 1 01



A/D Converter InterruptTheA/DConverterInterruptiscontrolledbytheterminationofanA/Dconversionprocess.AnA/DConverterInterruptrequestwilltakeplacewhentheA/DConverterInterruptrequestflag,ADF,isset,whichoccurswhentheA/Dconversionprocessfinishes.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andA/DInterruptenablebit,ADE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandtheA/Dconversionprocesshasended,asubroutinecalltotheA/DConverterInterruptvector,willtakeplace.Whentheinterruptisserviced,theA/DConverterInterruptflag,ADF,willbeautomaticallycleared.TheEMIbitwillalsobeautomaticallyclearedtodisableotherinterrupts.

Time Base InterruptsThefunctionoftheTimeBaseInterruptsistoprovideregulartimesignalintheformofaninternalinterrupt.Theyarecontrolledbytheoverflowsignalsfromtheirrespectivetimerfunctions.Whenthesehappens their respective interrupt request flags,TB0ForTB1Fwillbeset.Toallowtheprogramtobranchtotheirrespectiveinterruptvectoraddresses,theglobalinterruptenablebit,EMI,andTimeBaseenablebits,TB0EorTB1E,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandtheTimeBaseoverflows,asubroutinecall totheirrespectivevectorlocationswilltakeplace.Whentheinterruptisserviced,therespectiveinterruptrequestflag,TB0ForTB1F,willbeautomaticallycleared,theEMIbitwillalsobeautomaticallyclearedtodisableotherinterrupts.

ThepurposeoftheTimeBaseInterruptistoprovideaninterruptsignalatfixedtimeperiods.Itsclocksource, fPSC,originates fromthe internalclocksourcefSYS, fSYS/4or fSUBand thenpassesthroughadivider,thedivisionratioofwhichisselectedbyprogrammingtheappropriatebitsintheTB0CandTB1Cregisterstoobtainlongerinterruptperiodswhosevalueranges.Theclocksourcewhichinturncontrols theTimeBaseinterruptperiodisselectedusingtheCLKSEL1~CLKSEL0bitsinthePSCRregister.

MUX

fSYS/4fSYS

fSUB

Prescaler

CLKSEL[1:0]

fPSC MUX

TBn[:0]

Time Base n Interrpt

TBnON

fPSC/8 ~ fPSC/1

Time Base Interrupt (n=0~1)

PSCR Register

Bit 7 6 5 4 3 2 1 0Name — — — — — — CLKSEL1 CLKSEL0R/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas“0”Bit1~0 CLKSEL1~CLKSEL0:Prescalerclocksourceselection

00:fSYS

01:fSYS/41x:fSUB

Rev. 1.00 100 st 1 01 Rev. 1.00 101 st 1 01



TB0C Register

Bit 7 6 5 4 3 2 1 0Name TB0ON — — — — TB0 TB01 TB00R/W R/W — — — — R/W R/W R/WPOR 0 — — — — 0 0 0

Bit7 TB0ON:TimeBase0Control0:Disable1:Enable

Bit6~3 Unimplemented,readas“0”Bit2~0 TB02~TB00:SelectTimeBase0Time-outPeriod

000:28/fPSC001:29/fPSC010:210/fPSC011:211/fPSC100:212/fPSC101:213/fPSC110:214/fPSC111:215/fPSC

TB1C Register

Bit 7 6 5 4 3 2 1 0Name TB1ON — — — — TB1 TB11 TB10R/W R/W — — — — R/W R/W R/WPOR 0 — — — — 0 0 0

Bit7 TB1ON:TimeBase1Control0:Disable1:Enable

Bit6~3 Unimplemented,readas“0”Bit2~0 TB12~TB10:SelectTimeBase1Time-outPeriod

000:28/fPSC001:29/fPSC010:210/fPSC011:211/fPSC100:212/fPSC101:213/fPSC110:214/fPSC111:215/fPSC

Rev. 1.00 100 st 1 01 Rev. 1.00 101 st 1 01



Interrupt Wake-up FunctionEachof the interruptfunctionshas thecapabilityofwakingupthemicrocontrollerwhenin theSLEEPorIDLEMode.Awake-upisgeneratedwhenaninterruptrequestflagchangesfromlowtohighandisindependentofwhethertheinterruptisenabledornot.Therefore,eventhoughthedeviceisintheSLEEPorIDLEModeanditssystemoscillatorstopped,situationssuchasexternaledgetransitionsontheexternalinterruptpinsoralowpowersupplyvoltagemaycausetheirrespectiveinterruptflagtobesethighandconsequentlygenerateaninterrupt.Caremustthereforebetakenifspuriouswake-upsituationsaretobeavoided.Ifaninterruptwake-upfunctionistobedisabledthenthecorrespondinginterruptrequestflagshouldbesethighbeforethedeviceenterstheSLEEPorIDLEMode.Theinterruptenablebitshavenoeffectontheinterruptwake-upfunction.

Programming ConsiderationsBydisablingtherelevantinterruptenablebits,arequestedinterruptcanbepreventedfrombeingserviced,however,oncean interrupt request flag is set, itwill remain in thiscondition in theinterruptregisteruntilthecorrespondinginterruptisservicedoruntiltherequestflagisclearedbytheapplicationprogram.

It isrecommendedthatprogramsdonotusethe“CALL”instructionwithintheinterruptservicesubroutine.Interruptsoftenoccurinanunpredictablemannerorneedtobeservicedimmediately.Ifonlyonestackisleftandtheinterruptisnotwellcontrolled,theoriginalcontrolsequencewillbedamagedonceaCALLsubroutineisexecutedintheinterruptsubroutine.

Everyinterrupthasthecapabilityofwakingupthemicrocontrollerwhenit isinSLEEPorIDLEMode,thewakeupbeinggeneratedwhentheinterruptrequestflagchangesfromlowtohigh.IfitisrequiredtopreventacertaininterruptfromwakingupthemicrocontrollerthenitsrespectiverequestflagshouldbefirstsethighbeforeenterSLEEPorIDLEMode.

AsonlytheProgramCounter ispushedontothestack, thenwhentheinterrupt isserviced, if thecontentsof theaccumulator,statusregisterorotherregistersarealteredbythe interruptserviceprogram,theircontentsshouldbesavedto thememoryat thebeginningof the interruptserviceroutine.Toreturnfromaninterruptsubroutine,eitheraRETorRETIinstructionmaybeexecuted.TheRETIinstructioninadditiontoexecutingareturntothemainprogramalsoautomaticallysetstheEMIbithightoallowfurtherinterrupts.TheRETinstructionhoweveronlyexecutesareturntothemainprogramleavingtheEMIbitinitspresentzerostateandthereforedisablingtheexecutionoffurtherinterrupts.

Rev. 1.00 10 st 1 01 Rev. 1.00 103 st 1 01



Low Voltage Detector – LVDThedevicehasaLowVoltageDetectorfunction,alsoknownasLVD.Thisenabledthedevicetomonitorthepowersupplyvoltage,VDD,andprovideawarningsignalshoulditfallbelowacertainlevel.Thisfunctionmaybeespeciallyusefulinbatteryapplicationswherethesupplyvoltagewillgraduallyreduceasthebatteryages,asitallowsanearlywarningbatterylowsignaltobegenerated.TheLowVoltageDetectoralsohasthecapabilityofgeneratinganinterruptsignal.

LVD RegisterTheLowVoltageDetectorfunctioniscontrolledusingasingleregisterwiththenameLVDC.Threebits inthisregister,VLVD2~VLVD0,areusedtoselectoneofeightfixedvoltagesbelowwhichalowvoltageconditionwillbedetermined.AlowvoltageconditionisindicatedwhentheLVDObitisset.IftheLVDObitislow,thisindicatesthattheVDDvoltageisabovethepresetlowvoltagevalue.TheLVDENbit isusedtocontrol theoverallon/offfunctionof thelowvoltagedetector.Settingthebithighwillenablethelowvoltagedetector.Clearingthebittozerowillswitchofftheinternallowvoltagedetectorcircuits.Asthelowvoltagedetectorwillconsumeacertainamountofpower,itmaybedesirabletoswitchoffthecircuitwhennotinuse,animportantconsiderationinpowersensitivebatterypoweredapplications.

LVDC Register

Bit 7 6 5 4 3 2 1 0Name — — LVDO LVDEN VBGEN VLVD VLVD1 VLVD0R/W — — R R/W R/W R/W R/W R/WPOR — — 0 0 0 0 0 0

Bit7~6 Unimplemented,readas“0”Bit5 LVDO:LVDOutputFlag

0:NoLowVoltageDetect1:LowVoltageDetect

Bit4 LVDEN:LowVoltageDetectorControl0:Disable1:Enable

Bit3 VBGEN:BandgapBufferControl0:Disable1:Enable

NotethattheBandgapcircuitisenabledwhentheLVDortheLVRfunctionisenabledorwhentheVBGENbitissethigh.

Bit2~0 VLVD2~VLVD0:SelectLVDVoltage000:2.0V001:2.2V010:2.4V011:2.7V100:3.0V101:3.3V110:3.6V111:4.0V

Rev. 1.00 10 st 1 01 Rev. 1.00 103 st 1 01



LVD OperationTheLowVoltageDetectorfunctionoperatesbycomparingthepowersupplyvoltage,VDD,withapre-specifiedvoltagelevelstoredintheLVDCregister.Thishasarangeofbetween2.0Vand4.0V.Whenthepowersupplyvoltage,VDD,fallsbelowthispre-determinedvalue,theLVDObitwillbesethighindicatingalowpowersupplyvoltagecondition.WhenthedeviceisintheSLEEPmode,thelowvoltagedetectorwillbedisabledevenif theLVDENbit ishigh.AfterenablingtheLowVoltageDetector,atimedelaytLVDSshouldbeallowedforthecircuitrytostabilisebeforereadingtheLVDObit.NotealsothatastheVDDvoltagemayriseandfallratherslowly,atthevoltagenearsthatofVLVD,theremaybemultiplebitLVDOtransitions.

VDD

LVDEN

LVDO

VLVD

tLVDS

LVD Operation

TheLowVoltageDetectoralsohasitsowninterrupt,providinganalternativemeansoflowvoltagedetection, inadditiontopollingtheLVDObit.TheinterruptwillonlybegeneratedafteradelayoftLVDaftertheLVDObithasbeensethighbyalowvoltagecondition.WhenthedeviceisintheSLEEPmode,thelowvoltagedetectorwillbedisabledeveniftheLVDENbitishigh.Inthiscase,theLVFinterruptrequestflagwillbeset,causinganinterrupttobegeneratedifVDDfallsbelowthepresetLVDvoltage.Thiswillcausethedevicetowake-upfromtheIDLEMode,howeverif theLowVoltageDetectorwakeupfunctionisnotrequiredthentheLVFflagshouldbefirstsethighbeforethedeviceenterstheIDLEMode.

Application Circuits

1

1

2

2

3

3

4

4

5

5

6

6

D D

C C

B B

A A

Title

Number RevisionSize

B

Date: 2017/7/5 Sheet ofFile: C:\Users\..\HT68FH002.SchDoc Drawn By:

+-

BR1+-BR2

L1

L2

D1 R1

C1

R2

R3

VCC

R4C2

DC1

DC2

C3

Q1

VDDR8

D2

D7

R9

L1

B1

S2

S3

S4

S5

R6

C4

C5

Q2

Q3

R7

R13

R5

P1 P2D3

D6

HT45FH0082聲光報警器

U1

BA45FH0082

TRXISVSS

I/OI/OI/OI/OVSS

VCC VDD

I/OVDDI/OI/OI/O

U2

HT45F2020

VCCI/O

I/O

OUT1

I/OR14 S6

I/O I/O

Rev. 1.00 104 st 1 01 Rev. 1.00 10 st 1 01



Instruction Set

IntroductionCentral to thesuccessfuloperationofanymicrocontroller is its instructionset,whichisasetofprograminstructioncodesthatdirectsthemicrocontrollertoperformcertainoperations.InthecaseofHoltekmicrocontroller,acomprehensiveandflexiblesetofover60instructionsisprovidedtoenableprogrammerstoimplementtheirapplicationwiththeminimumofprogrammingoverheads.

Foreasierunderstandingofthevariousinstructioncodes, theyhavebeensubdividedintoseveralfunctionalgroupings.

Instruction TimingMostinstructionsareimplementedwithinoneinstructioncycle.Theexceptionstothisarebranch,call,or tablereadinstructionswheretwoinstructioncyclesarerequired.Oneinstructioncycleisequalto4systemclockcycles,thereforeinthecaseofan4MHzsystemoscillator,mostinstructionswouldbeimplementedwithin1μsandbranchorcallinstructionswouldbeimplementedwithin1μs.AlthoughinstructionswhichrequireonemorecycletoimplementaregenerallylimitedtotheJMP,CALL,RET,RETIandtablereadinstructions,itisimportanttorealizethatanyotherinstructionswhichinvolvemanipulationoftheProgramCounterLowregisterorPCLwillalsotakeonemorecycletoimplement.AsinstructionswhichchangethecontentsofthePCLwillimplyadirectjumptothatnewaddress,onemorecyclewillberequired.Examplesofsuchinstructionswouldbe"CLRPCL"or"MOVPCL,A".Forthecaseofskipinstructions,itmustbenotedthatiftheresultofthecomparisoninvolvesaskipoperationthenthiswillalsotakeonemorecycle,ifnoskipisinvolvedthenonlyonecycleisrequired.

Moving and Transferring DataThe transferofdatawithin themicrocontrollerprogram isoneof themost frequentlyusedoperations.MakinguseofthreekindsofMOVinstructions,datacanbetransferredfromregisterstotheAccumulatorandvice-versaaswellasbeingabletomovespecificimmediatedatadirectlyintotheAccumulator.Oneofthemostimportantdatatransferapplicationsis toreceivedatafromtheinputportsandtransferdatatotheoutputports.

Arithmetic OperationsTheabilitytoperformcertainarithmeticoperationsanddatamanipulationisanecessaryfeatureofmostmicrocontrollerapplications.WithintheHoltekmicrocontrollerinstructionsetarearangeofaddandsubtract instructionmnemonicstoenablethenecessaryarithmetictobecarriedout.Caremustbe taken toensurecorrecthandlingofcarryandborrowdatawhenresultsexceed255foradditionandlessthan0forsubtraction.TheincrementanddecrementinstructionsINC,INCA,DECandDECAprovideasimplemeansofincreasingordecreasingbyavalueofoneofthevaluesinthedestinationspecified.

Rev. 1.00 104 st 1 01 Rev. 1.00 10 st 1 01



Logical and Rotate OperationThestandardlogicaloperationssuchasAND,OR,XORandCPLallhavetheirowninstructionwithintheHoltekmicrocontroller instructionset.Aswiththecaseofmost instructionsinvolvingdatamanipulation, datamust pass through theAccumulatorwhichmay involve additionalprogrammingsteps. Inall logicaldataoperations, thezero flagmaybeset if the resultof theoperationiszero.AnotherformoflogicaldatamanipulationcomesfromtherotateinstructionssuchasRR,RL,RRCandRLCwhichprovideasimplemeansofrotatingonebitrightorleft.Differentrotateinstructionsexistdependingonprogramrequirements.Rotateinstructionsareusefulforserialportprogrammingapplicationswheredatacanberotatedfromaninternalregister intotheCarrybitfromwhereitcanbeexaminedandthenecessaryserialbitsethighorlow.Anotherapplicationwhichrotatedataoperationsareusedistoimplementmultiplicationanddivisioncalculations.

Branches and Control TransferProgrambranchingtakestheformofeitherjumpstospecifiedlocationsusingtheJMPinstructionor toa subroutineusing theCALL instruction.Theydiffer in the sense that in thecaseofasubroutinecall, theprogrammustreturn to the instruction immediatelywhenthesubroutinehasbeencarriedout.Thisisdonebyplacingareturninstruction"RET"inthesubroutinewhichwillcausetheprogramtojumpbacktotheaddressrightaftertheCALLinstruction.InthecaseofaJMPinstruction,theprogramsimplyjumpstothedesiredlocation.ThereisnorequirementtojumpbacktotheoriginaljumpingoffpointasinthecaseoftheCALLinstruction.Onespecialandextremelyusefulsetofbranchinstructionsaretheconditionalbranches.Hereadecisionisfirstmaderegardingtheconditionofacertaindatamemoryor individualbits.Dependingupon theconditions, theprogramwillcontinuewiththenextinstructionorskipoveritandjumptothefollowinginstruction.These instructionsare thekey todecisionmakingandbranchingwithin theprogramperhapsdeterminedbytheconditionofcertaininputswitchesorbytheconditionofinternaldatabits.

Bit OperationsTheabilitytoprovidesinglebitoperationsonDataMemoryisanextremelyflexiblefeatureofallHoltekmicrocontrollers.Thisfeature isespeciallyusefulforoutputportbitprogrammingwhereindividualbitsorportpinscanbedirectlysethighorlowusingeitherthe"SET[m].i"or"CLR[m].i" instructionsrespectively.Thefeatureremovestheneedforprogrammers tofirstreadthe8-bitoutputport,manipulatetheinputdatatoensurethatotherbitsarenotchangedandthenoutputtheportwiththecorrectnewdata.Thisread-modify-writeprocessistakencareofautomaticallywhenthesebitoperationinstructionsareused.

Table Read OperationsDatastorage isnormally implementedbyusing registers.However,whenworkingwith largeamountsoffixeddata, thevolumeinvolvedoftenmakesit inconvenienttostorethefixeddataintheDataMemory.Toovercomethisproblem,HoltekmicrocontrollersallowanareaofProgramMemory tobesetasa tablewheredatacanbedirectlystored.Asetofeasy touse instructionsprovides themeansbywhich this fixeddatacanbereferencedandretrievedfromtheProgramMemory.

Other OperationsInaddition to theabovefunctional instructions,a rangeofother instructionsalsoexistsuchasthe"HALT"instructionforPower-downoperationsand instructions tocontrol theoperationoftheWatchdogTimerfor reliableprogramoperationsunderextremeelectricorelectromagneticenvironments.Fortheirrelevantoperations,refertothefunctionalrelatedsections.

Rev. 1.00 106 st 1 01 Rev. 1.00 10 st 1 01



Instruction Set SummaryThefollowingtabledepictsasummaryoftheinstructionsetcategorisedaccordingtofunctionandcanbeconsultedasabasicinstructionreferenceusingthefollowinglistedconventions.

Table Conventionsx:Bitsimmediatedatam:DataMemoryaddressA:Accumulatori:0~7numberofbitsaddr:Programmemoryaddress

Mnemonic Description Cycles Flag AffectedArithmeticDD [m] dd Data Memory to CC 1 Z C C OVDDM [m] dd CC to Data Memory 1Note Z C C OVDD x dd immediate data to CC 1 Z C C OVDC [m] dd Data Memory to CC with Carry 1 Z C C OVDCM [m] dd CC to Data memory with Carry 1Note Z C C OVSUB x Sbtract immediate data from the CC 1 Z C C OVSUB [m] Sbtract Data Memory from CC 1 Z C C OVSUBM [m] Sbtract Data Memory from CC with reslt in Data Memory 1Note Z C C OVSBC [m] Sbtract Data Memory from CC with Carry 1 Z C C OVSBCM [m] Sbtract Data Memory from CC with Carry reslt in Data Memory 1Note Z C C OVD [m] Decimal adjst CC for ddition with reslt in Data Memory 1Note CLogic OperationND [m] Loical ND Data Memory to CC 1 ZOR [m] Loical OR Data Memory to CC 1 ZXOR [m] Loical XOR Data Memory to CC 1 ZNDM [m] Loical ND CC to Data Memory 1Note ZORM [m] Loical OR CC to Data Memory 1Note ZXORM [m] Loical XOR CC to Data Memory 1Note ZND x Loical ND immediate Data to CC 1 ZOR x Loical OR immediate Data to CC 1 ZXOR x Loical XOR immediate Data to CC 1 ZCPL [m] Complement Data Memory 1Note ZCPL [m] Complement Data Memory with reslt in CC 1 ZIncrement & DecrementINC [m] Increment Data Memory with reslt in CC 1 ZINC [m] Increment Data Memory 1Note ZDEC [m] Decrement Data Memory with reslt in CC 1 ZDEC [m] Decrement Data Memory 1Note ZRotateRR [m] Rotate Data Memory riht with reslt in CC 1 NoneRR [m] Rotate Data Memory riht 1Note NoneRRC [m] Rotate Data Memory riht throh Carry with reslt in CC 1 CRRC [m] Rotate Data Memory riht throh Carry 1Note CRL [m] Rotate Data Memory left with reslt in CC 1 NoneRL [m] Rotate Data Memory left 1Note NoneRLC [m] Rotate Data Memory left throh Carry with reslt in CC 1 CRLC [m] Rotate Data Memory left throh Carry 1Note C

Rev. 1.00 106 st 1 01 Rev. 1.00 10 st 1 01



Mnemonic Description Cycles Flag AffectedData MoveMOV [m] Move Data Memory to CC 1 NoneMOV [m] Move CC to Data Memory 1Note NoneMOV x Move immediate data to CC 1 NoneBit OperationCLR [m].i Clear bit of Data Memory 1Note NoneSET [m].i Set bit of Data Memory 1Note NoneBranch OperationJMP addr Jmp nconditionally NoneSZ [m] Skip if Data Memory is zero 1Note NoneSZ [m] Skip if Data Memory is zero with data movement to CC 1Note NoneSZ [m].i Skip if bit i of Data Memory is zero 1Note NoneSNZ [m].i Skip if bit i of Data Memory is not zero 1Note NoneSIZ [m] Skip if increment Data Memory is zero 1Note NoneSDZ [m] Skip if decrement Data Memory is zero 1Note NoneSIZ [m] Skip if increment Data Memory is zero with reslt in CC 1Note NoneSDZ [m] Skip if decrement Data Memory is zero with reslt in CC 1Note NoneCLL addr Sbrotine call NoneRET Retrn from sbrotine NoneRET x Retrn from sbrotine and load immediate data to CC NoneRETI Retrn from interrpt NoneTable Read OperationTBRD [m] Read table (specific page) to TBLH and Data Memory Note NoneTBRDC [m] Read table (crrent pae) to TBLH and Data Memory Note NoneTBRDL [m] Read table (last pae) to TBLH and Data Memory Note NoneMiscellaneousNOP No operation 1 NoneCLR [m] Clear Data Memory 1Note NoneSET [m] Set Data Memory 1Note NoneCLR WDT Clear Watchdo Timer 1 TO PDFCLR WDT1 Pre-clear Watchdo Timer 1 TO PDFCLR WDT Pre-clear Watchdo Timer 1 TO PDFSWP [m] Swap nibbles of Data Memory 1Note NoneSWP [m] Swap nibbles of Data Memory with reslt in CC 1 NoneHLT Enter power down mode 1 TO PDF

Note:1.Forskipinstructions,iftheresultofthecomparisoninvolvesaskipthentwocyclesarerequired,ifnoskiptakesplaceonlyonecycleisrequired.

2.AnyinstructionwhichchangesthecontentsofthePCLwillalsorequire2cyclesforexecution.3.For the"CLRWDT1"and"CLRWDT2"instructions theTOandPDFflagsmaybeaffectedbytheexecution status.TheTOandPDF flagsareclearedafterboth "CLRWDT1"and"CLRWDT2"instructionsareconsecutivelyexecuted.OtherwisetheTOandPDFflagsremainunchanged.

Rev. 1.00 108 st 1 01 Rev. 1.00 109 st 1 01



Instruction Definition

ADC A,[m] AddDataMemorytoACCwithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]+CAffectedflag(s) OV,Z,AC,C

ADCM A,[m] AddACCtoDataMemorywithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]+CAffectedflag(s) OV,Z,AC,C

ADD A,[m] AddDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]Affectedflag(s) OV,Z,AC,C

ADD A,x AddimmediatedatatoACCDescription ThecontentsoftheAccumulatorandthespecifiedimmediatedataareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+xAffectedflag(s) OV,Z,AC,C

ADDM A,[m] AddACCtoDataMemoryDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]Affectedflag(s) OV,Z,AC,C

AND A,[m] LogicalANDDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″[m]Affectedflag(s) Z

AND A,x LogicalANDimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″xAffectedflag(s) Z

ANDM A,[m] LogicalANDACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalAND operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″AND″[m]Affectedflag(s) Z

Rev. 1.00 108 st 1 01 Rev. 1.00 109 st 1 01



CALL addr SubroutinecallDescription Unconditionallycallsasubroutineatthespecifiedaddress.TheProgramCounterthen incrementsby1toobtaintheaddressofthenextinstructionwhichisthenpushedontothe stack.Thespecifiedaddressisthenloadedandtheprogramcontinuesexecutionfromthis newaddress.Asthisinstructionrequiresanadditionaloperation,itisatwocycleinstruction.Operation Stack←ProgramCounter+1 ProgramCounter←addrAffectedflag(s) None

CLR [m] ClearDataMemoryDescription EachbitofthespecifiedDataMemoryisclearedto0.Operation [m]←00HAffectedflag(s) None

CLR [m].i ClearbitofDataMemoryDescription BitiofthespecifiedDataMemoryisclearedto0.Operation [m].i←0Affectedflag(s) None

CLR WDT ClearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CLR WDT1 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksin conjunctionwithCLRWDT2andmustbeexecutedalternatelywithCLRWDT2tohave effect.RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT2will havenoeffect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CLR WDT2 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksinconjunction withCLRWDT1andmustbeexecutedalternatelywithCLRWDT1tohaveeffect. RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT1willhaveno effect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CPL [m] ComplementDataMemoryDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Operation [m]←[m]Affectedflag(s) Z

Rev. 1.00 110 st 1 01 Rev. 1.00 111 st 1 01



CPLA [m] ComplementDataMemorywithresultinACCDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Thecomplementedresultisstoredin theAccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]Affectedflag(s) Z

DAA [m] Decimal-AdjustACCforadditionwithresultinDataMemoryDescription ConvertthecontentsoftheAccumulatorvaluetoaBCD(BinaryCodedDecimal)value resultingfromthepreviousadditionoftwoBCDvariables.Ifthelownibbleisgreaterthan9 orifACflagisset,thenavalueof6willbeaddedtothelownibble.Otherwisethelownibble remainsunchanged.Ifthehighnibbleisgreaterthan9oriftheCflagisset,thenavalueof6 willbeaddedtothehighnibble.Essentially,thedecimalconversionisperformedbyadding 00H,06H,60Hor66HdependingontheAccumulatorandflagconditions.OnlytheCflag maybeaffectedbythisinstructionwhichindicatesthatiftheoriginalBCDsumisgreaterthan 100,itallowsmultipleprecisiondecimaladdition.Operation [m]←ACC+00Hor [m]←ACC+06Hor [m]←ACC+60Hor [m]←ACC+66HAffectedflag(s) C

DEC [m] DecrementDataMemoryDescription DatainthespecifiedDataMemoryisdecrementedby1.Operation [m]←[m]−1Affectedflag(s) Z

DECA [m] DecrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisdecrementedby1.Theresultisstoredinthe Accumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]−1Affectedflag(s) Z

HALT EnterpowerdownmodeDescription Thisinstructionstopstheprogramexecutionandturnsoffthesystemclock.Thecontentsof theDataMemoryandregistersareretained.TheWDTandprescalerarecleared.Thepower downflagPDFissetandtheWDTtime-outflagTOiscleared.Operation TO←0 PDF←1Affectedflag(s) TO,PDF

INC [m] IncrementDataMemoryDescription DatainthespecifiedDataMemoryisincrementedby1.Operation [m]←[m]+1Affectedflag(s) Z

INCA [m] IncrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisincrementedby1.TheresultisstoredintheAccumulator. ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]+1Affectedflag(s) Z

Rev. 1.00 110 st 1 01 Rev. 1.00 111 st 1 01



JMP addr JumpunconditionallyDescription ThecontentsoftheProgramCounterarereplacedwiththespecifiedaddress.Program executionthencontinuesfromthisnewaddress.Asthisrequirestheinsertionofadummy instructionwhilethenewaddressisloaded,itisatwocycleinstruction.Operation ProgramCounter←addrAffectedflag(s) None

MOV A,[m] MoveDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Operation ACC←[m]Affectedflag(s) None

MOV A,x MoveimmediatedatatoACCDescription TheimmediatedataspecifiedisloadedintotheAccumulator.Operation ACC←xAffectedflag(s) None

MOV [m],A MoveACCtoDataMemoryDescription ThecontentsoftheAccumulatorarecopiedtothespecifiedDataMemory.Operation [m]←ACCAffectedflag(s) None

NOP NooperationDescription Nooperationisperformed.Executioncontinueswiththenextinstruction.Operation NooperationAffectedflag(s) None

OR A,[m] LogicalORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwise logicalORoperation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″[m]Affectedflag(s) Z

OR A,x LogicalORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″xAffectedflag(s) Z

ORM A,[m] LogicalORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″OR″[m]Affectedflag(s) Z

RET ReturnfromsubroutineDescription TheProgramCounterisrestoredfromthestack.Programexecutioncontinuesattherestored address.Operation ProgramCounter←StackAffectedflag(s) None

Rev. 1.00 11 st 1 01 Rev. 1.00 113 st 1 01



RET A,x ReturnfromsubroutineandloadimmediatedatatoACCDescription TheProgramCounterisrestoredfromthestackandtheAccumulatorloadedwiththespecified immediatedata.Programexecutioncontinuesattherestoredaddress.Operation ProgramCounter←Stack ACC←xAffectedflag(s) None

RETI ReturnfrominterruptDescription TheProgramCounterisrestoredfromthestackandtheinterruptsarere-enabledbysettingthe EMIbit.EMIisthemasterinterruptglobalenablebit.Ifaninterruptwaspendingwhenthe RETIinstructionisexecuted,thependingInterruptroutinewillbeprocessedbeforereturning tothemainprogram.Operation ProgramCounter←Stack EMI←1Affectedflag(s) None

RL [m] RotateDataMemoryleftDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←[m].7Affectedflag(s) None

RLA [m] RotateDataMemoryleftwithresultinACCDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0. TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremain unchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←[m].7Affectedflag(s) None

RLC [m] RotateDataMemoryleftthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←C C←[m].7Affectedflag(s) C

RLCA [m] RotateDataMemoryleftthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7replacesthe Carrybitandtheoriginalcarryflagisrotatedintothebit0.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←C C←[m].7Affectedflag(s) C

RR [m] RotateDataMemoryrightDescription ThecontentsofthespecifiedDataMemoryarerotatedrightby1bitwithbit0rotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←[m].0Affectedflag(s) None

Rev. 1.00 11 st 1 01 Rev. 1.00 113 st 1 01



RRA [m] RotateDataMemoryrightwithresultinACCDescription DatainthespecifiedDataMemoryisrotatedrightby1bitwithbit0rotatedintobit7. TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremain unchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←[m].0Affectedflag(s) None

RRC [m] RotateDataMemoryrightthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←C C←[m].0Affectedflag(s) C

RRCA [m] RotateDataMemoryrightthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0replaces theCarrybitandtheoriginalcarryflagisrotatedintobit7.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←C C←[m].0Affectedflag(s) C

SBC A,[m] SubtractDataMemoryfromACCwithCarryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheAccumulator.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]−CAffectedflag(s) OV,Z,AC,C

SBCM A,[m] SubtractDataMemoryfromACCwithCarryandresultinDataMemoryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheDataMemory.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]−CAffectedflag(s) OV,Z,AC,C

SDZ [m] SkipifdecrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]−1 Skipif[m]=0Affectedflag(s) None

Rev. 1.00 114 st 1 01 Rev. 1.00 11 st 1 01



SDZA [m] SkipifdecrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0, theprogramproceedswiththefollowinginstruction.Operation ACC←[m]−1 SkipifACC=0Affectedflag(s) None

SET [m] SetDataMemoryDescription EachbitofthespecifiedDataMemoryissetto1.Operation [m]←FFHAffectedflag(s) None

SET [m].i SetbitofDataMemoryDescription BitiofthespecifiedDataMemoryissetto1.Operation [m].i←1Affectedflag(s) None

SIZ [m] SkipifincrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]+1 Skipif[m]=0Affectedflag(s) None

SIZA [m] SkipifincrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot 0theprogramproceedswiththefollowinginstruction.Operation ACC←[m]+1 SkipifACC=0Affectedflag(s) None

SNZ [m].i SkipifbitiofDataMemoryisnot0Description IfbitiofthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i≠0Affectedflag(s) None

SUB A,[m] SubtractDataMemoryfromACCDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheAccumulator.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]Affectedflag(s) OV,Z,AC,C

Rev. 1.00 114 st 1 01 Rev. 1.00 11 st 1 01



SUBM A,[m] SubtractDataMemoryfromACCwithresultinDataMemoryDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheDataMemory.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]Affectedflag(s) OV,Z,AC,C

SUB A,x SubtractimmediatedatafromACCDescription TheimmediatedataspecifiedbythecodeissubtractedfromthecontentsoftheAccumulator. TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionisnegative,theC flagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−xAffectedflag(s) OV,Z,AC,C

SWAP [m] SwapnibblesofDataMemoryDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.Operation [m].3~[m].0↔[m].7~[m].4Affectedflag(s) None

SWAPA [m] SwapnibblesofDataMemorywithresultinACCDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.The resultisstoredintheAccumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC.3~ACC.0←[m].7~[m].4 ACC.7~ACC.4←[m].3~[m].0Affectedflag(s) None

SZ [m] SkipifDataMemoryis0Description IfthecontentsofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.Operation Skipif[m]=0Affectedflag(s) None

SZA [m] SkipifDataMemoryis0withdatamovementtoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Ifthevalueiszero, thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstruction whilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0the programproceedswiththefollowinginstruction.Operation ACC←[m] Skipif[m]=0Affectedflag(s) None

SZ [m].i SkipifbitiofDataMemoryis0Description IfbitiofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthisrequires theinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultisnot0,theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i=0Affectedflag(s) None

Rev. 1.00 116 st 1 01 Rev. 1.00 11 st 1 01



TABRD [m] Readtable(specificpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(specificpage)addressedbythetablepointerpair (TBHPandTBLP)ismovedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

TABRDC [m] Readtable(currentpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(currentpage)addressedbythetablepointer(TBLP)is movedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

TABRDL [m] Readtable(lastpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(lastpage)addressedbythetablepointer(TBLP)ismoved tothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

XOR A,[m] LogicalXORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″[m]Affectedflag(s) Z

XORM A,[m] LogicalXORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalXOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″XOR″[m]Affectedflag(s) Z

XOR A,x LogicalXORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″xAffectedflag(s) Z

Rev. 1.00 116 st 1 01 Rev. 1.00 11 st 1 01



Package Information

Note that thepackage informationprovidedhere is for consultationpurposesonly.As thisinformationmaybeupdatedatregularintervalsusersareremindedtoconsulttheHoltekwebsiteforthelatestversionofthePackage/CartonInformation.

Additionalsupplementaryinformationwithregardtopackagingislistedbelow.Clickontherelevantsectiontobetransferredtotherelevantwebsitepage.

• PackageInformation(includeOutlineDimensions,ProductTapeandReelSpecifications)

• TheOperationInstructionofPackingMaterials

• Cartoninformation

http://www.holtek.com/en/

http://www.holtek.com/en/package_carton_information

Rev. 1.00 118 st 1 01 Rev. 1.00 119 st 1 01



16-pin NSOP (150mil) Outline Dimensions

SymbolDimensions in inch

Min. Nom. Max. — 0.36 BSC —B — 0.14 BSC —C 0.01 — 0.00C’ — 0.390 BSC —D — — 0.069E — 0.00 BSC —F 0.004 — 0.010G 0.016 — 0.00H 0.004 — 0.010α 0° — 8°

SymbolDimensions in mm

Min. Nom. Max. — 6.00 BSC —B — 3.90 BSC —C 0.31 — 0.1C’ — 9.90 BSC —D — — 1.E — 1. BSC —F 0.10 — 0.G 0.40 — 1.H 0.10 — 0.α 0° — 8°

Rev. 1.00 118 st 1 01 Rev. 1.00 119 st 1 01



20-pin SSOP (150mil) Outline Dimensions

SymbolDimensions in inch

Min. Nom. Max. — 0.36 BSC —B — 0.14 BSC —C 0.008 — 0.01 C’ — 0.341 BSC —D — — 0.069E — 0.0 BSC —F 0.004 — 0.010 G 0.016 — 0.00 H 0.004 — 0.010 α 0° — 8°

SymbolDimensions in mm

Min. Nom. Max. — 6.00 BSC —B — 3.90 BSC —C 0.0 — 0.30 C’ — 8.66 BSC —D — — 1. E — 0.63 BSC —F 0.10 — 0. G 0.41 — 1. H 0.10 — 0. α 0° — 8°

Rev. 1.00 10 st 1 01 Rev. 1.00 PB st 1 01



Copyriht© 01 by HOLTEK SEMICONDUCTOR INC.

The information appearin in this Data Sheet is believed to be accrate at the time of pblication. However Holtek assmes no responsibility arisin from the se of the specifications described. The applications mentioned herein are used solely for the prpose of illstration and Holtek makes no warranty or representation that sch applications will be sitable withot frther modification nor recommends the se of its prodcts for application that may present a risk to hman life de to malfnction or otherwise. Holtek's prodcts are not athorized for se as critical components in life spport devices or systems. Holtek reserves the riht to alter its products without prior notification. For the most up-to-date information, please visit or web site at http://www.holtek.com.tw.

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