the future of nanoelectronics by scaling of cmos …the future of nanoelectronics by scaling of cmos...

S.Deleonibus LETI February 2011 1

2010

© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA

2008

The future of Nanoelectronics by Scaling of CMOSand Functional Diversification

S.Deleonibus,

CEA-LETI, MINATEC, CEA-Grenoble 17 rue des Martyrs 38054 Grenoble Cedex 09 France.

Tel : 33 (0)4 38 78 59 73 ; Fax: 33 (0)4 38 78 51 8 3; email: [email protected]

26th Workshop and IEEE EDS Mini-colloquiumon NAnometer CMOS Technology (WIMNACT 26)

Yokohama, February 9, 2011


2010


Since 2005: A complete set of research platforms…

interacting daily with R & D platforms worldwide (ST Crolles, IBM Albany, …)

CEA LETI (1600 CEA researchers)collaborating

in MINATEC campus (3000 researchers)

300mmCMOS Integration

& adv. modules

200mm‘CMOS’ new concepts

& Beyond CMOS

More Than Moore200mm

NanoscaleCharacterization

Design

MicroTechsfor bio

Education

Incubation

Advanced Research100-200mm


2010


Outline

• Introduction : Trends and Hot Topics in Nanoelectronics

• Nanoelectronics scaling and use of the 3rddimension to continue Moore’s law.

• Interfacing the Multiphysics World (More Than Moore) thanks to functional diversification

•Building new systems and their packaging with a 3D tool box at a wafer level.

• Conclusions


2010


Semiconductor Market applications successive waves

Source : Semico Research Corp. May 2004 IPI Report

Quality of life, Social, Environment, Health, Energy, …associated to ICT


2010


• Currently, 3 % of the world-wide energy is consumed b y the ICT infrastructure – which causes about 2 % of the world-wide CO2 emissions– comparable to the world-wide CO2 emissions by airplanes or ¼

of the world-wide CO2 emissions by cars• ICT: 10% of electrical energy in industrialized nation s

– 900 Bill.. kWh / year = Central and South Americas• The transmitted data volume increases approximately b y a

factor of 10 every 5 years

Source: TU Dresden

Ecological Footprint of ICTs reported by Intergovernmental Panel Climate Change(IPCC)

For ICTs, keep in mind: P = Pstat + Pdyn Pstat= VddxIoff and Pdyn=CVdd

2 f


2010


Scaling: a success story…thanks to innovation

1,00E+00

1,00E+01

1,00E+02

1,00E+03

1,00E+04

1,00E+05

1,00E+06

1,00E+07

1,00E+08

1,00E+09

1,00E+10

1958 1963 1968 1973 1978 1983 1988 1993 1998 2003 2008 2013 2018

Date

Num

ber

oftr

ansi

stor

s pe

rch

ip

100µm

10µm

1µm

0,10µm

10 nm

Crit

ica

lDim

ensi

on

4004

8080

808680286

i386

i486Pentium

Pentium II

Pentium III

Pentium IV

Itanium

1k4k

16k

64k

256k

1M4M

16M

64M128M

256M512M

1G2G

4G

microp

roce

ssors

dynam

icmem

ories

(DRAM

)

contacts « plugs »(3 lev met)

vias « plugs »,CMP(4 lev met)

FSG(6 lev met)

damascene(5 lev met)

Cu (7 lev met)

Cu+H(M)SQ (9 lev met)

polymers+ALD (10 lev met)

ULK(11 lev met)

poly gate

polycide

1 billionOffice

PC

Main Frame

C.T.V.

VCRDefense

Home PC

Portable Internet

Convergence

10 millions

STI, salicide

DigitalCamera

HiK +metal gate

1,00E+00

1,00E+01

1,00E+02

1,00E+03

1,00E+04

1,00E+05

1,00E+06

1,00E+07

1,00E+08

1,00E+09

1,00E+10

1958 1963 1968 1973 1978 1983 1988 1993 1998 2003 2008 2013 2018

Date

Num

ber

oftr

ansi

stor

s pe

rch

ip

100µm

10µm

1µm

0,10µm

10 nm

Crit

ica

lDim

ensi

on

4004

8080

808680286

i386

i486Pentium

Pentium II

Pentium III

Pentium IV

Itanium

1k4k

16k

64k

256k

1M4M

16M

64M128M

256M512M

1G2G

4G

microp

roce

ssors

dynam

icmem

ories

(DRAM

)

contacts « plugs »(3 lev met)

vias « plugs »,CMP(4 lev met)

FSG(6 lev met)

damascene(5 lev met)

Cu (7 lev met)

Cu+H(M)SQ (9 lev met)

polymers+ALD (10 lev met)

ULK(11 lev met)

poly gate

polycide

1 billionOffice

PC

Main Frame

C.T.V.

VCRDefense

Home PC

Portable Internet

Convergence

10 millions

STI, salicide

DigitalCamera

HiK +metal gate

Moore’s law: 2Xdevices/year

Electronic Device Architectures for the Nano-CMOS EraFrom Ultimate CMOS Scaling to Beyond CMOS DevicesEditor: S.Deleonibus, Pan Stanford Publishing, Oct 2008


2010


Hot Topics: parasitic effects in MOSFET technology

• Introduction of HiK and metal gate allows continued scaling and relaxes SiO2 gate leakage current related issues - Ig added to SCE, DIBL, subthreshold leakage(LETI IEDM 2002, Intel IEDM 2005)

• Statistical dopant variability- number of dopants in the active area decreases with scaling

- random distribution of channel dopants

Poisson’s law. Standard deviation:

S.Deleonibus et al. ESSDERC 1999

Major interest for LowDoped channels

21

=Volume

Ndopingσ

0.01

0.1

1

10

100

1000

104

0.01 0.1 1

σσ σσ N/N

Nom

bre

d'im

pure

tés

Lg (µm)

Statistical fluctuations of threshold voltage: 150 mV decayfor VT=200mV( Lg=25nm) !!


2010


Outline





• Conclusions


2010


32nm Low Power FDSOIUndoped channels

C.Fenouillet Beranger et al., IEDM 2007, VLSI Symp 2010

V.Barral et al., IEDM2007

VDD=1V Ioff=6pA/µm

0.248µm2 SNM (1.2V)=140mV 0.179µm2 SNM (1.2V)=230mV

6T SRAM

10 nm BOx8 nm TSi 10 nm BOx8 nm TSi

Range = ±4 Å!

0000

+5+5+5+5

----5555

1 9 17

25

33

41

49

57

65

73

81

89

97

105

113

121

129

137

Wafer #

-10

-5

0

5

10

SO

I Thi

ckne

ssD

evia

tion

to ta

rget

(Å

)SOI Thickness

Max

Mean

Min

XUT+/- 5 Å - SOI thickness deviation

1 9 17

25

33

41

49

57

65

73

81

89

97

105

113

121

129

137

Wafer #

-10

-5

0

5

10

SO

I Thi

ckne

ssD

evia

tion

to ta

rget

(Å

)SOI Thickness

Max

Mean

Min

XUT+/- 5 Å - SOI thickness deviation

300mm wafers


2010


0.5

1

1.5

2

2.5

3

10 20 30 40 50 60

AV

t (m

V.u

m)

Gate length L (nm)

FinFETs

Planar FDSOI

Wfin

=10nm

UTBSOILETI

square : Vd=50mV

circle : Vd=1V

Wfin

=20nm

Wfin

=15nmW

fin=20nm

[14]

[13]

[1]

[12]

[13]

[15]

[15]

[16]

0

20

40

60

80

100

120

-105 -8

7-6

9-5

1-3

3-1

5 0 15 33 51 69 87 105

σ∆Vt=34.5mV

σVt=24.5mV

AVt=0.95mV.µm

Cou

nt

Vt shift ∆Vt (mV)

0

20

40

60

80

100

120

-105 -8

7-6

9-5

1-3

3-1

5 0 15 33 51 69 87 105

σ∆Vt=34.5mV

σVt=24.5mV

AVt=0.95mV.µm

Cou

nt

Vt shift ∆Vt (mV)

Best trade-off between VT variations and gate length scaling compared to bulk MOSFETs and FinFETs

L=25nmW=60nm

(σVt=σ∆Vt/√2 to compare measurements on pairs and on arrays of transistors in the literature)

O.WeberO.WeberO.WeberO.Weber et al., IEDM 2008et al., IEDM 2008et al., IEDM 2008et al., IEDM 2008WL

AVtVt =σ

Record -high V T matching performance FDSOI Undoped channels vs.FinFET


2010


Multi VT solutions for SOC design UTBOX + Back bias ; Gate stack engineering

0

0,1

0,2

0,3

0,4

0,5

0,6

0,7

0,8

0,9

0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9

VTP (V)

VTN

(V)

HfO2/TiN

HfO2/Al 203/TiN

HfO2/Al203+/TiN

HfSiON/TiN5

HfSiON/Al 203+/TiN

HfSiON/TaAlN/TaN

HfSiON/TaN/TaAlN

HfSiON/TiN10

HfSiON/TiN

VT tuning by gate stack engineering

F.Andrieu et al. , VLSI 2010 Honolulu O.Faynot et al., IEDM 2010 San Francisco, invited talk

BOX = 10nm and VBB/ Ground PlaneN and PMOS: VT modulation of ≤200mV


2010


Merits of FDSOI

Reachable Scaling rules(TSi, TBOx)

Delay vs. Power x Delay22% improvement/bulk (20nm)

O.Faynot et al, IEDM 2010, invited talk

L.Clavelier et al, IEDM 2010, invited talk


2010


Thin Films Devices Relaxing optimization scaling rule by architecture

TSi= ¼ Lg

TSi= 1 to 2 Lg

Planar Double-gate

Planar or Finfet

Trigate/nanowire

tsource

Gate

tsource

Gate

Gate source

t

Gate

SourceL

w

ThinSOI

Bulk or thick SOI

TSi= ½ Lg

w

TSi=2.5nmStrain global & local

Lg=10nm

Barral et al. IEDM2007

Andrieu et al VLSI2006

Bernard et al. VLSI 2008

Dupré et al. IEDM 2008

Ernst et al. IEDM 2008

Jahan et al. VLSI2005

Vinet et al. EDL 2005

4.8 nm

3.4 nm

4.8 nm

3.4 nm


2010


Si/Si0.8Ge0.2superlatticeepitaxy on SOI

Anisotropicetchingof these layers

Isotropicetchingof SiGe or Si

HfO2 (3nm)TiN (10nm)Poly-Si (200nm)

Gate depositions

S/D implantationSpacer formationActivation annealSalicidation

BOX

SiSiGe

SiSiGe

SiSiGeSiN

BOX BOX BOX

Gate

BOX

Gate

Gate etching

StandardBack-Endof-LineProcesses

500 nm

Source Drain

Gate

Top view of our device

Nanowires

Device fabrication


2010


0

1

2

3

4

5

6

0 1 2Layout width (a.u.)

Con

duct

ance

(a.

u.)

1 nanowire

planar

0

1

2

3

4

5

6


Con

duct

ance

(a.

u.)

1 nanowire

3 nanowires

0

1

2

3

4

5

6


Con

duct

ance

(a.

u.)

Finfet

Tunable width

See for details:T. Ernst et al, IEDM’06,’08 SSDM’07, ICIDT’08E. Bernard et al. VLSI’08, ESSDER’07C. Dupré et al, IEEE SOI Conference 07

Layout width1 2

vvv

0

1

2

3

4

5

6


Con

duct

ance

(a.

u.)

3 multichannels(MC)

W W

pitch

Design flexibility to tune the conductance


2010


Stacked Multichannels and MultiNanowires« Top-Down » approach

LETI: Dupré et al. IEDM 2008, San Francisco(CA)Ernst et al., Invited talk IEDM 2008, San Francisco( CA) Bernard et al, VLSI Symposium 2008 Honolulu K.Tachi et al., IEDM 2010, San Francisco

LETI top down approach for Low Power and High performance

10-12

10-10

10-8

10-6

10-4

10-2

-2 -1.5 -1 -0.5 0 0.5 1 1.5 2D

rain

Cur

rent

ID (

A/µ

m)

Gate Voltage VG (V)

VD=1.2VV

D=1.2V

NWFET

P N

VD=50mV

ION

=6.5mA/µm

IOFF

=27nA/µm

SS=68mV/decDIBL=15mV/VV

T=0.5V

C.E.T.=1.8nm

VD=50mV

ION

=3.3mA/µm

IOFF

=0.5nA/µm

SS=65mV/decDIBL=7mV/VV

T=-0.62V

-CV/I outperforms Planar in loaded environment-Improved voltage gain (8GHz) wrt Planar-Gate separation possible


2010


Pervasion of Nanowire technology

20nm

Poly SiSiO2Si3N4SiO2

3D NAND Flash Memories

Q=870 resonatorGauge width = 80 nm

15 nm oscillator

Zeptogram mass resolution

Mass detection

60

70

80

90

100

110

120

130

0 2000 4000 6000 8000 10000 12000

Time (s)

Con

duct

ance

(nS

)

pH 7

pH 4pH 5

pH 6

pH 3

pH 2

60

70

80

90

100

110

120

130

0 2000 4000 6000 8000 10000 12000

Time (s)

Con

duct

ance

(nS

)

pH 7

pH 4pH 5

pH 6

pH 3

pH 2

Metaln-doped Si Hole ElectronPassivation

Buffer solutionat pH<7

Buffer solutionat 7<pH<10

Buffer solutionat pH>10

Metaln-doped Si Hole ElectronPassivation

Buffer solutionat pH<7

Buffer solutionat 7<pH<10

Buffer solutionat pH>10

T.Ernst et al., IEDM 2008 Hubert et al., IEDM 2009

Chemical sensing


2010


CoCo--Integrating Heterogeneous orientation or materialsIntegrating Heterogeneous orientation or materials3D sequential process3D sequential process

(100)

First First heterogeneousheterogeneous orientation in 3D Si orientation in 3D Si sequentialsequential integrationintegrationEnabledEnabled by use of wafer by use of wafer bondingbonding by by keepingkeeping lowlow thermal budgetthermal budget

(110)

0.0 0.2 0.4 0.6 0.8 1.00

50

100pMOS

Reference TiN/ HfO2/ Si (100)

TiN/HfO2/Si(110) <100>

µe

ff,

ho

le (

cm

2/

V.s

)

Eeff (MV/cm)

P.Batude et al., Best student Paper Award, IEDM 2009

Ge

-4T SRAM - cold end process(bonding). Opportunities for other SC(Ge,III-V,...) - improved layout (40% area SRAM cell) -dynamically controlled VT:

improved RNM and SNM


2010


~ 1 node gain with same design rules for Front end levels

topGeOI pMOS

2µm

nMOSGate

nMOSSource

pMOSGate

pMOSSource

bottomSOI nMOS

topGeOI pMOS

2µm

nMOSGate

nMOSSource

pMOSGate

pMOSSource

bottomSOI nMOS

Y-H. Son et al, VLSI 07, Jung et al, IEDM 2006

� Nanoelectronics & Photonicsapplications withSi-Ge Co-integration

�SRAM on top SOI logic, I/Os, analogon bottom bulk

�…

� SRAMs � FLASH

Sequential 3D: Potential and Demonstrated Applicati onsSequential 3D: Potential and Demonstrated Applicati ons

High density logic applicationsHigh density logic applications Highly miniaturized Highly miniaturized CMOS imagers pixelsCMOS imagers pixels

Heterogeneous integrationHeterogeneous integration 3D memories3D memories

P. Coudrain et al, IEDM 08,

P. Batude et al,VLSI09

P.Batude et al., IEDM 2009, Best Student Paper Award


2010


Logic + Stacked NVM: High bandwith, Reduced Power consumption,…Reconfigurabilityex: 32 nm node : > 1TB/s per 1mm2

Resistive switchesToshiba, Stanford Univ.: K.Abe et al, ICICDT 2008

3D-Xbar Memory stacked on Logic: towards NV Logic

proven in 2D withMagnetic Tunnel Junctions, FeRAM TohokuUniv., Hitachi: S.Matsunaga et al., Appl.Phys.Express(2008);

ROHM


2010


More Moore

More thanMoore

Dual channel

xsSOI(N)/ Ge(P)

Advanced Devices and Systems Future Vision

UTBOX

22nm 16nm <11nm

sSOI

2010 20132009 2014 2016

FDSOI

11nm

Std SOI

HP options

Nanowire

3D Nanowires

3D stacked devices3D

Logic

2012 2015

3D

Year of transfer to Industry Development

III-V/Ge Heat sink C

Car

bon

elec

tron

ics(

Gra

phen

e, D

iam

ond)

Memory storing (SRAM, NVM) -

ZDRAM

3D stacked Mixed functions: NV Logic +sensors/polymers

X bar

3D Sensing/Actuation Bio, Mechanical & Chemical –(functionalization, NEMS, Single electronics, RF, opto,… )

Diversified Logic(association to Memory, Passives, Sensors,…)

Beyond CMOS (e-wavesconfinement, Spin electronics)

Si

FeFe

Si

FeFe


2010


Outline





• Conclusions


2010


« More, More than, Beyond Moore »Tomorrow’s top added value markets

ITRS 2009

High growth with ‘More than Moore’ technologies:they require expertise in all technical domains and in-

depth knowledge of the targeted markets


2010


NEMS scaling laws: is it worth?

k3 [rough estimate]energy consumption

k-4mass responsivity

k-1resonant frequency

kstiffness

k3mass

Scaling ruleParameter

twlM eff ⋅⋅∝

3

3

l

tweff ⋅∝κ

20 l

t

Mf

eff

eff ∝∝κ

effeff M

f

M

f

200 −=

∂∂=ℜ

2

21

MaxeffP xE ⋅≈ κ

txMax ∝and

- resolution increases- sensitivity decreases (SBR,SNR) => arrays, actuation,…- figures of merit pressure and vacuum quality dependent

( )20/10 DReff

Q

Mm −⋅=δ

SNRP

SDR

act

noise 1=∝ ∑

ML Roukes et. al. APL (2005)


2010


Nanowire used for mass detection

- First 200 mm wafers with 3.5 millions NEMS - Same process as MultiNanowires CMOS NWFET

Capacitive actuation & detection Capacitive actuation & piezo-resistive detection with nanowires

Thermo-elastic actuation & piezo-resistive detection.

15 nm oscillator

Hzzgm /5.0≈δ

Q=870 resonatorGauge width = 80 nm

LETI: T.Ernst et al., IEDM 2008, Invited talkL. Duraffourg et. al, APL 92, 174106 (2008)

E Mille et al, Nanotechnology, 165504, (2010)

NEMS array


2010


NEMS switch

from AB. Kaul et al., Nano Letters 6(5) 942-947 (2006)

“high” speed

rf

from Q.Li et al.,IEEE Nano 6(2) 256-262 (2007)

bistable

memory

high on/offlow power

logic

from D. Tsamados et al. Solid-State Elec. 52 1374 (2008)


2010


Outline





• Conclusions


2010


System On Wafer.

Heterogenous Integration On Silicon

80 µm diameter TSV imagers packaging

1 µm diameter High AR TSV stacked ICs

12µm1µm

Si

Si

12µm1µm

Si

Si

Si

Si

Cu

SiO2

Si

Si

Cu

SiO2

Si

Si

Cu

SiO2

Si

Si

Cu

SiO2

Copper/Copper bonding

Oxide/Oxide bonding

Wafer level packaged MEMS

Packaging is taken into accountat the 3D wafer level

Via belt technology

MEMS + IC stack

Ultra flat 3D

Chip stacking(TSV)

Active Silicon interposer


2010

© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEAImage-on-Board

Active Silicon interposer

Die to Die Copper pillars

Die to substrate

copper pillars

Thinned wafer (~100 µm)

Diam 60µmThick 120 µm

Via Last TSV (Aspect Ratio 2-3)

3D Integration: from imagers to advanced 3D ICs3D Integration: from imagers to advanced 3D ICs3D Integration: from imagers to advanced 3D ICs3D Integration: from imagers to advanced 3D ICs

Memory, Processors, Memory, Processors, Memory, Processors, Memory, Processors, ImagersImagersImagersImagers

withwithwithwith highhighhighhigh densitydensitydensitydensity TSV, NEMSTSV, NEMSTSV, NEMSTSV, NEMS…………

3D-IC

Metal1

ØTSV~3µm Thin Si~15µm

ØTSV~3µm Thin Si~15µm

3D highdensity

withTSV

2001

2008

VGA cameras (300kpixels)

withTSV

2001

2008

2001

2008

VGA cameras (300kpixels)

ST ST ST ST –––– LETI collaborationLETI collaborationLETI collaborationLETI collaboration Stack structure

170µm

30µm

120µm

80µm

400µm

Pitch 120µm

Pitch 50µm

Stack structure

170µm

30µm

120µm

80µm

400µm

Pitch 120µm

Pitch 50µm

Mixed Signal Digital/Analog ST ST ST ST –––– LETI collaborationLETI collaborationLETI collaborationLETI collaboration


2010


By courtesy: D43D Workshop - 3D Integration program – P. Ancey Lausanne – 2010, May 27th-28th

Digital

Analog

Stack structure

170µm

30µm

120µm

80µm

400µm

Pitch 120µm

Pitch 50µm

Stack structure

170µm

30µm

120µm

80µm

400µm

Pitch 120µm

Pitch 50µm

Mixed Signal Digital/Analog

Stack structure

170µm

30µm

120µm

80µm

400µm

Pitch 120µm

Pitch 50µm

Stack structure

170µm

30µm

120µm

80µm

400µm

Pitch 120µm

Pitch 50µm

Mixed Signal Digital/Analog

•1056 inter-chip connections•588 TSV’s•482 bumps •In BGA 864 lead free balls, 1.0 mm pitch


2010


3D Roadmap : Overview of architectures

1101E21E31E41E51E61E71E81E9

Vertical 3D via pitch (µm)

Vertical Interconnect D

ensity (cm-2)

Flip chip solder bump min pitch

ITRS C65nm M1 min pitch

ITRS C65nm min Global metal pitch

Multi-level 3D IC(CPU + cache + DRAM + Analog + RF + sensor + IO)

3D Stacked memory (NAND, DRAM, …)

0.11101001000

2007 2009 2012 >2014

100% filled via

Vertical device on CMOS (NTC, NW, NEMS)

Low density 3D via Chip-level bonding

Logic ( multicore processor with cache memory)

Image Sensor

Digital Signal Processor

Via size=50µm

Via size=5-30µm

Via size=<5µmCPU

Cache memory

Via size=<2µmCPU

Cache Memory

DRAM / NVM

Analog

RF Power

Sensor I/O

Sensor I/O

High density 3D via wafer-level bonding

CMOS Image sensor (Sensor + DSP + RAM)

Targets for MEDEA+ project

65n

m

45n

m

32n

m

ITRS

Optical Interconnects

InP/SOI µ-laser1.6µm 0.5mA

Gephotodetector

Cross talks:-delay, matching, -power dissipation(global temp. increase, hot spots, reliability, …)


2010


Conclusion :Nanoelectronics CMOS from Devices to Systems Perspectives

• Si CMOS: Nanoelectronics Base platform beyond ITRS• Durable Low Power solutions:

health, environment, quality of life, energy, IST,…• Low Power consumption: major challenge (sub 1V VDD CMOS ).

=> Device/ system architecture optimization: Thin Films Gate All Around nanowires, low slopes,layout , 3D=> Opportunities for new materials on Silicon(Ge, revised low BG III-V, Carbon,…)

• Heterogeneous 3D co-Integration on Si, Low Power: Monolithic/Sequential 3rd dimension in device. New a ctive materialsReconfigurabilty with NVM ; NV LogicSystem On Wafer: 2 to 3D heterogeneity functions & ch ips


2010


2006

Thank you for your attention

AcknowledgementsProfessors H.Iwai(TokyoTech) and WIMNACT 26 organizersCEA LETI Co-workers - Silicon Technologies DivisionsM.Aid, F.Andrieu, J.Buckley, M.Brillouet, B. de Salvo, L.Duraffourg, T.Ernst, O.Faynot, P.Leduc, C.Le Royer, G.Molas,T.Poiroux, G.Poupon, P.Robert, M.Scannell, N.Sillon, M.Vinet, O.Weber


2010


Electronic Device Architectures for the Nano-CMOS Era

From Ultimate CMOS Scaling to Beyond CMOS Devicesedited by Simon Deleonibus (CEA-LETI, France) Cloth July 2008 978-981-4241-28-1

� Discusses the scaling limits of CMOS, the leverage brought by new materials, processes and device architectures (HiK and metal gate, SOI, GeOI, Multigate transistors, and others), the fundamental physical limits of switching based on electronic devices and new applications based on few electrons operation

�Weighs the limits of copper interconnects against the challenges of implementation of optical interconnects

� Reviews different memory architecture opportunities through the strong low-power requirement of mobile nomadic systems, due to the increasing role of these devices in future circuits

� Discusses new paths added to CMOS architectures based on single-electron transistors, molecular devices, carbon nanotubes, and spin electronic FETs

Available at Amazon.com or any good bookstores.

the future of nanoelectronics by scaling of cmos …the future of nanoelectronics by scaling of cmos...

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