1 introduction to cmos technology c. fenouillet-beranger soi devices engineer, cea/leti &...
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1
Introduction to CMOS TechnologyIntroduction to CMOS TechnologyIntroduction to CMOS TechnologyIntroduction to CMOS Technology
C. Fenouillet-Beranger
SOI Devices Engineer, CEA/LETI & STMicroelectronics, Crolles
2C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
OutlineOutline MOSFET Basics
– Ideal MOSFET physics– Main parameters : threshold, leakage and speed– What MOSFET for what application ?– Scaling theory and good design rules of CMOS Devices
The Real World– Threshold voltage control limitations– Gate oxide leakage and capacitance scaling
Technological Solution ?– Gate alternative : High-K and Metal Gate– Channel engineering : Strained-Si– Alternative devices and substrates– Basic logic functions
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MOSFET BasicsMOSFET Basics
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CMOS technology applicationsCMOS technology applications
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Different scales inside a chipDifferent scales inside a chip
2x2 cm²
10x10 mm²
4x4 µm²
500x500 nm²
Silicon channel
NiSiNiSi
Source Drain
Gate
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Making a Switch with Metal, Oxide and SiliconMaking a Switch with Metal, Oxide and Silicon
Energy Barrier
x
Carrier reservoirSourceSource
DrainDrain
E
Energy Barrier
x
Carrier reservoirSourceSource
DrainDrain
MetalMetalOxideOxide
Si (p)Si (p)nn++ nn++
0
Vg
= S D
C
Silicon channel
NiSiNiSi
Source Drain
Gate
Silicon channel
NiSiNiSi
Source Drain
Gate
Vd
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What is an ideal MOS Transistor ?What is an ideal MOS Transistor ?
VS=0V VD>0V
VG=0V
S D
G+ + + + + +
- - - - - - - VS=0V VD>0V
VG>0V
S D
G
IDSCanal vide : courant nul Canal rempli : courant non nul
A BTMOS bloqué TMOS passant
OFF-STATE ON-STATE
A MOS capacitor is modulating the transport between two carrier reservoir
MOS capacitance : Field Effect MOSFETMOSFET
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n-type & p-type MOSFETsn-type & p-type MOSFETs
nMOSFETnMOSFETElectron conductionElectron conduction
pMOSFETpMOSFETHole conductionHole conduction
MetalMetalOxideOxide
0
Vg<0
pp++ pp++Si (n)Si (n)
Vd<0
MetalMetalOxideOxide
Si (p)Si (p)nn++ nn++
0
Vg>0
Vd>0
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SiSi
MOSFET morphologyMOSFET morphology
STI STI
W
Contact drainContact source
Contact grille
Zone Active de Si
DrainSource
Gate (Poly-Si)Gate (Poly-Si)
SourceSource DrainDrain
Métal
Oxyde
Semi-conducteur
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Basic Physics of MOSFETBasic Physics of MOSFET
Vgate
Log(Idrain)Ideal switch
Threshold (Vth)
ON state Current
OFF state Current
MOSFET switch
OFF State Current (Thermal)
3 main parameters3 main parameters
1.1. Threshold VoltageThreshold Voltage2.2. Ion (=speed)Ion (=speed)3.3. Ioff (=stand-by power)Ioff (=stand-by power)
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MOSFET PhysicsMOSFET Physics
L
WS/CWD/C
source drain
grille
canal
BCN
P
d--- -- - N--- -- -
VG=0
VDVS
VB
LTox
« Off State»
N P N+ + + +--- ---
nMOSFET L
WS/CWD/C
source drain
gate
channel
BC
P
NVD
N -- --- - - - -
-- -
VG=VD
VDVS
VB
LTox
N P N--- - - ---
+ + + + +
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Threshold Voltage (VThreshold Voltage (Vthth))
Fox
depFBth C
QVV 2
L
WS/CWD/C
source drain
gate
channel
BC
P
NVD
N -- --- - - - -
-- -
Gate Material
Oxide Thickness
Channel Doping
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On State Current (IOn State Current (Ionon))
Lgate
SourceSource DrainDrain
GateGatet
QI inv
DS
DSDS
thGoxeDS VV
VVL
WCµI
2
L
Eµv eL
VE DS
DSeVµ
Lt
2
WLV
VVCWLQQQ DSthGox
Dinv
Sinvinv
22
1
Vg-Vth Vg-Vth-VDS
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Off – State Current (IOff – State Current (Ioffoff))
- - -- - -
VD>0
VG1<Vth
- - -- - -
VD>0
VG1<VG2<Vth
Ithermique Idiffusion Ithermique Idiffusion
kT
Vq
S
VII DSGT
thDS exp110lnexp
S
VII th
thoff )log()log(
Modulation of barrier heigth by Capacitive coupling1/S
Vth
Log Idrain
Vgate
+ dec Ioff
S should be as small as possible
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The Static Leakage ComponentsThe Static Leakage Components
i) Gate leakage (oxide thickness dependance)
iii) Junction leakage (doping dependance)
ii) Channel Leakage (Vth and S dependant)
Ioff = IS + IG + IB
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Different Applications : Some typical numbersDifferent Applications : Some typical numbers
0.001
0.01
0.1
1
10
100
0 500 1000 1500
Ion (µA/µm)
Ioff
(n
A/µ
m)
High Performance
Digital Consumer
Wireless
Operation SpeedOperation Speed
Po
wer D
issipatio
nP
ow
er Dissip
ation
Computers
Mobile
Phones
Hifi – TV
Low Vth
High Vth
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CMOS ScalingCMOS Scaling
CMOS090
CMOS065
CMOS045
CMOS032
CMOS120
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Gordon Moore, a co-founder of Intel said in 1965:“Component count per unit area doubles every two years”
- Last 40 years : technological advances achieved mainly by reducingtransistors size
- However current trend of miniaturization causes undesired effects degrading the electrical parameters and transistor performance
Scaling Theory: Moore’s law Scaling Theory: Moore’s law
In reality:• µ decreases • Tox levels-off• Off current increases as transistor size is reduced
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Ideal MOSFET Basics summary Ideal MOSFET Basics summary
Source Drain
Gate Electrode
Source Drain
Gate Electrode
Source Drain
Gate Electrode
Source Drain
Gate Electrode On-State :On-State :MOS gate capacitance lowers channel barrier electrons(holes) flow from Source to Drain Ion currentCarrier transit time is Cgate*Vgate / Ion the higher Ion the faster the device
Off-State :Off-State :MOS gate capacitance potential = 0electrons(holes) flow from Source to Drain due to Thermionic current Ioff currentStatic Power dissipation is Pstat = VDS * Ioff
Threshold Voltage :Threshold Voltage :Determines the gate voltage transition Vth between Off-state and On-state regimesVth depends (at the 1st order) on the channel doping and gate electrode material
Log(IDS)
VGS
Low Vth
High VthLog(IDS)
VGS
Low Vth
High Vth
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Part 2.Part 2.
The Real WorldThe Real World
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VVthth Control : Short Channel Effects Control : Short Channel Effects
Zone de charge d’espace ZCE
L
BC
SCE=Short Channel Effect
SCEDIBL
DIBL=Drain Induced Barrier Lowering
VDS
Vth
Log Idrain
Vgate
SCE
Vth1
DIBL
Vth2
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MOSFET Typical Lenghts and RatiosMOSFET Typical Lenghts and Ratios
Lgate,phys
draingate
Tdep
source
Lel
Xj
Tox
; ; 3
1
el
j3040
1
el
ox
L
T 3
1
el
dep
L
T
L
X 5
1
dd
th
V
V
jphysgateel XLL 8.0,
SBdB
Sidep V
qNT
2
Good design rules of MOSFET architecture :
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dsel
dep
el
ox
el
j
ox
Si VL
T
L
T
L
XDIBL
2
2
1
biel
dep
el
ox
el
j
ox
SiV
L
T
L
T
L
XSCE
2
2
1
0.8
0.8
dsatgoxeffdsat V(VLel
WelCI 21 -Vth)
T. Skotnicki et al. IEEE EDL, March’88 & IEDM’1994
Scaling rules (MASTAR Model)Scaling rules (MASTAR Model)
VTH(short Mosfet)=VTH(long)-SCE-DIBL
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Why is it so difficult to get a « Good Scaling » ?Why is it so difficult to get a « Good Scaling » ?
Lgate,phys
draingate
Tdep
source
Lel
Xj
3
1el
j
L
X
3
1el
j
L
X
3040
1el
ox
L
T
3040
1el
ox
L
T
3
1el
dep
L
T
3
1el
dep
L
T
5
1dd
th
V
V
5
1dd
th
V
V
Oxide Scaling Junction Scaling
Subthreshold controlDoping increase
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TToxox/L/Lelel ratio : Gate Oxide Scaling ratio : Gate Oxide Scaling
Lgate,phys
drainPoly-Si
gate
Tdep
source
Lel
Xj
zz
zz
Tox
BC
BV
SiliciumSiliciumOxydeOxydePolyPoly--SiliciumSiliciumTox
BC
BV
SiliciumSiliciumOxydeOxydePolyPoly--SiliciumSiliciumTox
BC
BV
SiliciumSiliciumOxydeOxydePolyPoly--SiliciumSilicium
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The Gate-Poly Silicon DepletionThe Gate-Poly Silicon Depletion
poly
pSipolydep qN
T2
2
2
242
FFBG
ppp VV
kk
ox
pSip C
Nqk
2
Ref.: E. Josse et al., IEDM’99
N+ P+
Tdeppoly = 0.4nm 0.6nm
02468
101214161820
0 10 20 30 40CMOS relevant Tox , A
NMOS ( Npoly =1e20cm-3)
Tp (EOT)@1.8V1.3V1.0V0.7V0.5V0.35V0.25V
EO
T o
f p
oly
de
ple
tio
n , A
02468
101214161820
0 10 20 30 40CMOS relevant Tox , A
NMOS ( Npoly =1e20cm-3)
Tp (EOT)@1.8V1.3V1.0V0.7V0.5V0.35V0.25V
Tp (EOT)@1.8V1.3V1.0V0.7V0.5V0.35V0.25V
EO
T o
f p
oly
de
ple
tio
n , A
Vdd scaledwith Tox
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Quantization Effects in Inversion LayerQuantization Effects in Inversion Layer
3/2
4
3
2
3
3/1
*2
2
n
qF
m
nE
C-Y. Hu et al., IEEE EDL, June 1996
q
E
eloxTD
thVD
thV0
_
32
~150mV
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Impact on Good Design RuleImpact on Good Design Rule
einv
Tox
edepBC
BV
SiliciumOxydePoly-Silicium
n=0
n=1econf2
e
continuumeinv
Tox
edepBC
BV
SiliciumOxydePoly-Silicium
n=0
n=1econf2
e
continuum
qpoly
depoxea
ox TTTT
Tox,eff = Tox + 8A
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
0.18
0 50 100 150CMOS node
Tox
/L
Tox/ Lmask
Tox_el/ Lmask
Tox_el/ Lgate
Tox_el/ LelTox, Tox_el and Lmask, Lgate, Lelaccording to ITRS 2001
Good design Rule
Reality
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The problem of Gate LeakageThe problem of Gate Leakage
Poly-Si
Si
EfEvEf
Ec
Gate N+SiO2
Substrate Si P
Ec
Ev
Wpd
2A reduction in Tox ~ 1 dec increase in gate leakage
1.E-09
1.E-07
1.E-05
1.E-03
1.E-01
1.E+01
1.E+03
1.E+05
0 1 2 3Gate bias, V
Gat
e cu
rren
t, A
/cm
2
1nm
1.5nm
2nm
.5nm
3nm
3.5nm
SiO2
1.E-09
1.E-07
1.E-05
1.E-03
1.E-01
1.E+01
1.E+03
1.E+05
0 1 2 3Gate bias, V
Gat
e cu
rren
t, A
/cm
2
1nm
1.5nm
2nm
.5nm
3nm
3.5nm
SiO2
2
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Impact of Gate Leakage on CircuitsImpact of Gate Leakage on Circuits
In Static Mode, two gate leakages: IgOff & IgOn : increase of Ioff
If Tox , Ig , Power
0
10
0
Ioffcanal
Igoff
1
00
0
IgOn
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VVthth/V/Vdddd Ratio Ratio
5
1dd
th
V
V
5
1dd
th
V
VIf Vdd drops, just decrease the Vth too keep a good Ion. But …
S degrades at smaller L !
VgsVth
Log(IDS )
Ioff
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What Did We Learn ?What Did We Learn ?
Controlling VControlling Vthth ( (IIoffoff))
Increasing DopingIncreasing Doping
Scaling JonctionsScaling Jonctions
Scaling ToxScaling Tox
DarkspaceDarkspace
PolydepletionPolydepletion
Junc. Leak.Junc. Leak.
Rs increaseRs increase IIonon (speed) reduction (speed) reduction
IIoffoff (power) increase (power) increase
Higher IHigher Ioffoff
Limited ScalingLimited Scaling IIonon reduction reduction
Gate leakageGate leakage
Reducing Vdd (power)Reducing Vdd (power) IIonon reduction reduction
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Technological Boosters to recover a Technological Boosters to recover a Healthy ScalingHealthy Scaling
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What can we do to retrieve a Healthy Scaling ?What can we do to retrieve a Healthy Scaling ?
Silicon channel
NiSiNiSi
Source Drain
Gate
3040
1el
ox
L
T
3040
1el
ox
L
T
Oxide Scaling Junction Scaling
Subthreshold control Vs Overdrive
Doping increase
3
1el
dep
L
T
3
1el
dep
L
T
Less Gate LekageLess Gate LekageNo Poly DepletionNo Poly Depletion
DIBL-Free ArchitectureDIBL-Free Architecture
Low RSD for lower Xj Low RSD for lower Xj Better Contact ResistanceBetter Contact Resistance
Better Ion at the same Better Ion at the same overdriveoverdriveBetter Subthreshold Better Subthreshold SlopeSlope
5
1dd
th
V
V
5
1dd
th
V
V
3
1el
j
L
X
3
1el
j
L
X
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Mobility EnhancementMobility Enhancement
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IIonon Enhancement by materials Enhancement by materials
DSDS
thGoxeDS VV
VVL
WCµI
2
Transistor ArchitectureMaterial Properties
Carrier velocity under electric field E in the linear regime: v = µ E
µEcritical
Efield
Velocity Velocity saturation regime
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Mobility In SiliconMobility In Silicon
E
carrier, mass m*carrier, mass m*
Shockwave from lattice vibration, or impurities, or
gate oxide rugosity every seconds
Shockwave from lattice vibration, or impurities, or
gate oxide rugosity every seconds 1.1. Small m* : ligth Small m* : ligth
electrons or holeselectrons or holes
*
2
m
Ev c
2. High 2. High (less possible (less possible collision)collision)
*mqµ
Effective mass of carrierLinked to valence/conduction bands
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Who are the guys responsible for IWho are the guys responsible for Ionon ? ?
Silicon Band Structure
ml
mt
(x)100
(y) 010
(z) 001
6 equivalent types of electrons are involved in conduction regime of nMOS
2 types of holes are involved in conduction regime of pMOS : heavy and light
39C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
What happens in Strained-Si ?What happens in Strained-Si ?
*cm
q
i*c i
i
mm . ? Splitting Sub-band Carrier Redistribution
Band structuredeformation
Splitting less intervalleyphonon scattering
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Redistribution in subbands and scattering reductionRedistribution in subbands and scattering reduction
-0.3
-0.2
-0.1
0.0
0.1
0.2
E(LH-HH)
Si/Si0.5
Ge0.5
Ene
rgy
(eV
)
LH
SO
[100] [110]
HH
Strained-SiStrained-Si
< 1 % in HH
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
Si bulk
SO
LH
HH
[110][100]
Ene
rgy
(eV
)
Unstrained SiUnstrained Si
>80 % in HH
E
NFermi-Dirac
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Is Stress the Only Way to Enhance Mobility ?Is Stress the Only Way to Enhance Mobility ?
Carrier effective mass can depend on cristal direction !– For Electron iso-energy are ellipsoidal average
dependance does not depend on Si direction for standard (100) substrate (not true in other direction)
– For Hole : extremely high anisotopy of mass !!
Heavy Mass
Light Mass
Holes with the same energyCristal Direction (3D)
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Choosing the right Si-orientation for HolesChoosing the right Si-orientation for Holes
Heavy Mass along transportStandard <110> channel
Standard (100) wafer Standard (100) wafer
Light Mass along transportRotated <100> channel
45° Rotation
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Optimum Cristal OrientationsOptimum Cristal Orientations
From M.Yang et al., IEDM 2004
nMOS pMOS
Inversion layer mobility depends on the surface orientations and current flow directions For holes, mobility is 2.5x higher on (110) surface compared to standard wafer with (100)
orientation For electrons, mobility is highest on (100) substrates
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Hybrid integrationHybrid integration
[M. Yang et al.,
IEDM 2003]
To fully take advantage of the carrier mobility dependence on
surface orientation, fabrication of CMOS on hybrid substrates has
been demonstrated
The hybrid substrate is obtained using a layer transfer technique in
which the bonded wafer and the handle wafer have different crystal
orientation. An additional photo step is used to etch through the SOI
and BOX and expose the surface of the handle wafer to perform SEG
Issues : limited scalability of bulk devices and increased process
complexity
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Mobility Enhancement TechniquesMobility Enhancement Techniques
Substrate-basedSubstrate-based
BULK SSOI
SixGe1-x Based
Bulk SSOI
Tensile bi-axial stress
nMOS+pMOS
Si
SiGe box
SiGe SD
Compressive
pMOS
SiGe SEG
Process-based Induced StessProcess-based Induced Stess
Liners
CESL SMT
nMOS
Tensile
nMOS
Tensile
pMOS
Compressive
Cristal Orientation
In-plane Out of plane
Mod.Orientation Si Channel
pMOS
Natural mobility boost
Rotated substrate
Cristal Orientation
STI
SACVD
TensileBi-axial
nMOS+pMOS
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Strain and mobilityStrain and mobility
Low field mobilityLow field mobility ElectronsElectrons HolesHoles
Biaxial tensileBiaxial tensile ++ ++
Biaxial compressiveBiaxial compressive -- ++
Uniaxial tensile (along LUniaxial tensile (along Lgg)) ++ --
Uniaxial compressive (along LUniaxial compressive (along Lgg)) -- ++Uniaxial compressive
(along Lg)Biaxial tensile Uniaxial tensile
(along Lg)
[F. Payet, L2MP PhD, 2006]
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Uniaxial Stress By Stressed-LinerUniaxial Stress By Stressed-Liner
1.E-08
1.E-07
1.E-06
250 450 650 850Ion (µA/µm)
Ioff
(A/µ
m)
Strained
Unstrained
Vdd=0.9V
+15.6%
2D mecanical Simulations
Impact on nMOSFETs performances
Tension
Strained MOSFET (Lg=30nm) by
CESL
CESL Tensile
(F.Bœuf et al., IEDM 2004 , SSDM 2004)
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Hole Mobility enhancement using Rotated SubstratesHole Mobility enhancement using Rotated Substrates
45°
CurrentFlow
<110>
<100>
-9
-8.5
-8
-7.5
-7
-6.5
-6
-5.5
-5
0.4 0.6 0.8 1
Ion [a.u.]
Ioff
Lo
g[A
/µm
]
<110>
<100>
+15%
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Uniaxial Stress using SiGe S/DUniaxial Stress using SiGe S/D
Wafer #1 and #2
1.E-09
1.E-08
1.E-07
1.E-06
250 300 350 400 450 500 550 600 650 700Ion [µA/µm]
Ioff
[A/
µm
]
+20%
SiGe SD <110>Wafer #1 and #2
1.E-09
1.E-08
1.E-07
1.E-06
250 300 350 400 450 500 550 600 650 700Ion [µA/µm]
Ioff
[A/
µm
]
+20%
SiGe SD <110>
T.Korman
Courtesy, F.Payet
<110
> unst
rain
ed
+15%
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Gate Capacitance Scaling : Gate Capacitance Scaling : High-K dielectricsHigh-K dielectrics
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Figthing against Gate LeakageFigthing against Gate Leakage
EfEvEf
Ec
Gate N+SiO2
Substrate Si P
Ec
Ev
Wpd
Reducing Tunneling…Increasing Tox !But without reduction of Cox !Increasing permitivity
HIGH K materials
ox
oxox T
εC
Leakage issue
Polydepletion issueReplacing Poly-Si by Metal
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ContextContext
Down to 90nm gate length, N+ and P+ polysilicon gate was used for CMOS integration compatible with oxide or oxynitride gate dielectric.
Due to aggressive scaling of the gate dielectric, the gate leakage is becoming unacceptably high (>Ioff), requiring the use of high-k dielectric
Due to the incompatibility of polysilicon gate with high-k dielectric (Fermi pinning, large Vt, mobility degradation) and the need to boost performance (elimination of polydepletion, boron penetration,…), metal gate electrodes will likely be needed
For bulk technology, two metals with WFs close to the bandgap edges are needed (high channel doping required to control SCE).
For FDSOI or double gate devices, WFs within 250meV from midgap are preferred, requiring more complex integration
Two integration approaches are considered: gate first and gate last.
Figthing against Gate LeakageFigthing against Gate Leakage
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High-k dielectricHigh-k dielectric
C. Fenouillet et al IEDM 2007
0,00001
0,0001
0,001
0,01
0,1
1
10
100
17 19 21 23 25 27
CET (A)
J g ON (
A/C
m²)
MG/HfO2
2 Dec
FD SOI nMOS, Vg = 1.1V
2 DecPoly-Si/SiON1 Dec
MG/Hf SiON
MG/SiON
MASTAR Exp data.
High-K At an equivalent CET of SiON dielectric, the gate leakage current is reduced by more than 2 decades
For EOTs below 20Å, gate leakage current
becomes higher than off-state leakage current.
High-k dielectric
High-k (HfO2, ZrO2, Hf-based or Zr-based,
LaO2, Al2O3,… ALCVD or MOCVD deposition
Pre-deposition clean and post deposition
anneals affect the quality of high-k
Large Vt: Fermi pinning at the poly-Si/
Metal oxide interface but occurs also metal gate electrodes
Compatibility of polysilicon gate with high-k is unlikely !
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High-k Dielectric : IssuesHigh-k Dielectric : Issues Mobility degradation
- Many publications have reported mobility degradation using high-k dielectrics.
- Possible cause is coupling of soft optical phonons in high-k with inversion channel charge carrier
Vt instabilities and reliability and noise issues
Large k and large dielectric thickness result in fringing field (FIBL) and loss of control of the channel by the gate
B. Tavel et al, PhD Thesis 2002
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Gate Capacitance Scaling : Gate Capacitance Scaling : Metal GatesMetal Gates
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Choosing The « Good Metal »Choosing The « Good Metal »
Mid-gap Gate
Ec
Ev
nMOS Gatepoly-Si N+ Metal Gate « N+like »
1.1
2V
pMOS Gatepoly-Si P+
Metal Gate « P+like »
Fox
depFBth C
QVV 2
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The use of metal gate suppress:– the polysilicon depletion : a reduced CET of 3-5Å for performance
improvement– and suppress the boron penetration problem
Two approaches have been proposed: gate first or gate last
– Gate first approach requires to take care of FE contamination tool, metal etching and to the high temperature anneal
– Gate last approach (replacement gate): dummy gate removal and replacement, gate dielectric integrity has to be kept
But for some applications CMOS requires 2 different metal gates in order to separate WFs for NMOS and PMOS devices (Dual metal gate integration)
Metal gate integrationMetal gate integration
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Why is Metal Workfunction so important ? Why is Metal Workfunction so important ?
Vg
Log Id
Id
Vg
Vth,nVth,p
Ion,n
Ion,p
VddVdd
Regular Poly-gate n+/p+
Vg
Id
Vg
Vth,nVth,p
Ion,nIon,p
VddVdd
Mid-gap Metal Gate
+0.5V+0.5V
Vg
Log Id
Id
Vg
Vth,nVth,p
Ion,nIon,p
VddVdd
Dual n+/p+ Metal Gate
Log Id
+25%Polydepreduction
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Why midgap metal gate ? Why high-k ?
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
Vth
(V)
@ V
d=|0
.1V
|
Lg= 200 nm, TBOX
= 145 nm,
TSi= 8 nm, Tox = 1.9 nm
N+ like gate
P+ like gate
pFET Midgap gate
nFET Midgap gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
Vth
(V)
@ V
d=|0
.1V
|
Lg= 200 nm, T = 145 nm,
TSi
P+ like gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
Vth
(V)
@ V
d=|0
.1V
|
Lg= 200 nm, TBOX
= 145 nm,
TSi= 8 nm, Tox = 1.9 nm
P+ like gate
pFET Midgap gate
nFET Midgap gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
Vth
(V)
@ V
d=|0
.1V
|
Lg= 200 nm, T = 145 nm,
TSi
P+ like gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
Vth
(V)
@ V
d=|0
.1V
|
Lg= 200 nm, TBOX
= 145 nm,
TSi= 8 nm, Tox = 1.9 nm
N+ like gate
P+ like gate
pFET Midgap gate
nFET Midgap gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
Vth
(V)
@ V
d=|0
.1V
|
Lg= 200 nm, T = 145 nm,
TSi
P+ like gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
Vth
(V)
@ V
d=|0
.1V
|
Lg= 200 nm, TBOX
= 145 nm,
TSi= 8 nm, Tox = 1.9 nm
P+ like gate
pFET Midgap gate
nFET Midgap gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
Vth
(V)
@ V
d=|0
.1V
|
Lg= 200 nm, T = 145 nm,
TSi
P+ like gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
Vth
(V)
@ V
d=|0
.1V
|
Lg= 200 nm, TBOX
= 145 nm,
TSi= 8 nm, Tox = 1.9 nm
N+ like gate
P+ like gate
pFET Midgap gate
nFET Midgap gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
Vth
(V)
@ V
d=|0
.1V
|
Lg= 200 nm, T = 145 nm,
TSi
P+ like gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
Vth
(V)
@ V
d=|0
.1V
|
Lg= 200 nm, TBOX
= 145 nm,
TSi= 8 nm, Tox = 1.9 nm
P+ like gate
pFET Midgap gate
nFET Midgap gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
Vth
(V)
@ V
d=|0
.1V
|
Lg= 200 nm, T = 145 nm,
TSi
P+ like gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
Vth
(V)
@ V
d=|0
.1V
|
Lg= 200 nm, TBOX
= 145 nm,
TSi= 8 nm, Tox = 1.9 nm
N+ like gate
P+ like gate
pFET Midgap gate
nFET Midgap gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
Vth
(V)
@ V
d=|0
.1V
|
Lg= 200 nm, T = 145 nm,
TSi
P+ like gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
Vth
(V)
@ V
d=|0
.1V
|
Lg= 200 nm, TBOX
= 145 nm,
TSi= 8 nm, Tox = 1.9 nm
P+ like gate
pFET Midgap gate
nFET Midgap gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
Vth
(V)
@ V
d=|0
.1V
|
Lg= 200 nm, T = 145 nm,
TSi
P+ like gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
Vth
(V)
@ V
d=|0
.1V
|
Lg= 200 nm, TBOX
= 145 nm,
TSi= 8 nm, Tox = 1.9 nm
N+ like gate
P+ like gate
pFET Midgap gate
nFET Midgap gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
Vth
(V)
@ V
d=|0
.1V
|
Lg= 200 nm, T = 145 nm,
TSi
P+ like gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
Vth
(V)
@ V
d=|0
.1V
|
Lg= 200 nm, TBOX
= 145 nm,
TSi= 8 nm, Tox = 1.9 nm
P+ like gate
pFET Midgap gate
nFET Midgap gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
Vth
(V)
@ V
d=|0
.1V
|
Lg= 200 nm, T = 145 nm,
TSi
P+ like gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
Vth
(V)
@ V
d=|0
.1V
|
Lg= 200 nm, TBOX
= 145 nm,
TSi= 8 nm, Tox = 1.9 nm
N+ like gate
P+ like gate
pFET Midgap gate
nFET Midgap gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
Vth
(V)
@ V
d=|0
.1V
|
Lg= 200 nm, T = 145 nm,
TSi
P+ like gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
Vth
(V)
@ V
d=|0
.1V
|
Lg= 200 nm, TBOX
= 145 nm,
TSi= 8 nm, Tox = 1.9 nm
P+ like gate
pFET Midgap gate
nFET Midgap gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
Vth
(V)
@ V
d=|0
.1V
|
Lg= 200 nm, T = 145 nm,
TSi
P+ like gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
Vth
(V)
@ V
d=|0
.1V
|
Lg= 200 nm, TBOX
= 145 nm,
TSi= 8 nm, Tox = 1.9 nm
N+ like gate
P+ like gate
pFET Midgap gate
nFET Midgap gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
Vth
(V)
@ V
d=|0
.1V
|
Lg= 200 nm, T = 145 nm,
TSi
P+ like gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
Vth
(V)
@ V
d=|0
.1V
|
Lg= 200 nm, TBOX
= 145 nm,
TSi= 8 nm, Tox = 1.9 nm
P+ like gate
pFET Midgap gate
nFET Midgap gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
Vth
(V)
@ V
d=|0
.1V
|
Lg= 200 nm, T = 145 nm,
TSi
P+ like gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
Vth
(V)
@ V
d=|0
.1V
|
Lg= 200 nm, TBOX
= 145 nm,
TSi= 8 nm, Tox = 1.9 nm
N+ like gate
P+ like gate
pFET Midgap gate
nFET Midgap gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
Vth
(V)
@ V
d=|0
.1V
|
Lg= 200 nm, T = 145 nm,
TSi
P+ like gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
Vth
(V)
@ V
d=|0
.1V
|
Lg= 200 nm, TBOX
= 145 nm,
TSi= 8 nm, Tox = 1.9 nm
P+ like gate
pFET Midgap gate
nFET Midgap gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
Vth
(V)
@ V
d=|0
.1V
|
Lg= 200 nm, T = 145 nm,
TSi
P+ like gate
Midgap electrode with undoped channel : symmetrical Vth for NMOS and PMOS for high Vth applications
With Band edge gate electrodes (as poly-Si), FDSOI requires very high channel doping > 8e18 at/cm3 for HVT -> Variability degradation
Metal gate interest for FDSOIMetal gate interest for FDSOI
60C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Device ArchitectureDevice Architecture
61C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Bulk PD SOI
Scalability ? Scalability as BULK
Scalability much improved if GP
FD SOI
Scalability may be better or worse (GP,BOX)
FD SON
GP
Scalability very much improved
DG (Delta, FinFET, SON, Vertical,TriGate, Omega, etc., etc.
el
dep
el
ox
el
j
L
T
L
T
L
X
EI
2
2
1
1
el
dep
el
ox
el
j
L
T
L
T
L
Xx
EI
2
2
1
1
el
boxsi
el
ox
el
si
L
TT
L
T
L
T
EI
2
21
1
el
boxsi
el
ox
el
si
L
TT
L
T
L
T
EI
2
21
1
el
si
el
ox
el
si
L
T
L
T
L
T
EI
2/
4/1
5.0
2
2
XjTdep
dsd VEIDEISCE ox
si
ox
si 0.8IBL 64.0
REF.:T. Skotnicki, invited paper
ESSDERC 2000, pp. 19-33, edit. Frontier Group
Device ArchitectureDevice Architecture
62C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011
Layout and basic functionsLayout and basic functions
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Logic ApplicationsLogic Applications
Complex Function (MP4 Decoder,
µProc,Motion
Detector, TVDH …)
Layout
Layout
inverter
NAND
SRAM
Basic Functions
Layout
Silicon
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Layout of the transistorLayout of the transistor
isolationSi=ActiveSi=Active
GateGate
SourceSource DrainDrain
Gate
Source DrainMetal 1Metal 1 Metal 1Metal 1
Metal 1Metal 1
ContactContactContactContact
ContactContact
MetalMetal
OxideOxide
Si (p)Si (p)nn++ nn++
0
Vg>0
Vd>0
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Design rulesDesign rules
Design Rule Manual (DRM)– Document that gives the
design rules for a technology node
– Gives the minium dimensions for each level
– Give the minium distance between two levels
The design rules give the maximum density achievable for a technology node
Si=ActiveSi=Active
Lpoly
W
Diam. contact
Poly-active
Poly-contact
Active-contact
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Circuit cross-sectionCircuit cross-section
InterconnectInterconnect
TransistorsTransistors
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FEOL & BEOLFEOL & BEOL
Metal 1Metal 1
Metal 2Metal 2
Metal 3Metal 3
Metal 4Metal 4
Metal 5Metal 5
Metal 6Metal 6
MOSFETsMOSFETsFEOL=Front End of LineFEOL=Front End of Line
BEOL = Back End Of LineBEOL = Back End Of Line