solution hesta8ep
DESCRIPTION
ddsolTRANSCRIPT
-
Principles Of Digital Design
Homework 6 Solution: RTL Storage Components
Shift Register Timing Register File Timing RAM Up/Down Counter
-
RTL Storage Components DIGITAL DESIGN 101, University of California
1. Complete the timing diagram for the shift register shown. Assume the register stores 0s initially and inputs IL and IR are always 1.
Shift Register Timing
Present State Operation
S1 S0 0 0 No Shift 0 1 Load Input 1 0 Shift Left 1 1 Shift Right
Q0D0
3 0Selector Selector Selector Selector
Q1D1Q2D2Q3D3
123 0123 0123 012
I3 I2 I1 I0
Y3 Y2 Y1 Y0
ILIR
S1S0
Clk
Shifter Timing Diagram Shifter Schematic
Shifter Truth Table 2
I3I2I1I0
Clk
Q3Q2Q1Q0
S1S0
t0 t1 t2 t3 t4
-
RTL Storage Components DIGITAL DESIGN 101, University of California
2. Complete the timing diagram for the register file (RF) shown. Assume RF stores 0s initially, REB is always 0, and REA is always 1.
Register File Timing
3
RF Timing Diagram RF Schematic
RFC RFC RFC RFC
RFC RFC RFC RFC
RFC RFC RFC RFC
RFC RFC RFC RFC
0
1
2
3
0
1
2
3
0
1
2
3
2-to-4Write
Decoder
2-to-4Read
Decoder
2-to-4Read
Decoder
I3 I2 I1 I0
B3A3 B2A2 B1A1 B0A0
WA
1
WA
0W
E
RA
B1
RA
B0
RE
BR
AA
1
RA
A0
RE
A
I3I2I1I0
Clk
A3A2A1A0
WAWE
RA
t0t1 t2 t3 t4
1 3 0 2 31 2 3 0 1
-
RTL Storage Components DIGITAL DESIGN 101, University of California
256K RAM Design
3. How many 8 K x 8 RAMs are needed to build a 256k x 16 RAM? What is the size of the decoder for such RAM?
Answer: There are 32 rows and 2 of 8 K x 8 cells in each row. This is a total of 32 x 2 = 64 of 8 K x 8 cells. We also need a 5 to 32 decoder to choose between 32 rows.
... ... ...CS
I7 I1 I0 A12
A1 A0
RWS
8k x 8 RAM
. . .
. . .
O7 O1 O0 . . . . . .
. . .
. . .
Memory address and content
4
-
RTL Storage Components DIGITAL DESIGN 101, University of California
Timer Counter 4. We need to run a circuit that needs a clock frequency of 1MHz with %75
duty cycle ( i.e. maintains 1 for %75 of its period), and we have a signal generator that generates a 16MHz clock signal. Use a counter and simple gates to generate the right clock for our circuit.
Answer:
Q0Q1Q2Q3
Up /Down Counter E
Reset
D
Q4Q5Q6Q7
E D Operations 0 X 1 0 1 1
No change Count up
Count down
5
Q 0Q 1Q 2Q 3
Up/ Down Counter E
Reset
D
Q 4Q 5Q 6Q 7
1
0
Clk
OUT
Homework 6 Solution: RTL Storage ComponentsShift Register TimingRegister File Timing256K RAM DesignSlide Number 5