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  • National Aeronautics and Space Administration

    Scaled CMOS Technology Reliability Users Guide

    Mark White Jet Propulsion Laboratory

    Pasadena, California

    Jet Propulsion Laboratory California Institute of Technology

    Pasadena, California

    JPL Publication 09-33 01/10

  • National Aeronautics and Space Administration

    Scaled CMOS Technology Reliability Users Guide

    NASA Electronic Parts and Packaging (NEPP) Program

    Office of Safety and Mission Assurance

    Mark White Jet Propulsion Laboratory

    Pasadena, California

    NASA WBS: 724297.40.43 JPL Project Number: 103982

    Task Number: 03.02.02

    Jet Propulsion Laboratory 4800 Oak Grove Drive Pasadena, CA 91109

    http://nepp.nasa.gov

  • ii

    This research was carried out at the Jet Propulsion Laboratory, California Institute of

    Technology, and was sponsored by the National Aeronautics and Space Administration

    Electronic Parts and Packaging (NEPP) Program.

    Reference herein to any specific commercial product, process, or service by trade name,

    trademark, manufacturer, or otherwise, does not constitute or imply its endorsement by

    the United States Government or the Jet Propulsion Laboratory, California Institute of

    Technology.

    Copyright 2010. California Institute of Technology. Government sponsorship

    acknowledged.

  • ii

    ABSTRACT

    The desire to assess the reliability of emerging scaled microelectronics technologies

    through faster reliability trials and more accurate acceleration models is the precursor for

    further research and experimentation in this relevant field. The effect of semiconductor

    scaling on microelectronics product reliability is an important aspect to the high

    reliability application user. From the perspective of a customer or user, who in many

    cases must deal with very limited, if any, manufacturers reliability data to assess the

    product for a highly-reliable application, product-level testing is critical in the

    characterization and reliability assessment of advanced nanometer semiconductor scaling

    effects on microelectronics reliability. A methodology on how to accomplish this and

    techniques for deriving the expected product-level reliability on commercial memory

    products are provided.

    Competing mechanism theory and the multiple failure mechanism model are applied to

    the experimental results of scaled SDRAM products. Accelerated stress testing at

    multiple conditions is applied at the product level of several scaled memory products to

    assess the performance degradation and product reliability. Acceleration models are

    derived for each case. For several scaled SDRAM products, retention time degradation is

    studied and two distinct soft error populations are observed with each technology

    generation: early breakdown, characterized by randomly distributed weak bits with

    Weibull slope =1, and a main population breakdown with an increasing failure rate.

  • iii

    Retention time soft error rates are calculated and a multiple failure mechanism

    acceleration model with parameters is derived for each technology. Defect densities are

    calculated and reflect a decreasing trend in the percentage of random defective bits for

    each successive product generation.

    A normalized soft error failure rate of the memory data retention time in FIT/Gb and

    FIT/cm2 for several scaled SDRAM generations is presented revealing a power

    relationship. General models describing the soft error rates across scaled product

    generations are presented. The analysis methodology may be applied to other scaled

    microelectronic products and their key parameters.

  • iv

    Table of Contents List of Tables ..................................................................................................................... viList of Figures ................................................................................................................... viiChapter 1: Overview ............................................................................................................1

    1.1 Background ............................................................................................................11.1.1 Aerospace Vehicle Systems Institute (AVSI) Consortium ....................31.1.2 Lifetime Enhancement through Derating ...............................................41.1.3 Derating Factor ......................................................................................61.1.4 Failure Mechanism Simulation ..............................................................71.1.5 Micro-Architectural Level Reliability Modeling ...................................81.1.6 Circuit-Level Reliability Modeling and Simulation ............................111.1.7 Deep Submicron CMOS VLSI Circuit Reliability Modeling and

    Simulation ............................................................................................121.1.8 Physics-of-Failure Based VLSI Circuits Reliability Simulation and

    Prediction .............................................................................................151.1.9 Product Reliability ...............................................................................16

    1.2 CMOS Technology Scaling and Impact ..............................................................181.2.1 MOS Scaling Theory ...........................................................................181.2.2 Moores Law ........................................................................................201.2.3 Scaling to Its limits ..............................................................................211.2.4 Scaling Impact on Circuit Performance ...............................................231.2.5 Scaling Impact on Power Consumption ...............................................241.2.6 Scaling Impact on Circuit Design ........................................................251.2.7 Scaling Impact on Parts Burn-in ..........................................................271.2.8 Scaling Impact on Long Term Microelectronics Reliability ...............28

    1.3 Physics-of-Failure (PoF) Methodology ...............................................................311.3.1 Competing Mechanism Theory............................................................321.3.2 Intrinsic Failure Mechanism Overview ...............................................321.3.3 Hot Carrier Injection and Statistical Model .........................................331.3.4 Electromigration and Statistical Model ...............................................351.3.5 Negative Bias Temperature Instability and Statistical Model .............361.3.6 Time-Dependent Dielectric Breakdown and Statistical Model ...........371.3.7 Multiple Failure Mechanism Model ....................................................381.3.8 Acceleration Factor ..............................................................................40

    1.4 Motivation and Objectives ...................................................................................431.4.1 Motivation ............................................................................................431.4.2 Objectives ............................................................................................47

    Chapter 2: Scaling Impact on SDRAM .............................................................................482.1 Overview ..............................................................................................................482.2 Design of Experiments .........................................................................................52

    2.2.1 Electrical Test Flow .............................................................................572.2.2 Electrical Test Conditions and Limits ..................................................58

    2.3 Technology and Construction Analysis ...............................................................62

  • v

    2.4 Device Characterization .......................................................................................642.4.1 Voltage Breakdown .............................................................................642.4.2 Minimum Frequency Operation Characterization ...............................65

    2.5 Stress Test Results ...............................................................................................652.5.1 Stress Test Results (Iddo) ......................................................................662.5.2 Retention Time Degradation (Tret) .....................................................69

    Chapter 3: SDRAM Degradation and Predictive Model ...................................................733.1 Acceleration Model ..............................................................................................73

    3.1.1 Life Distribution..................................................................................743.1.2 Multivariable Life-Stress Relationship ...............................................75

    3.2 Data Analysis .......................................................................................................813.3 Degradation Model ..............................................................................................97

    Chapter 4: Physics-of-Failure & Systems Approach .......................................................1014.1 Overview ............................................................................................................1014.2 Failure Mechanisms .......................................

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