design for manufacturability and reliability in extreme...
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Design for Manufacturability and Reliability in Extreme CMOS Scaling and Beyond
David Z. Pan Dept. of Electrical and Computer Engineering
The University of Texas at Austin http://www.cerc.utexas.edu/utda
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Nanometer Issues
-nce
Temp(oC)
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Emerging Lithography EUV
mindp
193i w/ DPL
E-beam
Quadruple patterning
DSA 3D-IC
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The “Moore”, the Merrier!
t More Moore • Nano-Patterning for Extreme Scaling
• Lithography Aware Physical Design
t A different kind of “Moore” • 3D Integration
• New devices/material/…
è Need synergistic design and technology co-optimization for cross-layer resilience
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What is Double Patterning?
Overlay Error
mindp
Stitch A E
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Dealing with Overlay in LELE
6
1st patterning
C1 -∆C1
1st patterning C2 -∆C2
2nd patterning 2nd patterning
2nd patterning
C1 -∆C1 C2 +∆C2
2nd patterning
1st patterning
Overlay Compensation
Stitch
[Lucas SPIE’08]
Stitch
Minimum Stitch Insertion
1) Minimize stitch # 2) A bit more overlap margin for stitch, but area increases
1st patterning
Without Overlay Compensation With Overlay Compensation
[Yang+, ASPDAC10]
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A Graph-Partitioning Based, Multi-Objective Decomposer
Decomposition Graph Construction
A
Ā
A
Ā
A
Ā
E
Ē
E
Ē
E
Ē
X Y Z
7
Ā(20) A(17)
X(9)
E(15)
Y(9)
Ē(17)
1 2
2 1
Z(5)
1
1
Constraint: (A, Ā) and (E, Ē) are repulsive pairs.
Theorem : Stitch minimization problem is equivalent to the min-cut partitioning of the decomposition graph Extensions of the framework: to incorporate other constraints and costs into graph partitioning, e.g., balanced density, overlay compensation, and so on
[Yang+, ASPDAC10]
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Overlay Compensation & Density Balancing
8
C432:27% and 73% (7 stitches)
C432:50% and 50% (17 stitches)
[Yang+, ASPDAC10]
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Triple Patterning
t What’s triple patterning lithography (TPL)? › Extension of double patterning concept › Original layout is divided into three masks › Triple effective pitch
t Why TPL? › Delay of next generation lithography (EUV, E-beam) › Resolve conflicts of DPL › Achieve further feature-size scaling (14nm, 11nm)
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LAPD
t Double/multiple patterning layout compliance/decomposition
t Still something could go wrong! t Lithography Aware Physical Design
(LAPD) è t Litho Hotspot Detection t Litho Friendly Design
› Hotspot Avoiding/Correction › Correct by Construction/Prescription
10
Another LAPD
Correction
Detection
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Lithography Hotspot Detection
t Lithographic hotspots › What you see (at design) is NOT what you get (at fab) › Hotspots mean poor printability › Highly dependent on manufacturing conditions › Exist after resolution enhancement techniques
t Litho-simulations are extremely CPU intensive › Full-blown OPC could take a week › Impossible to be used in inner design loop
Litho simulations
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Various Approaches
12
Pattern/Graph Matching
t Pros and cons › Accurate and fast for known
patterns › But too many possible
patterns to enumerate › Sensitive to changing
manufacturing conditions › High false-alarms
Data Mining/Machine Learning
SVM [J. Wuu+ SPIE09][Drmanac+ DAC09] Neural Network Model [Norimasa+ SPIE07][Ding+ ICICDT09] Regression Model [Torres+ SPIE09]
[Xu+ ICCAD07] [Yao+ ICCAD08, [Khang SPIE06], etc.
t Pros and cons t Good to detect unknown or
unseen hotspots t Accuracy may not be good for
“seen” patterns (cf. PM) › Hard to trade-off accuracy and
false alarms
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A New Unified Formulation (EPIC) Good for detecting all types of hotspots with advantageous accuracy/false-alarm (Meta-Classifier)
A New Meta-Classification Paradigm
t Meta-Classification combines the strength of different types of hotspot detection techniques
13
Pattern Matching Methods Good for detecting previously known types of hotspots
Machine Learning Methods Good for detecting new/previously unknown hotspots
[Ding et al, ASPDAC 2012]
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Components of Meta-Classifier Core
t Base classifier results are first collected t Weighting functions to make the overall meta
decision (e.g., quadratic programming) t Threshold with accuracy and false-alarm trade-off
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Critical Pattern/Feature Extraction
Weighting Functions and Decision Parameters
Base Classifier Decision
Meta-Classifier Core
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False-alarm Rate and Accuracy
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AENEID Router [Ding+, DAC’11]
t Using the machine learning models, we built a new detailed router AENEID to avoid hotspot patterns
Initialize Lagrangian Multiplier
Solve the MCSP Problem
Update Layout Fragmentation Database
Stopping criteriaSatisfied?
N
Y
Update Lithography Cost : litho(e)
solution
Update Lagrangian Multiplier
Hotspot Detection Kernel
Routing Path Prediction Kernel
AENEID
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Machine Learning for Placement
t Data mining and extraction based on not just graph but also physical information
t We can extract data-path like structures even for “random” logics
t Use them to explicitly guide placement
t Very good results obtained cf. other leading placers like simPL, NTUPlace, mPL, CAPO
Datapath Aware Detailed Placement
Legalization
4. Cluster Classification and Evaluation
3. High-Dimensional Data Extraction
Circuit Netlist
2. Single GP Iteration
6. Datapath Aware Single GP Iteration
δ ≤ n < M
5. ILP Based Bit-stack Selection
n < δ no
no
yes
yes
1. Trained Data
Models
[Ward+, DAC’12]
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Abstraction to Logic Synthesis & Above?
t Can we further extend the abstraction up to logic synthesis?
› Not just lithography hotspot, but other hotspots such as reliability metrics including BTI, oxide breakdown
t Machine learning to raise the abstraction t NSF/SRC FRS program (started April 1, 2003)
› E.g., Deming Chen and I have a collaborative project across lower level PD to high level synthesis
t NSF/SRC/DFG Cross-Layer Resilience Workshop in Austin, July 11 and 12
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Extreme Scaling and Beyond
t Continuing pushing the envelope, 14nm, 11nm, 7nm (ITRS)
› Double/triple Patterning › Emerging Nanolithography › Novel design tools and methodologies
t Vertically – 3D IC integration
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Thermal/Mechanical Stress
CTE : Coefficient of thermal expansion
TSV: 250 °C ~400 °C process (Higher than operating temperature) Since Cu has larger CTE than Si è tensile stress in Si near TSV.
Silicon Cu TSV
< Tensile stress >
FEA simulation structure of a single TSV # variables: 400K, Memory: 2GB runtime: 40min
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Stress => Variability/Reliability t Systematic Variations
› Mobility › Timing
t Reliability (interfacial crack, EM, etc.)
Si Cu
Electromigration Effect – Open
Electromigration Effect – Short Interfacial Crack
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Lateral Linear Superposition
TSV1 TSV2
TSV3 TSV4
stress influence zone (25um)
P: point under consideration
TSV4 doesn’t affect P
TSV1, TSV2, and TSV3 affect P
[ECTC’11, DAC’11]
t Full-chip stress analysis considering multiple TSVs
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t FEA simulation structures
› All structures undergo ∆T = -250°C of thermal load (Annealing/reflow 275°C → room temperature 25°C)
Chip-Package Co-Analysis of Stress
substrate TSV 30um device layer
30um
μ-‐bump 20um
20um
TSV
Pkg-‐bump
30um
100um
100um
TSV
Pkg-‐bump
30um
100um
μ-‐bump 20um
100um
BEOL
Back metal 5um
(a) TSV only (b) TSV + μ-‐bump
(c) TSV + pkg-‐bump (d) TSV + μ-‐bump + pkg-‐bump
underfill
underfill
device layer
device layer
device layer
TSV
[Jung et al, DAC’12]
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(Lateral &) Vertical Superposition
t Stress components are added up “vertically”
LVLS works well
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Interactive Stress & Modeling
t Linear superposition: › Consider the stress contribution of TSV separately › May not be accurate enough for very dense TSVs with BCB liner
t Semi-analytical model developed [Li and Pan, DAC’13] › Still run fast › Can reduce the error by 50%
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Reliability/Variability Impact of Stress
1. Von Mises Reliability
2. Crack: Energy release rate (ERR)
3. Mobility/ Vth variaOon of MOS
• Von Mises Yield is function of stress tensor
• TSV stress affects ERR of TSV structure à aggravate crack
Cu shrinking d: iniOal crack length
crack propagaOon direcOon
crack front
(a) Side view
TSV
substrate
(b) Top view
liner
• TSV stress changes mobility of hole/electron à timing, Vth variation
(a) Hole mobility variaOon
(b) Electron mobility variaOon
(a) Von Mises stress with TSV array
(b) Von Mises stress with three TSVs
[J. Mitra et al., ECTC’11] [M. Jung et al., ICCAD’11] [J. Yang et al., DAC’10]
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From Stress to Reliability t Von Mises Reliability Metric
t Physical meaning
2)σσ6(σ)σ(σ)σ(σ)σ(σ
σ2zx
2yz
2xy
2xxzz
2zzyy
2yyxx
v
+++−+−+−=
linear elastic
plastic L
strain LLΔ
=ε
ε
σv
If σv > yielding strength, deformation will be permanent and non-reversible Yielding strength - Cu: 225 ~ 600 MPa - Si: 7,000 MPa
yielding strength
∆L
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Wide I/O 3D DRAM 8mm
8m
m
Bank0 Bank1
Bank2 Bank3
2x128 TSV array 1024 TSVs in total
Bank0 Bank1
Bank2 Bank3
(a) Pkg-bumps are placed underneath TSV arrays
(b) Pkg-bumps are placed 200um apart from TSV arrays
Pkg-bump
200um
…
…
…
…
…
…
…
…
case von Mises stress distribution (MPa)
780-810 810-840 840-870 870-900 900-930 (a) 30 114 52 220 608 (b) 182 842 0 0 0
case (b) shows that chip/package co-design can greatly reduce mechanical reliability problem in TSV-based 3D ICs
[Jung et al, DAC’12]
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TSV Interfacial Crack
Cu shrinking d: initial crack length
crack propagation
direction
crack front TSV
substrate
(a) Side view (b) Top view
liner
• Cu shrinks faster than Si under negative thermal load (∆T = -250°C) • Model through Energy Release Rate (ERR) • Full chip model with design-of-experiments of different layout styles
and multiple TSV structures
[Jung et al, ICCAD’11]
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Full-Chip Crack Analysis and Study t Regular vs. irregular TSV arrays
(a) IrregA (b) RegA
(c) ERR map of IrregA (d) ERR map of RegA
100um
ERR (J/m2)
2.15 2.10 2.05 2.00 1.95 1.90 1.85 1.80
1.95 ~ 2.00
1.90 ~ 1.95
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Stress Effect on Mobility & Current
TSV
CMOS (Stress: 200MPa, R=r)
Cmos
NMOS: 0.5 ∆µ (∆Ids:+1.5%) PMOS: 0.6∆µ (∆Ids:+1.8%)
Cmos
NMOS: ∆µ(∆Ids:+3%) PMOS: -∆µ(∆Ids:-3%)
Cmos
NMOS: 0.75∆µ (∆Ids:+2.25%) PMOS: -0.1∆µ(∆Ids:-0.3%)
Cell characterizations based on distance and orientation are needed
FS corner
[Yang+, DAC’10]
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Stress Aware Design Flow [Yang+, DAC’10]
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Stress estimation induced by TSVs
Mobility change (∆µ/µ) calculation
Verilog, SPEF merging for 3D STA
Cell characterization with mobility (Cell name change in Verilog)
TSV stress aware layout optimization
Pre-placed TSV location
Liberty file having cell timing with different
mobility
Stress aware Verilog netlist
Critical gate selection
3D Timing Analysis with PrimeTime
Optimized layout with TSV stress
Verilog netlist
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Stress-Aware ECO
3
7
2
4
8 9
3
7
2
4
8 9 Rising critical optimization
with hole contour
Falling critical optimization
with electron contour
Original cell placement After cell perturbation
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Nanophotonics On-chip Integration
t Holistic Optical Interconnect Planning and Synthesis › Co-design and optimization with electrical interconnect › Optical interconnect library (OIL) ) [Ding+, DAC’09,
SLIP’09, and available http://www.cerc.utexas.edu/~ding/oil.htm] › WDM, partitioning, routing, …
t Nanophotonics is a very active field t Many new research problems for CAD community!
Electro-Optical Interconnect Planning
Electro-Optical Interconnect Synthesis
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Case Study 1: O-Router [Ding et al, DAC’09]
t Objectives: performance (throughput, latency, power), cost ($$, economics)
t Constraints (SNR, signal integrity, reliability, system-level reqs.)
pin2
Si
Metal L ayerspin1
pin2
transistor layeroptical waveguide
SiDedicated transistor layer
Metal L ayerspin1
pin3
Si
dedicated photonic layer
Metal L ayers
optical waveguide
pin1
Metal L ayers
-‐ optical and electrical data conversion
-‐ wafer-‐to-‐wafer T SV
pin2pin2
Si
Metal L ayerspin1 pin3
pin4
transistor layeroptical waveguide
SiDedicated transistor layer
Metal L ayerspin1
pin3
Si
dedicated photonic layer
Metal L ayers
optical waveguide
pin1
Metal L ayers
-‐ optical and electrical data conversion
-‐ wafer-‐to-‐wafer T SV
-‐ optical and electrical data conversion
-‐ wafer-‐to-‐wafer T SV-‐ wafer-‐to-‐wafer T SV
pin4
(b)(a)
R R
R
R R
P2-1
P1-1P1-2
P3-1
P2-1
P1-1P1-2
P1-3
P1-4P2-2P3-2
P1-3
P1-3P2-1P1-1
P1-2
P1-2
P1-1
P2-1 P1-3
P1-1
P1-2
P1-3
P1-4
P2-3
P2-2
P2-1
P3-1
P3-2
P3-3
P4-1 P4-2
P4-3
(c)
pin2
Si
Metal L ayerspin1
pin2
transistor layeroptical waveguide
SiDedicated transistor layer
Metal L ayerspin1
pin3
Si
dedicated photonic layer
Metal L ayers
optical waveguide
pin1
Metal L ayers
-‐ optical and electrical data conversion
-‐ wafer-‐to-‐wafer T SV
pin2pin2
Si
Metal L ayerspin1 pin3
pin4
transistor layeroptical waveguide
SiDedicated transistor layer
Metal L ayerspin1
pin3
Si
dedicated photonic layer
Metal L ayers
optical waveguide
pin1
Metal L ayers
-‐ optical and electrical data conversion
-‐ wafer-‐to-‐wafer T SV
-‐ optical and electrical data conversion
-‐ wafer-‐to-‐wafer T SV-‐ wafer-‐to-‐wafer T SV
pin4
pin2pin2
Si
Metal L ayerspin1
pin2
transistor layeroptical waveguide
SiDedicated transistor layer
Metal L ayerspin1
pin3
Si
dedicated photonic layer
Metal L ayers
optical waveguide
pin1
Metal L ayers
-‐ optical and electrical data conversion
-‐ wafer-‐to-‐wafer T SV
-‐ optical and electrical data conversion
-‐ wafer-‐to-‐wafer T SV-‐ wafer-‐to-‐wafer T SV
pin2pin2
Si
Metal L ayerspin1 pin3
pin4
transistor layeroptical waveguide
SiDedicated transistor layer
Metal L ayerspin1
pin3
Si
dedicated photonic layer
Metal L ayers
optical waveguide
pin1
Metal L ayers
-‐ optical and electrical data conversion
-‐ wafer-‐to-‐wafer T SV-‐ wafer-‐to-‐wafer T SV
-‐ optical and electrical data conversion
-‐ wafer-‐to-‐wafer T SV-‐ wafer-‐to-‐wafer T SV
pin4
(b)(a)
R R
R
R R
P2-1
P1-1P1-2
P3-1
P2-1
P1-1P1-2
P1-3
P1-4P2-2P3-2
P1-3
P1-3P2-1P1-1
P1-2
P1-2
P1-1
P2-1 P1-3
P1-1
P1-2
P1-3
P1-4
P2-3
P2-2
P2-1
P3-1
P3-2
P3-3
P4-1 P4-2
P4-3
(c)
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Case Study 2: GLOW
t Global router for low-power thermal-reliable optical interconnect synthesis using Wavelength Division Multiplexing (WDM)
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Minimize Power (Laser driving power)
Circuit implementation
Max{inter. Delay} <= A
Max{SNR} <= B
Min{Ther. Reliability} >= C
Min{Pathend power} >= D
Synthesis Engine GLOW for On-Chip Optical/Electrical Interconnect
[Ding et al, ASPDAC’12]
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Conclusion
t Optical lithography still pushing ahead for 14nm, 11nm, 7nm è extreme scaling › Multiple patterning, EUV, DSA, and hybrid lithography
t Design enablement with lithography capability co-optimization from mask to physical synthesis (and logic/high-level synthesis?) › Cross-layer resilience
t Horizontal scaling è Vertical scaling: 3D-IC › Reliability/Variability issues
t New material/devices è new CAD paradigms and tools
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Acknowledgment
t Support/collaboration from NSF, SRC, NSFC, Sematch, IBM, Intel, Oracle, Fujitsu, Qualcomm, Synopsys, Mentor Graphics, …
t The materials in this talk include results from many former/current PhD students at UTDA
› They are the ones who did the real work!
t Collaborators › DFM: IBM, Intel, Globalfoundries, Mentor, Synopsys, etc. › 3D-IC: Prof. Sung Kyu Lim’s group at Georgia Tech › Optical: Prof. Ray Chen’s group at UT Austin