risc by betty tang

RISC by

Betty Tang

CS 147 RISC by Betty Tang 2

What is RISC?What is RISC?

RISC stands for RISC stands for RReduced educed IInstruction nstruction SSet et CComputer. omputer.

It is a computer CPU design philosophy that It is a computer CPU design philosophy that favors a favors a smallersmaller and and simplersimpler set of set of instructions that all take about the instructions that all take about the same same amount of timeamount of time to execute . to execute .

Also referred to as load-store architectures.Also referred to as load-store architectures.


What inspired RISC?What inspired RISC?

The idea was inspired by:The idea was inspired by:

• The discovery that many features that The discovery that many features that were included in traditional CPU designs were included in traditional CPU designs for speed were being ignored by the for speed were being ignored by the programs that were running on them.programs that were running on them.

• The disparity of speed of the CPU in The disparity of speed of the CPU in relation to memory speed.relation to memory speed.


Pre-RISC design Pre-RISC design Philosophy (CISC)Philosophy (CISC)

• Compiler technology did not exist!Compiler technology did not exist!

• Computer architects created more and more Computer architects created more and more complex instructions which were direct complex instructions which were direct representation of high level programming representation of high level programming languages.languages.

• At the time, hardware design was easier than At the time, hardware design was easier than compiler design, so the complexity went into compiler design, so the complexity went into hardware.hardware.


CISC CharacteristicsCISC Characteristics

• Instruction packingInstruction packing– Memories were small and precious. Memories were small and precious.

• In 1979, a 32KB memory cost $329. In 2004, In 1979, a 32KB memory cost $329. In 2004, 512MB cost $75. 512MB cost $75.

• An order of 4 magnitude decrease in $ per byte!An order of 4 magnitude decrease in $ per byte!

– Therefore, it was advantageous to pack as Therefore, it was advantageous to pack as much information in a single instruction as much information in a single instruction as possible to avoid access slower resource.possible to avoid access slower resource.

– As a result, instruction are highly encoded, As a result, instruction are highly encoded, variable sized, can perform multiple operations variable sized, can perform multiple operations and did both data movement and data and did both data movement and data calculation.calculation.


CISC CharacteristicsCISC Characteristics

• x86 example:x86 example:

.date .date var1 DWORD 30000hvar1 DWORD 30000h

.code.codeadd var1, 40000hadd var1, 40000h

calculation data storage data movementcalculation data storage data movement

– In a single instruction, a source operand is added to In a single instruction, a source operand is added to a destination operand, and the sum is stored in the a destination operand, and the sum is stored in the destination.destination.


CISC Characteristics CISC Characteristics (cont’d)(cont’d)

• Small set of registersSmall set of registers– CPU only had a few registers due to the CPU only had a few registers due to the

limitation in silicon integration and available limitation in silicon integration and available RAM.RAM.

– Silicon integration was not mature enough to Silicon integration was not mature enough to free up space in the chip area or board area for free up space in the chip area or board area for a larger register sets.a larger register sets.

– Having a large number of registers would have Having a large number of registers would have required a large number of instruction bit using required a large number of instruction bit using precious RAM.precious RAM.


CISC Characteristics CISC Characteristics (cont’d)(cont’d)

• ““Orthogonal” addressing modeOrthogonal” addressing mode– The general goal was to provide every The general goal was to provide every

possible addressing mode for every possible addressing mode for every instruction.instruction.

– This led to CPU complexity but in This led to CPU complexity but in theory every command could be tuned, theory every command could be tuned, making the design faster than if making the design faster than if simpler command is used.simpler command is used.


The emerging reasons for The emerging reasons for RISCRISC• In the late 1970s, research showed the majority of In the late 1970s, research showed the majority of

these “orthogonal” addressing modes were ignored these “orthogonal” addressing modes were ignored by most programs.by most programs.

– A side effect of the increasing use of compilers to A side effect of the increasing use of compilers to generate the programs, as opposed to writing them in generate the programs, as opposed to writing them in assembly language. The compilers in use at the time assembly language. The compilers in use at the time did not take advantage of the feature provided by did not take advantage of the feature provided by CISC CPUs.CISC CPUs.

• Another discovery was that since orthogonal mode Another discovery was that since orthogonal mode were rarely used, complex instruction tended to be were rarely used, complex instruction tended to be slower than a number of smaller operations doing slower than a number of smaller operations doing the same thing.the same thing.


The emerging reasons for The emerging reasons for RISC (cont’d)RISC (cont’d)

• CPU starts to run ever faster than CPU starts to run ever faster than memory and the trend continue.memory and the trend continue.

• It become apparent that more It become apparent that more registers would be need to support registers would be need to support these higher operating frequencies.these higher operating frequencies.


RISC design philosophyRISC design philosophy• New ideas about how to dramatically increase New ideas about how to dramatically increase

performance of the CPUs were starting to performance of the CPUs were starting to develop in the early 1980s, namely, pipelining develop in the early 1980s, namely, pipelining and parallel processing.and parallel processing.

• Pipelining: include a pipeline which would break Pipelining: include a pipeline which would break down instructions into steps, and work on one down instructions into steps, and work on one step of several instructions at the same time.step of several instructions at the same time.

• Parallel processing: instead of working on one Parallel processing: instead of working on one instruction, processors would look at the next instruction, processors would look at the next instruction in the pipeline and attempt to run it instruction in the pipeline and attempt to run it at the same time.at the same time.


RISC design RISC design philosophy(cont’d)philosophy(cont’d)

• Pipelining and Parallel processing relied on Pipelining and Parallel processing relied on increasing speed by adding complexity to the increasing speed by adding complexity to the basic layout of the CPU, as opposed to the basic layout of the CPU, as opposed to the instructions running on them.instructions running on them.

• In order to include these feature, something In order to include these feature, something would have to be removed to make room.would have to be removed to make room.

• RISC was design to incorporate these two RISC was design to incorporate these two technique since the core logic of a RISC CPU was technique since the core logic of a RISC CPU was much simpler than in CISC designs. much simpler than in CISC designs.


RISC design RISC design philosophy(cont’d)philosophy(cont’d)

• By the late 1980s, RISC were significantly By the late 1980s, RISC were significantly outperforming their CISC counterparts.outperforming their CISC counterparts.

Four stages in executing an instruction in CISC:Four stages in executing an instruction in CISC:

– Fetch, decode, execute, writeFetch, decode, execute, write

– Each instruction will take at least 4 clock cycles, some Each instruction will take at least 4 clock cycles, some complex instructions can take even morecomplex instructions can take even more

These same stages exist in a RISC machine, but the stages These same stages exist in a RISC machine, but the stages are execute in parallel. As soon as one stage completes, are execute in parallel. As soon as one stage completes, it passes on the result to the next stage and then begins it passes on the result to the next stage and then begins working on another instruction. This grantees each working on another instruction. This grantees each instruction will take only one clock cycle.instruction will take only one clock cycle.


RISC CharacteristicsRISC Characteristics• Fewer transistors dedicated to the core logic.Fewer transistors dedicated to the core logic.

• Larger register setLarger register set

– 32 general purpose registers in MIPS vs. 16 in Intel’s x8632 general purpose registers in MIPS vs. 16 in Intel’s x86

• Simple instruction setSimple instruction set

– the instruction set contains simple, basic instruction from which the instruction set contains simple, basic instruction from which more complex instructions can be composed.more complex instructions can be composed.

• Single machine-cycle instructionsSingle machine-cycle instructions

– most instructions complete in one machine cycle, which allows most instructions complete in one machine cycle, which allows the processor to handle several instructions at the same time the processor to handle several instructions at the same time via pipelining. via pipelining.

• Uniform instruction encoding which allows faster decodingUniform instruction encoding which allows faster decoding

• Complete separation between instructions that compute and Complete separation between instructions that compute and instructions that access memoryinstructions that access memory


RISC Characteristics (con’t)RISC Characteristics (con’t)• Complete separation between instructions that compute and Complete separation between instructions that compute and

instructions that access memoryinstructions that access memory

• MIPS example to add 3000h to memory:MIPS example to add 3000h to memory:

.data.data

.globl var.globl var

var: var: .word 500h.word 500h

__start:__start:

lw lw $t0, var$t0, var

addi addi $t1, $t0, 3000h$t1, $t0, 3000h

sw sw var, $t1var, $t1

.end.end


RISC MachineRISC Machine• The first system was designed in 1964 by Jim Thornton and The first system was designed in 1964 by Jim Thornton and

Seymour Cray as a number-crunching CPU.Seymour Cray as a number-crunching CPU.

• Another load/store machine was Data General Nova Another load/store machine was Data General Nova minicomputer, designed in 1968.minicomputer, designed in 1968.

• Yet, most public RISC designs were the results of university Yet, most public RISC designs were the results of university research programs.research programs.

• In 1980, under the direction of David Patterson, UC In 1980, under the direction of David Patterson, UC Berkeley's RISC project aimed to gain performance through Berkeley's RISC project aimed to gain performance through the use of pipelining and an aggressive use of register the use of pipelining and an aggressive use of register windows.windows.

• CPU with register windows has 128 registers, but programs CPU with register windows has 128 registers, but programs can only use 8 of them at a time. This limit per procedure can only use 8 of them at a time. This limit per procedure results in very fast procedure calls.results in very fast procedure calls.


RISC Machine(cont’d)RISC Machine(cont’d)

• In 1981, John Hennessy started a similar project called In 1981, John Hennessy started a similar project called MIPS at Stanford University. MIPS focussed almost MIPS at Stanford University. MIPS focussed almost entirely on the pipeline, making sure it could run as “full” entirely on the pipeline, making sure it could run as “full”

as possible.as possible.

• A number of successful RISC platforms and architectures A number of successful RISC platforms and architectures were developed in the 80’s to early 90’s.were developed in the 80’s to early 90’s.– MIPS: found in most SGI computers, PlayStation and Nintendo 64 MIPS: found in most SGI computers, PlayStation and Nintendo 64

game consoles.game consoles.– IBM’s Power series: used in all their minis and mainframesIBM’s Power series: used in all their minis and mainframes– Motorola and IBM’s PowerPC: used in all Apple Macintosh computersMotorola and IBM’s PowerPC: used in all Apple Macintosh computers– Sun’s SPARC and UltraSPARCSun’s SPARC and UltraSPARC– HP’s PA-RISC HP/PAHP’s PA-RISC HP/PA– DEC AlphaDEC Alpha


MIPS Instruction EncodingMIPS Instruction Encoding

Op

31 26 01516202125

Rs1 Rd immediate

Op

31 26 025

Op

31 26 01516202125

Rs1 Rs2

target

Rd Opx

Register-Register

561011

Register-Immediate

Op

31 26 01516202125

Rs1 Rs2/Opx immediate

Branch

Jump / Call

Shamt


RegADD Disp.

34 8

postbyteSHL

6 8

V/w

2

Disp.

8

TEST

7

W

1

postbyte

8

Immediate

8

W

1

x86 Instruction Encodingx86 Instruction Encoding

PUSH

5

Reg

3

CondJE Disp.

44 8

postbyteMOV

6 8

D/w

2

Disp.

8

CALLF Offset Segment Number

8 16 16


Decline of RISC, is it really?Decline of RISC, is it really?

• Despite many successes, RISC has not make it into the Despite many successes, RISC has not make it into the desktop PC and commodity server markets. desktop PC and commodity server markets.

• Intel’s x86 still remains the dominant processor Intel’s x86 still remains the dominant processor architecture.architecture.

– x86 had a very large base of proprietary applications. x86 had a very large base of proprietary applications. It is very difficult for companies to switch to RISC.It is very difficult for companies to switch to RISC.

– Intel had spend large amounts of money on processor Intel had spend large amounts of money on processor development. development.

– Recall that RISC is a set of design philosophies and Recall that RISC is a set of design philosophies and practices instead of an architecture. Instead of practices instead of an architecture. Instead of allowing itself to lag behind in the competitive market, allowing itself to lag behind in the competitive market, Intel started to apply many of RISC principles to their Intel started to apply many of RISC principles to their CISC processors.CISC processors.


Modern CPU designsModern CPU designs• The difference between CISC and RISC today is only in their The difference between CISC and RISC today is only in their

instruction sets (ISA).instruction sets (ISA).

• Important development in the 90s encourage separations Important development in the 90s encourage separations between CPU architecture designs from instruction designs. between CPU architecture designs from instruction designs. Most CPU today will have a translator to translate native Most CPU today will have a translator to translate native instruction set to internal instruction set.instruction set to internal instruction set.

• Recall the traditional design of CISC favors instruction Recall the traditional design of CISC favors instruction packing? Nowadays, CISC machine takes CISC instructions packing? Nowadays, CISC machine takes CISC instructions and translate them into simpler RISC-like instructions. and translate them into simpler RISC-like instructions.

• In addition, modern CISC design have include large number In addition, modern CISC design have include large number of pipelines, utilize techniques such as instruction reordering, of pipelines, utilize techniques such as instruction reordering, branch prediction (continuous improvement in compiler branch prediction (continuous improvement in compiler designs to inject hints to CPU what to expect next), designs to inject hints to CPU what to expect next), Simultaneous Multithreading (SMT) to increase CPU Simultaneous Multithreading (SMT) to increase CPU performance.performance.

• Pipelining and branch prediction were all inherently RISC and Pipelining and branch prediction were all inherently RISC and continue to play an important part in modern CPU designs.continue to play an important part in modern CPU designs.


Further readingFurther reading

CISC vs RISCCISC vs RISChttp://ctas.east.asu.edu/bgannod/CET520/Spring02/Projects/http://ctas.east.asu.edu/bgannod/CET520/Spring02/Projects/demone.htmdemone.htm

Simultaneous MultithreadingSimultaneous Multithreadinghttp://en.wikipedia.org/wiki/Simultaneous_multithreadinghttp://en.wikipedia.org/wiki/Simultaneous_multithreading

Computer Organization & Design: The Hardware/Software Computer Organization & Design: The Hardware/Software InterfaceInterfacePatternson, David. A and Hennessy, John L.Patternson, David. A and Hennessy, John L.ISBN: 1558606041ISBN: 1558606041

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