Review for Final: CPE 329 Fall 2007Review for Final: CPE 329 Fall 2007

•• Lectures 1Lectures 1--14, Therac14, Therac--25, Chapters 1 & 2, Labs 125, Chapters 1 & 2, Labs 1--55•• Exam Review OutlinesExam Review Outlines•• Homework problemsHomework problems•• ISE/EDK technologyISE/EDK technology•• DigilentDigilent Nexys board and peripherals technologyNexys board and peripherals technology

–– Not held accountable for specifics of Not held accountable for specifics of DigilentDigilent D2FTD2FT--DIO5 DIO5 technology, just principlestechnology, just principles

•• No coding, just pseudo code (no syntax)No coding, just pseudo code (no syntax)•• One page (both sides) of reference notesOne page (both sides) of reference notes•• Calculator Calculator

•• Course DescriptionCourse Description•• Course Learning ObjectivesCourse Learning Objectives•• Topics CoveredTopics Covered•• Prerequisite materialPrerequisite material•• Course MaterialCourse Material•• Lab OverviewLab Overview

–– Development Environment (CAD Tools)Development Environment (CAD Tools)–– Lab EquipmentLab Equipment–– ProcessorProcessor

•• Lab ExperimentsLab Experiments–– Experiment 1 HardwareExperiment 1 Hardware--Based Digital ClockBased Digital Clock–– Experiment 2 MicroBlaze Experiment 2 MicroBlaze ““Hello World!Hello World!””–– Experiment 3 MicrocontrollerExperiment 3 Microcontroller--Based Digital ClockBased Digital Clock–– Experiment 4 Function GeneratorExperiment 4 Function Generator–– Experiment 5 Final Design ProjectExperiment 5 Final Design Project

Exam Review Outline: lecture 1Exam Review Outline: lecture 1CPE 329 OverviewCPE 329 Overview

•• Taxonomy of Digital SystemsTaxonomy of Digital Systems–– Advantages and Disadvantages of each categoryAdvantages and Disadvantages of each category ((Cost, Cost,

performance, ease of design, customization, configurability, performance, ease of design, customization, configurability, integration, number of transistors)integration, number of transistors)

•• Semiconductor Technology TrendsSemiconductor Technology Trends–– MooreMoore’’s Law Number of transistors per die doubles every s Law Number of transistors per die doubles every

couple of years (historical data) couple of years (historical data) http://www.intel.com/research/silicon/mooreslaw.htmhttp://www.intel.com/research/silicon/mooreslaw.htm

–– ITRS Future ProjectionITRS Future Projection–– Increase in the number of practicing engineers per yearIncrease in the number of practicing engineers per year–– Must work at higher levels of abstractionMust work at higher levels of abstraction

•• Increasing levels of abstraction for HW and SWIncreasing levels of abstraction for HW and SW–– Hardware Software CoHardware Software Co--designdesign

Exam Review Outline: lecture 2Exam Review Outline: lecture 2Introduction to Digital SystemsIntroduction to Digital Systems

•• History of Integrated CircuitsHistory of Integrated Circuits•• Advantages of CPLDsAdvantages of CPLDs•• Programmable Elements to connect nets or configure hardware deviProgrammable Elements to connect nets or configure hardware devicesces

–– OneOne--timetime--programmable (OTP) programmable (OTP) –– Fuse/AntifuseFuse/Antifuse–– ReRe--programmableprogrammable

•• Volatile (SRAM)Volatile (SRAM)•• NonNon--Volatile (EEPROM, Flash)Volatile (EEPROM, Flash)

•• CPLD Architecture Functional BlocksCPLD Architecture Functional Blocks–– SPLD like configurable logic SPLD like configurable logic

–– MacroCellMacroCell–– MacroBlockMacroBlock

–– Programmable InterconnectProgrammable Interconnect–– I/O BlocksI/O Blocks

•• FPGA ArchitectureFPGA Architecture–– FPGA Fabric FPGA Fabric

•• Configurable Logic Block (Programmable MUX, Look Up Table, Pass Configurable Logic Block (Programmable MUX, Look Up Table, Pass Transistor)Transistor)•• Programmable InterconnectProgrammable Interconnect•• I/O BlocksI/O Blocks•• Block RAM MemoryBlock RAM Memory•• Hardcore blocks (ie Multipliers, PowerPC)Hardcore blocks (ie Multipliers, PowerPC)

–– System on Chip (Soc) using Hardcore or Softcore ProcessorsSystem on Chip (Soc) using Hardcore or Softcore Processors

Exam Review Outline Exam Review Outline –– lecture 3lecture 3Programmable LogicProgrammable Logic

•• Programmable Interconnect (6Programmable Interconnect (6--transistor junction)transistor junction)–– Direct Direct –– CLB to CLBCLB to CLB–– LocalLocal–– GlobalGlobal–– Timing Timing –– Clock networksClock networks

•• Propagation delay timing for interconnect 1st order modelPropagation delay timing for interconnect 1st order model–– Wired interconnect tWired interconnect tPLHPLH–– Programmable interconnect tProgrammable interconnect tPLHPLH

•• Design Example of 8Design Example of 8--bit Ripple Carry Adderbit Ripple Carry Adder–– CPLD DesignCPLD Design

•• Full AdderFull Adder–– FPGA DesignFPGA Design

•• 22--bit adder subcomponentbit adder subcomponent•• LUT programming (Combining LUTs for more input variables)LUT programming (Combining LUTs for more input variables)•• Programmable interconnect Programmable interconnect

–– Adder Using VHDLAdder Using VHDL

Exam Review OutlineExam Review Outline

•• Design FlowDesign Flow–– DesignerDesigner

•• Write HDL CodeWrite HDL Code•• SimulateSimulate•• ConstraintsConstraints

–– CAD ToolCAD Tool•• SynthesisSynthesis•• Translate/MapTranslate/Map•• Place and RoutePlace and Route•• Generate Programming FileGenerate Programming File•• Download bit fileDownload bit file

•• Xilinx FPGA and CPLDXilinx FPGA and CPLD–– Spartan IIE FPGA ArchitectureSpartan IIE FPGA Architecture

•• FPGA FabricFPGA Fabric•• I/O BlockI/O Block•• CLB and CLB SliceCLB and CLB Slice•• Product FamilyProduct Family

–– CoolRunner XPLA3 ArchitectureCoolRunner XPLA3 Architecture•• FeaturesFeatures•• Architecture Block DiagramArchitecture Block Diagram•• PLA Logic InputsPLA Logic Inputs•• Logic Block (MacroBlock)Logic Block (MacroBlock)•• I/O CellI/O Cell•• MacroCellMacroCell•• Timing ModelTiming Model

•• XilinxXilinx Spartan 3 Spartan 3 –– Nexys BoardNexys Board

Exam Review OutlineExam Review Outline

•• Computer Systems, Processors, and TerminologyComputer Systems, Processors, and Terminology–– Custom HW Custom HW –– ASIC, VLSI, ASIC, VLSI, ……–– Processor vs. MicroprocessorProcessor vs. Microprocessor–– Microcomputer vs. MicrocontrollerMicrocomputer vs. Microcontroller–– Embedded system design processEmbedded system design process

•• RequirementsRequirements•• SpecificationsSpecifications•• ArchitectureArchitecture•• ComponentsComponents•• System IntegrationSystem Integration

–– Embedded SystemEmbedded System•• Characteristics: Complex Algorithms, user interface, realCharacteristics: Complex Algorithms, user interface, real--time, multitime, multi--raterate•• Costs: Cost of goods, mfg cost, development costCosts: Cost of goods, mfg cost, development cost•• Challenges Challenges

–– Hardware performance vs. CostHardware performance vs. Cost–– Code Space/ Code DensityCode Space/ Code Density–– Need to meet realNeed to meet real--time demandstime demands–– Minimize power consumptionMinimize power consumption–– Design for upgradeDesign for upgrade--abilityability–– VerificationVerification–– ReliabilityReliability

Exam Review Outline Exam Review Outline –– lecture 4lecture 4Embedded Systems and Embedded Systems and MicroBlazeMicroBlaze Computer SystemComputer System

•• Embedded Systems ContinuedEmbedded Systems Continued–– Computer System Block DiagramComputer System Block Diagram–– System on Chip System on Chip ––SoCSoC

•• Processor in ASIC or FPGA with Softcore processorProcessor in ASIC or FPGA with Softcore processor–– Programmers model Programmers model –– Registers, Condition Codes and Instruction Set Registers, Condition Codes and Instruction Set

ArchitectureArchitecture–– Why is it important to know ISA?Why is it important to know ISA?–– Computer ClassificationComputer Classification

•• ArchitectureArchitecture–– Von Neuman / Princeton ArchitectureVon Neuman / Princeton Architecture–– Harvard ArchitectureHarvard Architecture–– DSPDSP’’s s

•• RISC vs. CISCRISC vs. CISC

•• EDK computer systemEDK computer system–– MicroBlaze ProcessorMicroBlaze Processor–– Busses (Busses (ILMB, DLMB, IOPB and DOPB)ILMB, DLMB, IOPB and DOPB)–– MicroBlaze Memory SystemMicroBlaze Memory System

•• Memory Controllers and BRAMMemory Controllers and BRAM–– Memory Mapped I/OMemory Mapped I/O–– IP CoresIP Cores–– GPIO Programming Input and Output DevicesGPIO Programming Input and Output Devices

Exam Review OutlineExam Review Outline

•• Base Address Base Address •• Memory Mapped Registers (Data Register and Data Direction RegistMemory Mapped Registers (Data Register and Data Direction Register)er)•• I/O InstructionsI/O Instructions

–– Software functions to read and write MicroBlaze memory locationsSoftware functions to read and write MicroBlaze memory locations•• Xio_In32( ); and Xio_Out32( );Xio_In32( ); and Xio_Out32( );•• xparameters.hxparameters.h and and xio.hxio.h•• DIO5 I/O ControllerDIO5 I/O Controller

–– Bus Based Interface Between FPGA and I/O ControllerBus Based Interface Between FPGA and I/O Controller–– Computer SystemComputer System–– Bus Write CycleBus Write Cycle

Timing DiagramTiming DiagramAlgorithm to implement using GPIO and MicroBlazeAlgorithm to implement using GPIO and MicroBlaze

–– DIO5 Memory Map of I/O DevicesDIO5 Memory Map of I/O Devices–– LCD initialization RoutineLCD initialization Routine–– LCD Display CharactersLCD Display Characters

–– Nexys interface to LCD and peripherals (buttons and Nexys interface to LCD and peripherals (buttons and ledsleds))

Exam Review OutlineExam Review Outline

•• Embedded Developers Kit Design FlowEmbedded Developers Kit Design Flow–– Hardware SystemHardware System

•• Add CoresAdd Cores•• Bus ConnectionBus Connection•• Memory MapMemory Map•• Port ConnectionsPort Connections•• ParametersParameters•• User ConstraintsUser Constraints

–– Software SystemSoftware System•• Device Driver Interface (Xio_Out, Xio_In, Device Driver Interface (Xio_Out, Xio_In, ……))•• Main Code using Main Code using ““CC””•• CompileCompile•• Generate BitstreamGenerate Bitstream•• Update BitstreamUpdate Bitstream•• Download codeDownload code

Exam Review Outline Exam Review Outline –– lecture 5lecture 5Xilinx Embedded Developers KitXilinx Embedded Developers Kit

Exam Review Outline Exam Review Outline –– lecture 6lecture 6MicroBlazeMicroBlaze Instruction set, Architecture, Performance, and InterruptsInstruction set, Architecture, Performance, and Interrupts

•• MicroBlazeMicroBlaze–– Programmers ModelProgrammers Model–– Data TypesData Types–– Instruction SetInstruction Set–– Program Counter and Machine State RegisterProgram Counter and Machine State Register–– General Purpose RegistersGeneral Purpose Registers–– Instruction formatsInstruction formats

•• Big Endian / Little EndianBig Endian / Little Endian•• PipeliningPipelining

–– Overlapped executionOverlapped execution–– Performance (Latency, throughput, IPC, and CPI)Performance (Latency, throughput, IPC, and CPI)–– MicroBlaze Pipeline (FMicroBlaze Pipeline (F-->D>D-->Execute)>Execute)–– Data Dependency HazardsData Dependency Hazards–– Control HazardsControl Hazards–– Delayed BranchesDelayed Branches

Exam Review Outline Exam Review Outline –– lecture 7lecture 7Timers and CountersTimers and CountersInterruptsInterrupts

•• Asynchronous event that allows device to interrupt CPU and transAsynchronous event that allows device to interrupt CPU and transfer control over to an interrupt fer control over to an interrupt service routine.service routine.

•• Foreground task (main loop)Foreground task (main loop)•• Interrupt Service Routing (ISR) or Interrupt Handler Interrupt Service Routing (ISR) or Interrupt Handler •• Interrupt and AcknowledgeInterrupt and Acknowledge•• Hardware interface for interruptHardware interface for interrupt•• Interrupt process at HW level Interrupt process at HW level

•• CPU Initializes and enables interrupt device and unmasks interruCPU Initializes and enables interrupt device and unmasks interruptspts•• External Interrupt request generatedExternal Interrupt request generated

–– Possibly on chip peripheral devicePossibly on chip peripheral device–– Possibly external devicePossibly external device

•• CPU typically finishes current instructionCPU typically finishes current instruction–– Some instructions are interruptible Some instructions are interruptible

•• Some CPUSome CPU’’s perform HW context save (if not context save is responsibilitys perform HW context save (if not context save is responsibility of ISR)of ISR)•• CPUCPU’’s typically disable interrupts automatically s typically disable interrupts automatically •• Return address stored (on stack or in dedicated register)Return address stored (on stack or in dedicated register)•• Branch to interrupt service routine: Fetch Interrupt Vector (addBranch to interrupt service routine: Fetch Interrupt Vector (address of interrupt service routine) or address of instruction ress of interrupt service routine) or address of instruction

in Jump table and put this address into the PCin Jump table and put this address into the PC•• Execute the interrupt service routineExecute the interrupt service routine•• ISR must clear interrupt flag (acknowledge interrupt)ISR must clear interrupt flag (acknowledge interrupt)•• Restore Context if not handled in HWRestore Context if not handled in HW•• RTI RTI -- Return from interrupt instruction :Restores CPU context includiReturn from interrupt instruction :Restores CPU context including condition codes and Branches to return addressng condition codes and Branches to return address

•• Debugging with interruptsDebugging with interrupts•• Multiple Interrupts and Interrupt Priorities Multiple Interrupts and Interrupt Priorities •• Maskable vs. NonMaskable vs. Non--Maskable interruptsMaskable interrupts•• Handling multiple interrupts using an OR gateHandling multiple interrupts using an OR gate•• Interrupt controllers and multiple interrupt devicesInterrupt controllers and multiple interrupt devices•• Interrupt overheadInterrupt overhead•• Comparison of Interrupts to Polling algorithmsComparison of Interrupts to Polling algorithms

•• Sampling theorySampling theory–– Sampling FrequencySampling Frequency–– ResolutionResolution

•• AnalogAnalog--toto--Digital ConvertersDigital Converters–– Sample and HoldSample and Hold–– Summing opSumming op--amp circuitamp circuit

•• DigitalDigital--toto--Analog ConvertersAnalog Converters–– Analog Devices AD7303 ArchitectureAnalog Devices AD7303 Architecture–– AD7303 IP Core and device driversAD7303 IP Core and device drivers–– Software for digitalSoftware for digital--toto--analog conversionanalog conversion–– DigilentDigilent AIO1 Interface Board setup and schematicAIO1 Interface Board setup and schematic

•• Interfacing SensorsInterfacing Sensors–– Resolution and Selection of VResolution and Selection of VREFREF–– ADC digital outputADC digital output–– LM35 Temperature SensorLM35 Temperature Sensor

Exam Review Outline Exam Review Outline –– lecture 8lecture 8DigitalDigital--toto--Analog Conversion and AnalogAnalog Conversion and Analog--toto--Digital ConversionDigital Conversion

•• Data ManagementData Management–– FIFOFIFO–– StackStack–– Software Implementation of FIFOs and StacksSoftware Implementation of FIFOs and Stacks

•• I/O Algorithms for UART with Keyboard and Monitor AlgorithmI/O Algorithms for UART with Keyboard and Monitor Algorithm–– I/O with busy waiting and Memory Mapped I/O I/O with busy waiting and Memory Mapped I/O

•• How it works How it works •• Algorithm (flow chart)Algorithm (flow chart)•• C code implementationC code implementation

–– I/O with interrupts I/O with interrupts •• I/O Buffer QueueI/O Buffer Queue

–– With separate input and output device interrupt handlers that caWith separate input and output device interrupt handlers that can n run at different speeds we need a place to store incoming data.run at different speeds we need a place to store incoming data.

–– FIFO or circular queueFIFO or circular queue–– Head and tail pointersHead and tail pointers–– Storing and removing charactersStoring and removing characters–– Queue empty, queue full, number of characters in queueQueue empty, queue full, number of characters in queue

•• How it works How it works •• Algorithm (flow chart)Algorithm (flow chart)•• C code implementationC code implementation

–– Task processing with ISRsTask processing with ISRs

Exam Review Outline Exam Review Outline –– lecture 9lecture 9Serial I/O and Programming Input and OutputSerial I/O and Programming Input and Output

•• Switches and Pushbuttons to digital logic (circuit and resistancSwitches and Pushbuttons to digital logic (circuit and resistance)e)•• Debouncing Switches and PushbuttonsDebouncing Switches and Pushbuttons

–– SR latchSR latch–– RC filterRC filter–– Software Debounce algorithmSoftware Debounce algorithm

•• Keypad Keypad –– Direct wired keypadDirect wired keypad–– Matrix keypadMatrix keypad

•• OperationOperation•• benefitbenefit

•• Keyboard Keyboard •• PC Keyboard (microcontroller, serial interface, scan codes)PC Keyboard (microcontroller, serial interface, scan codes)

–– PS2 portPS2 port–– Bidirectional Clock and dataBidirectional Clock and data–– Master SlaveMaster Slave–– Communication with Keyboard and HostCommunication with Keyboard and Host–– Timing diagramTiming diagram

•• Scanned Keyboard: Benefits and IssuesScanned Keyboard: Benefits and Issues•• MouseMouse

–– UnidirectionalUnidirectional–– Timing diagramTiming diagram

•• TouchTouch--screen Displays screen Displays –– Vertical and Horizontal PositionVertical and Horizontal Position

Exam Review Outline Exam Review Outline –– lecture 10lecture 10Other I/O DevicesOther I/O Devices

•• LEDs LEDs •• II--V Characteristics V Characteristics •• Circuit and current limiting resisterCircuit and current limiting resister•• 77--Segment DisplaysSegment Displays

–– 77--segment codesegment code–– Circuit elementsCircuit elements–– Raster scanRaster scan

•• Cathode Ray Tube (CRT) Cathode Ray Tube (CRT) •• Directly driven (Data, Horizontal and Vertical Deflection)Directly driven (Data, Horizontal and Vertical Deflection)•• Frame buffer device driverFrame buffer device driver•• VGA ControllerVGA Controller

–– Interface/ConnectorInterface/Connector–– Video RAMVideo RAM

•• Character LCD Displays Character LCD Displays –– Controller and LCDController and LCD–– Addressing ModesAddressing Modes–– ASCII CharactersASCII Characters–– DRAM BufferDRAM Buffer–– Font TableFont Table–– Hardware interfaceHardware interface

•• Graphical LCD Displays Graphical LCD Displays –– Pixel by Pixel Control RGBPixel by Pixel Control RGB

Exam Review OutlineExam Review Outline

•• External memory controllersExternal memory controllers–– SRAM structureSRAM structure–– SRAM memory block SRAM memory block –– datadata--in and datain and data--out busses, bidirectional data busout busses, bidirectional data bus–– Memory read and write signals Memory read and write signals –– proper assertion of control signalsproper assertion of control signals–– OPB EMC coreOPB EMC core

•• Parameter configurationParameter configuration•• Register modelRegister model•• Timing of read and write cyclesTiming of read and write cycles

•• Serial peripheral InterfaceSerial peripheral Interface–– Four concepts: Serial, synchronous, MasterFour concepts: Serial, synchronous, Master--slave protocol, data exchangeslave protocol, data exchange–– IO signalsIO signals–– MasterMaster--slave configurationslave configuration–– SPI modeSPI mode

•• Clock polarityClock polarity•• Clock phaseClock phase

–– OPB SPI coreOPB SPI core•• SCK, slave select, MOSI, MISO signalsSCK, slave select, MOSI, MISO signals•• Register modelRegister model

Exam Review Outline Exam Review Outline –– lecture 11lecture 11Other Peripheral Devices: External Memory controller and Serial Other Peripheral Devices: External Memory controller and Serial Peripheral InterfacesPeripheral Interfaces

•• Heat Generation depends on Power ConsumptionHeat Generation depends on Power Consumption•• Battery Life depends on Energy ConsumptionBattery Life depends on Energy Consumption•• In CMOS what causes power consumptionIn CMOS what causes power consumption

–– StaticStatic•• Leakage CurrentLeakage Current•• Sub Threshold CurrentSub Threshold Current•• Passive Current dissipationPassive Current dissipation

–– DynamicDynamic•• Switching CurrentSwitching Current•• Charging and Discharging Capacitive loadsCharging and Discharging Capacitive loads

•• PPcapcap = = ααCCeffeffVVdddd22f, Ef, Ecapcap = = ααCCeffeffVVdddd

22

•• Methods to Reduce Power and Energy ConsumptionMethods to Reduce Power and Energy Consumption•• Power managementPower management

–– StaticStatic–– DynamicDynamic–– Power management state machinesPower management state machines–– StrongARM ExampleStrongARM Example

Exam Review Outline Exam Review Outline –– lecture 12lecture 12Power Consumption and EnergyPower Consumption and Energy

1919

•• Microcontroller market segmentsMicrocontroller market segments•• Microcontrollers vs. MicroprocessorsMicrocontrollers vs. Microprocessors•• Market analysisMarket analysis•• Alternate Microcontroller DevicesAlternate Microcontroller Devices

–– PIC PIC –– AtmelAtmel–– Mot HC12Mot HC12–– Mot 68000Mot 68000

•• DSPsDSPs–– ApplicationsApplications–– What is a digital signal processorWhat is a digital signal processor–– TMS 320TMS 320–– DSP5600DSP5600

Exam Review Outline Exam Review Outline –– lecture 13lecture 13Survey of Microcontroller Market and Common MicrocontrollersSurvey of Microcontroller Market and Common Microcontrollers

•• IEEE Code of EthicsIEEE Code of Ethics•• Engineering ethics issuesEngineering ethics issues

–– CheatingCheating–– ResponsibilityResponsibility–– ScapegoatingScapegoating–– Intellectual PropertyIntellectual Property–– Whistle BlowingWhistle Blowing–– OutsourcingOutsourcing–– LayoffsLayoffs–– Engineering integrityEngineering integrity–– Conflict of interestsConflict of interests–– GiftsGifts–– Product ReadinessProduct Readiness–– DiscriminationDiscrimination

•• TheracTherac--25 Case25 Case–– PlayersPlayers–– IncidentsIncidents–– InIn--class group discussionclass group discussion

Exam Review Outline Exam Review Outline –– lecture 14lecture 14Ethics in EngineeringEthics in Engineering

Laboratory ReviewLaboratory Review

•• Lab 1 Digital Clock Design Using Lab 1 Digital Clock Design Using Programmable Logic and VHDLProgrammable Logic and VHDL–– Nexys/ISE tutorial exp 0Nexys/ISE tutorial exp 0–– Review of VHDL and Review of VHDL and XilinxXilinx ISE, ISE, MicroSimMicroSim–– Digital clock requirementsDigital clock requirements–– Development processDevelopment process–– Laboratory proceduresLaboratory procedures

Laboratory ReviewLaboratory Review

•• Lab 2 Lab 2 MicroBlazeMicroBlaze ““Hello WorldHello World”” and and Embedded Development Kit (EDK)Embedded Development Kit (EDK)–– EDK 9.1iEDK 9.1i--nexys board tutorialnexys board tutorial–– ““CC”” programming reviewprogramming review–– GPIO GPIO –– Interface to LCDInterface to LCD

•• DocumentationDocumentation•• Interface protocolInterface protocol•• Timing diagramTiming diagram

Laboratory ReviewLaboratory Review

•• Lab 3 Lab 3 MicroBlazeMicroBlaze Digital Clock and the Digital Clock and the Embedded Development KitEmbedded Development Kit–– Timer/counter peripheralTimer/counter peripheral–– InterruptsInterrupts–– Nexys buttonsNexys buttons–– Use of LCD driver codeUse of LCD driver code–– Demo: testing <Demo: testing <--> specifications> specifications

Laboratory ReviewLaboratory Review

•• Lab 4 Lab 4 MicroBlazeMicroBlaze Function Generator Function Generator DesignDesign–– SPISPI–– PMOD DA2PMOD DA2–– Analog instrumentation for verificationAnalog instrumentation for verification–– Reuse of C code, peripherals Reuse of C code, peripherals

Laboratory ReviewLaboratory Review

•• Lab 5 Computer Application Final Design ProjectLab 5 Computer Application Final Design Project–– Additional peripheral interface: ADC, PS/2Additional peripheral interface: ADC, PS/2–– Additional interface protocolsAdditional interface protocols–– Building on knowledge gained in previous labsBuilding on knowledge gained in previous labs–– Demonstrate ability to find interface informationDemonstrate ability to find interface information–– Hardware/software tradeoff in designHardware/software tradeoff in design–– Minimal hardware/software resourcesMinimal hardware/software resources–– ““CC”” coding style coding style –– Oral presentationOral presentation–– Proper embedded system project documentationProper embedded system project documentation