Review for Midterm: CPE 329 Fall 2007

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Review for Midterm: CPE 329 Fall 2007. Lectures 1-7, Chapters 1 & 2, Labs 1-2 Exam Review Outlines Homework problems ISE/EDK technology Digilent Nexys board technology Not held accountable for specifics of Digilent D2FT-DIO5 technology, just principles - PowerPoint PPT Presentation

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Review for Midterm: CPE 329 Fall 2007Lectures 1-7, Chapters 1 & 2, Labs 1-2Exam Review OutlinesHomework problemsISE/EDK technologyDigilent Nexys board technologyNot held accountable for specifics of Digilent D2FT-DIO5 technology, just principlesNo coding, just pseudo code (no syntax)One side page of reference notes CalculatorExam Review Outline: lecture 1Course DescriptionCourse Learning ObjectivesTopics CoveredPrerequisite materialCourse MaterialLab OverviewDevelopment Environment (CAD Tools)Lab EquipmentProcessorLab ExperimentsExperiment 1 Hardware-Based Digital ClockExperiment 2 MicroBlaze Hello World!Experiment 3 Microcontroller-Based Digital ClockExperiment 4 Function GeneratorExperiment 5 Final Design ProjectExam Review Outline: lecture 2Taxonomy of Digital SystemsAdvantages and Disadvantages of each category (Cost, performance, ease of design, customization, configurability, integration, number of transistors)Semiconductor Technology TrendsMoores Law Number of transistors per die doubles every couple of years (historical data) http://www.intel.com/research/silicon/mooreslaw.htmITRS Future ProjectionIncrease in the number of practicing engineers per yearMust work at higher levels of abstractionIncreasing levels of abstraction for HW and SWHardware Software Co-designHomeworkIn class we talked about field and factory programmable gate arrays. Which type of gate array would have better performance? State the two primary reasons given in class that one will perform better than the other.Hardware-based implementations typically have a performance benefit over stored-program digital systems. Explain why this is true? Given that hardware-based implementations typically have a performance benefit over stored-program digital systems give three reasons that most embedded systems use either microprocessors or microcontrollers?VHDL Alarm ClockUsing the clock you designed for lab 1 we would like to add an alarm function. The system requirement for the alarm function is to use another pushbutton to enter alarm mode. In alarm mode the alarm time should be displayed on the LCD and the hours and minutes pushbuttons should advance the hours and minutes of the alarm setting just as it did while setting the clock. There will be a module that asserts a logic signal called BUZZ if the current time matches the alarm time. Reusing the modules that you used for lab 1 (Time_Keeper, Arbiter, and HEX2BCD as shown in the figure on the following page) draw a hardware diagram with the additional modules needed to add the alarm function and briefly describe (1-2 sentences / module) how each block should function.In the first lab many students noticed that it was cumbersome to set the clock if the minutes and hours incremented every second during the set function. Determine how to have the set function increment every 0.5 seconds. Assume that you are supposed to minimize the changes to your current design and you can only use one system clock. Be sure to describe the conditions that are needed to increment the seconds, minutes, hours, and am/pm when in timekeeping mode.In the lab we designed a Digital Clock using VHDL that was clocked with a 50MHz Epson oscillator. The frequency tolerance for the oscillator is: f/f = +/- 50x10-6. Explain what are the sources of error in your digital clock and determine the maximum error that the clock would have after running for 1 day.HomeworkVHDL Design: Analyze the following VHDL code to answer the questions below:entity state_machine isport(clk,S: in std_logic; z:out std_logic);end state_machinearchitecture design of state_machine issignal NS : std_logic_vector ( 1 downto 0) :=00;beginsynch_proc: process (clk, S)beginif (clkevent and clk=1) thenif(S=0) thenif (NS = 00) then NS HomeworkIn the Introduction to Digital Systems chapter of the supplemental material digital systems were first divided into two different categories. List the two categories and identify which one generally has higher performance. Also explain why this type of digital system has higher performance?Does a factory programmed gate array or a field programmable gate array typically have better performance? List two factors that contribute to a performance advantage of one over the other. You are asked to implement an algorithm using the tools available to you in the CPE 329 lab. The application requires the highest-performance design that you can download into the Digilent D2FT board. You notice that the algorithm is computationally intense but does not have a significant amount of inherent parallelism. Describe which approach and design tool you would select. Also, explain why you chose this approach.Does a factory programmed gate array or a field programmable gate array typically use more silicon die area to implement a given VHDL design? List two factors that contribute to a area advantage of one over the other. Exam Review Outline lecture 3History of Integrated CircuitsAdvantages of CPLDsProgrammable Elements to connect nets or configure hardware devicesOne-time-programmable (OTP) Fuse/AntifuseRe-programmableVolatile (SRAM)Non-Volatile (EEPROM, Flash)CPLD Architecture Functional BlocksSPLD like configurable logic MacroCellMacroBlockProgrammable InterconnectI/O BlocksFPGA ArchitectureFPGA Fabric Configurable Logic Block (Programmable MUX, Look Up Table, Pass Transistor)Programmable InterconnectI/O BlocksBlock RAM MemoryHardcore blocks (ie Multipliers, PowerPC)System on Chip (Soc) using Hardcore or Softcore ProcessorsExam Review OutlineProgrammable Interconnect (6-transistor junction)Direct CLB to CLBLocalGlobalTiming Clock networksPropagation delay timing for interconnect 1st order modelWired interconnect tPLHProgrammable interconnect tPLHDesign Example of 8-bit Ripple Carry AdderCPLD DesignFull AdderFPGA Design2-bit adder subcomponentLUT programming (Combining LUTs for more input variables)Programmable interconnect Adder Using VHDLExam Review OutlineDesign FlowDesignerWrite HDL CodeSimulateConstraintsCAD ToolSynthesisTranslate/MapPlace and RouteGenerate Programming FileDownload bit fileXilinx FPGA and CPLD Note: emphasis on Spartan 3 Spartan IIE FPGA ArchitectureFPGA FabricI/O BlockCLB and CLB SliceProduct FamilyCoolRunner XPLA3 ArchitectureFeaturesArchitecture Block DiagramPLA Logic InputsLogic Block (MacroBlock)I/O CellMacroCellTiming ModelHomework1.In class we talked about the migration from discrete logic to CPLDs. State three advantages of using CPLDs over discrete components.2.Explain the three ways that SRAM cells are used to configure the Xilinx Spartan2e FPGA.3.Calculate the fall-time for the Driver inverter in the circuit below whose output is routed through the programmable interconnect on an FPGA. Use the values supplied in the table to approximate Rp, Rn, and CL. Use the following definition of fall time: The time from when the input changes from a low to high logic value to the time when the output reaches 0.1Vdd. (Note: ln(0.1) -2.3, ln(0.9) -0.1).ValueComponent22 kRp11 kRn1x10-15 fCL4.Map the combinational function, F(X2,X1,X0)=X2 XOR X1 XOR X0, to the macroblock given below. Assume an anti-fuse programmable element in the AND-array and denote a grown fuse with an X. Indicate the configuration memory required such that F is routed as an output to the I/O pin in the figure. Assume an SRAM-based programmable element (shaded boxes) for the MUX control and use the following notation: 1 = logic high, 0 = logic low, and D = dont care.X0X1X2DQto AND array10Clockglobal OEF10Ss1s00100111005.(a) Given the programmable interconnect structure shown below identify the best routing from the output of CLB 1 to the input of CLB 8 to achieve the minimum interconnect delay. Do so by darkening the best route you determined. All of the programmable interconnects shown use the same type of pass transistor. You can assume the resistance in the wire is approximately zero. (b) What circuit parameters affect the interconnect delay? 6.One student in a prior class asked how are the System Gate Equivalents determined for FPGAs since a configurable logic block uses look up tables not logic gates for computation. Estimate how many System Gate Equivalents one LUT has given the following data from the Xilinx Spartan-2E Spec. Assume that all of the LUTs in an FPGA count for 10% of the System Gates.Device System Gate Range Total CLBs Slices/CLB LUT(16x1b)/SliceXC2S300E 93K 300K 1,536 2 2123456789ABCDEExam Review Outline lecture 4Computer Systems, Processors, and TerminologyCustom HW ASIC, VLSI, Processor vs. MicroprocessorMicrocomputer vs. MicrocontrollerEmbedded system design processRequirementsSpecificationsArchitectureComponentsSystem IntegrationEmbedded SystemCharacteristics: Complex Algorithms, user interface, real-time, multi-rateCosts: Cost of goods, mfg cost, development costChallenges Hardware performance vs. CostCode Space/ Code DensityNeed to meet real-time demandsMinimize power consumptionDesign for upgrade-abilityVerificationReliabilityExam Review OutlineEmbedded Systems ContinuedComputer System Block DiagramSystem on Chip SoCProcessor in ASIC or FPGA with Softcore processorProgrammers model Registers, Condition Codes and Instruction Set ArchitectureWhy is it important to know ISA?Computer ClassificationArchitectureVon Neuman / Princeton ArchitectureHarvard ArchitectureDSPs RISC vs. CISCEDK computer systemMicroBlaze ProcessorBusses (ILMB, DLMB, IOPB and DOPB)MicroBlaze Memory SystemMemory Controllers and BRAMMemory Mapped I/OIP CoresGPIO Programming Input and Output DevicesExam Review OutlineBase Address Memory Mapped Registers (Data Register and Data Direction Register)I/O InstructionsSoftware functions to read and write MicroBlaze memory locationsXio_In32( ); and Xio_Out32( );DIO5 I/O Controller (principles only)Bus Based Interface Between FPGA and I/O ControllerComputer SystemBus Write CycleTiming DiagramAlgorithm to implement using GPIO and MicroBlazeDIO5 Memory Map of I/O DevicesLCD initialization RoutineLCD Display CharactersNexys interface to LCD and peripherals (buttons and leds)HomeworkMicrocontrollers are often a hybrid of RISC and CISC architectures. List the characteristics discussed in lecture for each below?At the hardware level how would the MicroBlaze CPU set an 8-bit GPIO peripheral to be an input? Describe what happens at the hardware level between the CPU and the GPIO peripheral and NOT the device driver function call. Describe the uses of and differences between the OPB and the LMB busses? The Spartan IIe that we are using in the lab has 8k words of BRAM memory. The BRAM is dual ported and has an address space of 0x0000 - 0x1fff. If the Instruction Memory Controller base address is set to 0x0000 and the base address for the Data Memory Controller is set to 0x1000 determine:What physical address would be read if the MicroBlaze fetched an instruction from address 0x0100?What physical address would be read if MicroBlaze fetched a data operand with data address of 0x1200?HomeworkThe following code is similar to the code in the blinker tutorial and shows how to set the lower 8 LEDs on the DIO5 board. Show how the code should be changed to read the lower 8 pushbuttons and store the result into the pb variable. Xuint32 XGpio_DiscreteRead (XGpio *InstancePtr, unsigned Channel)Read state of discretes for the specified GPIO channnel.Parameters: InstancePtr is a pointer to an XGpio instance. Channel contains the channel of the GPIO (1 or 2).Returns: Current copy of the discretes register.#define BtnLowAddr 0x00#define BtnHighAddr 0x01#define LedLowAddr 0x00#define LedHighAddr 0x01main(){XGpio led_gpio, data_gpio, addr_gpio, cs_gpio, oe_gpio, we_gpio;unsigned pb;XGpio_Initialize(&data_gpio, XPAR_DIO_DATA_DEVICE_ID);XGpio_Initialize(&addr_gpio, XPAR_DIO_ADDR_DEVICE_ID);XGpio_Initialize(&cs_gpio, XPAR_CS_N_DEVICE_ID);XGpio_Initialize(&oe_gpio, XPAR_OE_N_DEVICE_ID);XGpio_Initialize(&we_gpio, XPAR_WE_N_DEVICE_ID);XGpio_SetDataDirection(&addr_gpio, 1, 0);XGpio_SetDataDirection(&cs_gpio, 1, 0);XGpio_SetDataDirection(&oe_gpio, 1, 0);XGpio_SetDataDirection(&we_gpio, 1, 0);XGpio_SetDataDirection(&data_gpio, 1, 0);XGpio_DiscreteWrite(&oe_gpio, 1,1);XGpio_DiscreteWrite(&cs_gpio, 1,0);XGpio_DiscreteWrite(&we_gpio, 1,0);XGpio_DiscreteWrite(&addr_gpio, 1,LedLowAddr);XGpio_DiscreteWrite(&data_gpio, 1,0xAA);XGpio_DiscreteWrite(&we_gpio, 1,1)XGpio_DiscreteWrite(&cs_gpio, 1,1);} HomeworkWhat type of applications would benefit from a processor with a Harvard architecture? Explain how the application benefits from a processor with a Harvard architecture.Describe the uses of and differences between the OPB and the LMB busses?Draw a timing diagram that shows a read of the lower 8 pushbuttons through the DIO5 I/O Controller. Include all of the logic signals that connect to the DIO5 Board. You can assume that the pushbutton 4 is pushed and the rest of the pushbuttons are not pressed.What is the difference between a Harvard and Von Neumann/Princeton architecture? What type of architecture does the MicroBlaze use?MicroBlaze Memory System: Draw the architecture of the MicroBlaze memory system used in Experiments 2 and 3. Provide values for base address registers where applicable. I/O Controller Bus Cycles: In Experiments 2 and 3 you configured the MicroBlaze system with five GPIOs for the data bus, the address bus, and three control signals to communicate with the I/O Controller programmed in the CoolRunner CPLD on the DIO5 board. Write a C function turn_on_leds() that will turn on all 16 LEDs on the DIO5 board using this same MicroBlaze system. The header file for the xparameters.h and the DIO5 Default Circuit Memory Map are provided on the next page.In Experiments 2 and 3 you configured the MicroBlaze system with five GPIOs for the data bus, the address bus, and three control signals to communicate with the I/O Controller programmed in the CoolRunner CPLD on the DIO5 board. Write a C function display_message() that will write CPE 329! to the LCD screen. on the DIO5 board using this same MicroBlaze system. You may call the function configure_LCD() to initialize the LCD screen and configure it for entry mode. You can use the header file xparameters.h provided for lab 2 and 3.You need to select either a PowerPC (RISC) or Motorola 68000 (CISC) microcontroller for a particular design application. Both have adequate performance and comparable cost. The application will require external memory so minimizing the code space is critical. Which microcontroller will you select? Explain why you selected the microcontroller that you did. HomeworkAce engineer proposes writing a high performance OPB bus. Aces goal is to create an OPB bus equivalent with all of the same functionality as currently is available but allow single cycle bus transactions. Are these goals feasible? If so, describe one way the OPB bus performance can be improved.If our development board was running at 100MHz and the Xio_Write32() and Xio_In32() functions calls only take one clock cycle to execute, then would we need to make any changes in our bus read cycle code? Refer to the information in the DIO5 reference manual?You are asked to add a second DIO5 board to the lab setup so that you have two LCD displays to output messages. Now you are required to write Hello World! onto one screen as before, and write CPE 329 Rules! on the other LCD Screen. Your design requirements include using the fewest number of Slices and Code space as before. Draw the system architecture for the new system. Be sure to include the number of bits for each GPIO device. Describe how the code would have to change to accommodate the new hardware system and requirements as compared to the default computer system in the tutorial. Your answer can be in bullet format but you must use sufficient detail to carefully describe the software algorithms. Given the MicroBlaze memory map used in the blinker tutorial for the computer system write the minimum amount of C code to only light the lower four LEDs on the DIO5 board. Do not use any pound defined words in your code (use hex numbers for function parameters) or assume any initialization has been done. Exam Review Outline lecture 5Embedded Developers Kit Design FlowHardware SystemAdd CoresBus ConnectionMemory MapPort ConnectionsParametersUser ConstraintsSoftware SystemDevice Driver Interface (Xio_Out, Xio_In, )Main Code using CCompileGenerate BitstreamUpdate BitstreamDownload codeEDK Nexys TutorialHomeworkWhen using the EDK explain what happens when you execute the following commands?Generate Netlist?Generate Libraries? Update BitStream? Describe what happens in the mapping stage of the Hardware design flow? Describe what the input is for the mapping process and what is generated by the mapping process.You are asked to implement an algorithm using the tools available to you in the CPE 329 lab. The application requires the highest-performance design that you can download into the Digilent D2FT board. You notice that the algorithm is computationally intense but does not have a significant amount of inherent parallelism. Describe which approach and design tool you would select. Also, explain why you chose this approach.Exam Review Outline lecture 6MicroBlazeProgrammers ModelData TypesInstruction SetProgram Counter and Machine State RegisterGeneral Purpose RegistersInstruction formatsBig Endian / Little EndianPipeliningOverlapped executionPerformance (Latency, throughput, IPC, and CPI)MicroBlaze Pipeline (F->D->Execute)Data Dependency HazardsControl HazardsDelayed BranchesExam Review Outline lecture 7InterruptsAsynchronous event that allows device to interrupt CPU and transfer control over to an interrupt service routine.Foreground task (main loop)Interrupt Service Routing (ISR) or Interrupt Handler Interrupt and AcknowledgeHardware interface for interruptInterrupt process at HW level CPU Initializes and enables interrupt device and unmasks interruptsExternal Interrupt request generatedPossibly on chip peripheral devicePossibly external deviceCPU typically finishes current instructionSome instructions are interruptible Some CPUs perform HW context save (if not context save is responsibility of ISR)CPUs typically disable interrupts automatically Return address stored (on stack or in dedicated register)Branch to interrupt service routine: Fetch Interrupt Vector (address of interrupt service routine) or address of instruction in Jump table and put this address into the PCExecute the interrupt service routineISR must clear interrupt flag (acknowledge interrupt)Restore Context if not handled in HWRTI - Return from interrupt instruction :Restores CPU context including condition codes and Branches to return addressDebugging with interruptsMultiple Interrupts and Interrupt Priorities Maskable vs. Non-Maskable interruptsHandling multiple interrupts using an OR gateInterrupt controllers and multiple interrupt devicesInterrupt overheadComparison of Interrupts to Polling algorithmsHomework1.Determine the number of cycles from the time the first SUB instruction is fetched until the last BNE instruction completes execution and the CPI for the following MicroBlaze assembly code if the BNE branch is taken 1 times? Assume the SUB instruction execution stage takes 1 cycle to execute and the BNE takes the number of cycles described in lecture.Loop:SUB r3, r3, 1SUB r1, r1, 4SUB r2, r2, 8BNEI r3, loop_offset2.The semantics for the MicroBlaze Instruction BEQ and BEQD are both the same {if Ra=0: PC:=PC + Rb}. What is the difference between the two branch instructions? When would BEQD be used and why would it? Be specific. 3.List three specific items that contribute to interrupt overhead. 4.Explain why the EDK has an Interrupt Controller IP Core? Be certain to discuss the advantages that the Interrupt Controller IP Core would have compared to the simple OR gate approach discussed in lecture.5.Determine the state of the carry bit and the Registers R1, R2, and R3 after the following MicroBlaze assembly instruction is executed if R1 = 0x0f000000, R2 = 0xff000000, R3 = 0x8f000000 and C=0 before the instruction is executed. Also show the RTL description of the instruction. ADDKC R1, R2, R3