Review for Midterm: CPE 329 Fall 2007 jharris/courses/329f07/midterm...Review for Midterm: CPE 329 Fall 2007 ... Explain why this is true? 3. Given that hardware-based implementations typically have a performance benefit over stored-program digital systems give three reasons that most embedded systems use either ... parallelism. Describe which approach and design tool you would select. Also,
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Review for Midterm: CPE 329 Fall 2007Review for Midterm: CPE 329 Fall 2007
Lectures 1Lectures 1--7, Chapters 1 & 2, Labs 17, Chapters 1 & 2, Labs 1--22 Exam Review OutlinesExam Review Outlines Homework problemsHomework problems ISE/EDK technologyISE/EDK technology DigilentDigilent NexysNexys board technologyboard technology
Not held accountable for specifics of Not held accountable for specifics of DigilentDigilent D2FTD2FT--DIO5 technology, just principlesDIO5 technology, just principles
No coding, just pseudo code (no syntax)No coding, just pseudo code (no syntax) One side page of reference notes One side page of reference notes CalculatorCalculator
Course DescriptionCourse Description Course Learning ObjectivesCourse Learning Objectives Topics CoveredTopics Covered Prerequisite materialPrerequisite material Course MaterialCourse Material Lab OverviewLab Overview
Development Environment (CAD Tools)Development Environment (CAD Tools) Lab EquipmentLab Equipment ProcessorProcessor
Lab ExperimentsLab Experiments Experiment 1 HardwareExperiment 1 Hardware--Based Digital ClockBased Digital Clock Experiment 2 MicroBlaze Experiment 2 MicroBlaze Hello World!Hello World! Experiment 3 MicrocontrollerExperiment 3 Microcontroller--Based Digital ClockBased Digital Clock Experiment 4 Function GeneratorExperiment 4 Function Generator Experiment 5 Final Design ProjectExperiment 5 Final Design Project
Exam Review Outline: lecture 1Exam Review Outline: lecture 1
Taxonomy of Digital SystemsTaxonomy of Digital Systems Advantages and Disadvantages of each categoryAdvantages and Disadvantages of each category ((Cost, Cost,
performance, ease of design, customization, configurability, performance, ease of design, customization, configurability, integration, number of transistors)integration, number of transistors)
Semiconductor Technology TrendsSemiconductor Technology Trends MooreMoores Law Number of transistors per die doubles every s Law Number of transistors per die doubles every
couple of years (historical data) couple of years (historical data) http://www.intel.com/research/silicon/mooreslaw.htmhttp://www.intel.com/research/silicon/mooreslaw.htm
ITRS Future ProjectionITRS Future Projection Increase in the number of practicing engineers per yearIncrease in the number of practicing engineers per year Must work at higher levels of abstractionMust work at higher levels of abstraction
Increasing levels of abstraction for HW and SWIncreasing levels of abstraction for HW and SW Hardware Software CoHardware Software Co--designdesign
Exam Review Outline: lecture 2Exam Review Outline: lecture 2
HomeworkHomework1. In class we talked about field and factory programmable gate arrays. Which type of gate
array would have better performance? State the two primary reasons given in class that one will perform better than the other.
2. Hardware-based implementations typically have a performance benefit over stored-program digital systems. Explain why this is true?
3. Given that hardware-based implementations typically have a performance benefit over stored-program digital systems give three reasons that most embedded systems use either microprocessors or microcontrollers?
4. VHDL Alarm Clocka. Using the clock you designed for lab 1 we would like to add an alarm function. The system
requirement for the alarm function is to use another pushbutton to enter alarm mode. In alarm mode the alarm time should be displayed on the LCD and the hours and minutes pushbuttons should advance the hours and minutes of the alarm setting just as it did while setting the clock. There will be a module that asserts a logic signal called BUZZ if the current time matches the alarm time.
b. Reusing the modules that you used for lab 1 (Time_Keeper, Arbiter, and HEX2BCD as shown in the figure on the following page) draw a hardware diagram with the additional modules needed to add the alarm function and briefly describe (1-2 sentences / module) how each block should function.
5. In the first lab many students noticed that it was cumbersome to set the clock if the minutes and hours incremented every second during the set function. Determine how to have the set function increment every 0.5 seconds. Assume that you are supposed to minimize the changes to your current design and you can only use one system clock. Be sure to describe the conditions that are needed to increment the seconds, minutes, hours, and am/pm when in timekeeping mode.
6. In the lab we designed a Digital Clock using VHDL that was clocked with a 50MHz Epson oscillator. The frequency tolerance for the oscillator is: f/f = +/- 50x10-6. Explain what are the sources of error in your digital clock and determine the maximum error that the clock would have after running for 1 day.
HomeworkHomework7. VHDL Design: Analyze the following VHDL code to answer the questions below:
entity state_machine isport( clk,S : in std_logic;
z :out std_logic );end state_machinearchitecture design of state_machine issignal NS : std_logic_vector ( 1 downto 0) :=00;beginsynch_proc: process (clk, S)
beginif (clkevent and clk=1) then
if(S=0) thenif (NS = 00) then NS
HomeworkHomework8. In the Introduction to Digital Systems chapter of the supplemental material
digital systems were first divided into two different categories. List the two categories and identify which one generally has higher performance. Also explain why this type of digital system has higher performance?
9. Does a factory programmed gate array or a field programmable gate array typically have better performance? List two factors that contribute to a performance advantage of one over the other.
10.10. You are asked to implement an algorithm using the tools availablYou are asked to implement an algorithm using the tools available to you in the e to you in the CPE 329 lab. The application requires the highestCPE 329 lab. The application requires the highest--performance design that you performance design that you can download into the Digilent D2FT board. You notice that the can download into the Digilent D2FT board. You notice that the algorithm is algorithm is computationally intense but does not have a significant amount ocomputationally intense but does not have a significant amount of inherent f inherent parallelism. Describe which approach and design tool you would parallelism. Describe which approach and design tool you would select. Also, select. Also, explain why you chose this approach.explain why you chose this approach.
11.11. Does a factory programmed gate array or a field programmable gatDoes a factory programmed gate array or a field programmable gate array e array typically use more silicon die area to implement a given VHDL detypically use more silicon die area to implement a given VHDL design? List two sign? List two factors that contribute to a area advantage of one over the othefactors that contribute to a area advantage of one over the other. r.
History of Integrated CircuitsHistory of Integrated Circuits Advantages of CPLDsAdvantages of CPLDs Programmable Elements to connect nets or configure hardware deviProgrammable Elements to connect nets or configure hardware devicesces
OneOne--timetime--programmable (OTP) programmable (OTP) Fuse/AntifuseFuse/Antifuse ReRe--programmableprogrammable
Volatile (SRAM)Volatile (SRAM) NonNon--Volatile (EEPROM, Flash)Volatile (EEPROM, Flash)
CPLD Architecture Functional BlocksCPLD Architecture Functional Blocks SPLD like configurable logic SPLD like configurable logic
Programmable InterconnectProgrammable Interconnect I/O BlocksI/O Blocks
FPGA ArchitectureFPGA Architecture FPGA Fabric FPGA Fabric
Configurable Logic Block (Programmable MUX, Look Up Table, Pass Configurable Logic Block (Programmable MUX, Look Up Table, Pass Transistor)Transistor) Programmable InterconnectProgrammable Interconnect I/O BlocksI/O Blocks Block RAM MemoryBlock RAM Memory Hardcore blocks (ie Multipliers, PowerPC)Hardcore blocks (ie Multipliers, PowerPC)
System on Chip (Soc) using Hardcore or Softcore ProcessorsSystem on Chip (Soc) using Hardcore or Softcore Processors
Exam Review Outline Exam Review Outline lecture 3lecture 3
Programmable Interconnect (6Programmable Interconnect (6--transistor junction)transistor junction) Direct Direct CLB to CLBCLB to CLB LocalLocal GlobalGlobal Timing Timing Clock networksClock networks
Propagation delay timing for interconnect 1st order modelPropagation delay timing for interconnect 1st order model Wired interconnect tWired interconnect tPLHPLH Programmable interconnect tProgrammable interconnect tPLHPLH
Design Example of 8Design Example of 8--bit Ripple Carry Adderbit Ripple Carry Adder CPLD DesignCPLD Design
Full AdderFull Adder FPGA DesignFPGA Design
22--bit adder subcomponentbit adder subcomponent LUT programming (Combining LUTs for more input variables)LUT programming (Combining LUTs for more input variables) Programmable interconnect Programmable interconnect
Adder Using VHDLAdder Using VHDL
Exam Review OutlineExam Review Outline
Design FlowDesign Flow DesignerDesigner
Write HDL CodeWrite HDL Code SimulateSimulate ConstraintsConstraints
CAD ToolCAD Tool SynthesisSynthesis Translate/MapTranslate/Map Place and RoutePlace and Route Generate Programming FileGenerate Programming File Download bit fileDownload bit file
Xilinx FPGA and CPLDXilinx FPGA and CPLDNote: emphasis on Spartan 3 Note: emphasis on Spartan 3
Spartan IIE FPGA ArchitectureSpartan IIE FPGA Architecture FPGA FabricFPGA Fabric I/O BlockI/O Block CLB and CLB SliceCLB and CLB Slice Product FamilyProduct Family
CoolRunner XPLA3 ArchitectureCoolRunner XPLA3 Architecture FeaturesFeatures Architecture Block DiagramArchitecture Block Diagram PLA Logic InputsPLA Logic Inputs Logic Block (MacroBlock)Logic Block (MacroBlock) I/O CellI/O Cell MacroCellMacroCell Timing ModelTiming Model
Exam Review OutlineExam Review Outline
HomeworkHomework1. In class we talked about the migration from discrete logic to CPLDs. State three advantages
of using CPLDs over discrete components.
2. Explain the three ways that SRAM cells are used to configure the Xilinx Spartan2e FPGA.
3. Calculate the fall-time for the Driver inverter in the circuit below whose output is routed through the programmable interconnect on an FPGA. Use the values supplied in the table to approximate Rp, Rn, and CL. Use the following definition of fall time: The time from when the input changes from a low to high logic value to the time when the output reaches 0.1Vdd. (Note: ln(0.1) -2.3, ln(0.9) -0.1).
Vin VoutDriver Load
1 1 ValueComponent22 kRp11 kRn1x10-15 fCL
4. Map the combinational function, F(X2,X1,X0)=X2 XOR X1 XOR X0, to the macroblock given below. Assume an anti-fuse programmable element in the AND-array and denote a grown fuse with an X. Indicate the configuration memory required such that F is routed as an output to the I/O pin in the figure. Assume an SRAM-based programmable element (shaded boxes) for the MUX control and use the following notation: 1 = logic high, 0 = logic low, and D = dont care.
X0 X1 X2
to AND array
5. (a) Given the programmable interconnect structure shown below identify the best routing from the output of CLB 1 to the input of CLB 8 to achieve the minimum interconnect delay. Do so by darkening the best route you determined. All of the programmable interconnects shown use the same type of pass transistor. You can assume the resistance in the wire is approximately zero.
(b) What circuit parameters affect the interconnect delay?
6.6. One student in a prior class asked how are the One student in a prior class asked how are the System Gate EquivalentsSystem Gate Equivalents determined for determined for FPGAs since a configurable logic block uses look up tables not lFPGAs since a configurable logic block uses look up tables not logic gates for computation. ogic gates for computation. Estimate how many Estimate how many System Gate EquivalentsSystem Gate Equivalents one LUT has given the following data from one LUT has given the following data from the Xilinx Spartanthe Xilinx Spartan--2E Spec. Assume that all of the LUTs in an FPGA count for 10% o2E Spec. Assume that all of the LUTs in an FPGA count for 10% of the f the System Gates.System Gates.
Device System Gate Range Total CLBs Slices/CLB Device System Gate Range Total CLBs Slices/CLB LUT(16x1b)/SliceLUT(16x1b)/SliceXC2S300E 93K XC2S300E 93K 300K 1,536 2 300K 1,536 2 22
1 2 3 4 5 6 7 8 9 A B C D E
Computer Systems, Processors, and TerminologyComputer Systems, Processors, and Terminology Custom HW Custom HW ASIC, VLSI, ASIC, VLSI, Processor vs. MicroprocessorProcessor vs. Microprocessor Microcomputer vs. MicrocontrollerMicrocomputer vs. Microcontroller Embedded system design processEmbedded system design process
RequirementsRequirements SpecificationsSpecifications ArchitectureArchitecture ComponentsComponents System IntegrationSystem Integration
Embedded SystemEmbedded System Characteristics: Complex Algorithms, user interface, realCharacteristics: Complex Algorithms, user interface, real--time, multitime, multi--raterate Costs: Cost of goods, mfg cost, development costCosts: Cost of goods, mfg cost, development cost Challenges Challenges
Hardware performance vs. CostHardware performance vs. Cost Code Space/ Code DensityCode Space/ Code Density Need to meet realNeed to meet real--time demandstime demands Minimize power consumptionMinimize power consumption Design for upgradeDesign for upgrade--abilityability VerificationVerification ReliabilityReliability
Exam Review Outline Exam Review Outline lecture 4lecture 4
Embedded Systems ContinuedEmbedded Systems Continued Computer System Block DiagramComputer System Block Diagram System on Chip System on Chip SoCSoC
Processor in ASIC or FPGA with Softcore processorProcessor in ASIC or FPGA with Softcore processor Programmers model Programmers model Registers, Condition Codes and Instruction Set Registers, Condition Codes and Instruction Set
ArchitectureArchitecture Why is it important to know ISA?Why is it important to know ISA? Computer ClassificationComputer Classification
ArchitectureArchitecture Von Neuman / Princeton ArchitectureVon Neuman / Princeton Architecture Harvard ArchitectureHarvard Architecture DSPDSPs s
RISC vs. CISCRISC vs. CISC EDK computer systemEDK computer system
MicroBlaze ProcessorMicroBlaze Processor Busses (Busses (ILMB, DLMB, IOPB and DOPB)ILMB, DLMB, IOPB and DOPB) MicroBlaze Memory SystemMicroBlaze Memory System
Memory Controllers and BRAMMemory Controllers and BRAM Memory Mapped I/OMemory Mapped I/O IP CoresIP Cor...