research on a high performance ldo regulator … · 「過電流保護回路」に関しては0.35...

RESEARCH ON A HIGH PERFORMANCE

LDO REGULATOR OPERATING WITH

LOW-POWER AND LOW-SUPPLY-VOLTAGE

SOCHEAT HENG

Doctoral Program in Electronic Engineering

Graduate School of Electro-Communications

University of Electro-Communications

A thesis submitted for the degree of

DOCTOR OF ENGINEERING

30/09/2009

RESEARCH ON A HIGH PERFORMANCE

LDO REGULATOR OPERATING WITH

LOW-POWER AND LOW-SUPPLY-VOLTAGE

APPROVED

Asso. Prof. Cong-Kha PHAM, Chairman

Prof. Kazushi NAKANO

Prof. Yoshinao MIZUGAKI

Asso. Prof. Kohji HIGUCHI

Asso. Prof. Kouji WADA

Date Approved by Chairman

和文要旨

低消費電力・低電圧動作が可能な高性能のシリーズレギュレータに関する研究

ヘイン　ソチェット

電気通信学研究科電子工学専攻博士後期課程

電気通信大学大学院

近年，メインプロセッサやDSPが巨大化し続けるに従い，電子機器の消費電

力は増加し，動作電源電圧は加工寸法の微細化とともに低下している．ここで，給

電の役割を担う直流安定化電源の一種である低ドロップアウトレギュレータ（以

下LDOレギュレータ；ドロップアウト：レギュレータの入力電圧と出力電圧の差

の最小値）に「低消費電力・低電圧動作」させながら，「高精度出力電圧」，「高速

負荷過渡応答」，「高リプル除去率」，「高精度の過電流保護回路」，「高速起動かつ

小さい突入電流」という新たな要求が出現しつつある．本研究では，これらの要

求を満たすために，既存の回路技術だけで実現が困難とされる特性を新たに提案

したコンセプトに基づく回路を導入することにより，優れた特性を有する LDO

レギュレータを目指して研究を行ってきた．

高速負荷過渡応答特性を実現するために，「高速化回路」を提案した．電子機器

の高機能化・高速化・常時接続による消費電力の増加問題を解決するために，シ

ステム全体を複数のブロックに分割して給電を行う．不必要なブロックは内部ク

ロックを停止して消費電流を下げ，必要に応じて動作を開始する．この時，LDO

レギュレータ側から見ると無負荷状態から全負荷状態に過渡的に変化するため，

高速負荷過渡応答が必要となる．LDOレギュレータの動作電流を増やすことで，

高速応答が実現できるが，その反面，低消費電力システムを構成することは困難

となる．また，出力安定化のために大容量のコンデンサーを使用することも考え

られるが，実装用の基板面積を拡大させることになり，携帯機器の小型化や生産

性に向かない．提案した「高速化回路」は，負荷急変時に誤差アンプの応答を待

たずに，必要に応じてパワーMOSトランジスタのゲート容量を高速充放電させ

る新しい回路構成を導入する事により，LDOレギュレータの出力電圧の低下を限

りなく抑える事ができると確認できた．

高リプル除去率特性を実現するために，「基板バイアス制御回路」を提案した．

電子機器の動作電圧がDC-DCコンバータから給電される場合，電源ラインのリ

プル雑音電圧を避ける事ができない．高周波の送受信回路を有する携帯電話等の

通信機器において，電源ラインのリプル雑音は送信周波数の安定性に悪影響を与

え，音質を劣化させてしまう．このため，可能な限りこのリプル雑音を減衰させ

る必要がある．従来から，リプル雑音を減らすためには誤差アンプの応答速度を

維持する事が必須であるため，回路の消費電力を減らせないという事実がある．

提案した「基板バイアス制御回路」は，電源電圧によるMOSトランジスタのチャ

ンネル変調及びコンデンサーのAC結合特性を活用し，誤差アンプの出力電圧を

電源電圧に追従させ，リプルをキャンセル可能な新しい回路構成を有する．誤差

アンプの消費電力を増やさない構成のため，低消費電力でありながら高リプル特

性を持たせる事ができると確認できた．

高精度の負荷安定度特性を実現するために,「補正回路」を提案した．集積回

路の微細化に伴い，電子機器の動作電圧が急激に低下し，ついに 1Vを切る時代

になった．これにより，電源回路に対して新たな出力電圧精度の要求が出現した．

電源電圧が 0.9Vの場合，2%の精度ではわずか 18mVまでの変動幅しか許されな

い．パワーMOSトランジスタを用いるLDOレギュレータにおいて，負荷電流が

流れれば流れるほどパッケージに使用するボンディングワイヤの抵抗が無視でき

なくなってしまう．提案した「補正回路」は，ボンディングワイヤの抵抗による

出力電圧の降下を見込んで，フィードバック電圧を調整し，LDOレギュレータの

出力電圧を補正する新しい回路構成を導入した．ボンディングワイヤの抵抗によ

る電圧降下分と「補正回路」による補正分が互いにキャンセルさせ合う事で，高

精度の負荷安定度を実現する事が可能であると確認できた．

LDOレギュレータに過電流を流せないために内蔵型の「過電流保護回路」を

提案した．LDOレギュレータに内蔵される過電流保護回路は，デバイスが破壊さ

れないように正確に制限電流を超えた過電流を検出し，出力電圧をシャットダウン

するとともに，出力電流を一定の保持電流に固定させる必要がある．しかし，既

存回路構成において，消費電力が大きく，非線形の負荷電流によってラッチアップ

現象が発生してしまうという問題点を抱えている．ラッチアップ現象を回避する

ためにシャットダウンのカーブを変更させる手法などが用いられているが，LDO

レギュレータの出力電圧のシャットダウン特性はきれいな「フの字」特性が得ら

れず，保持電流を小さくさせる事ができなかった．提案した「過電流保護回路」

は LDOレギュレータの出力電圧をディジタル的にシャットダウンさせ，ラッチ

アップ現象を回避しながら，きれいな「フの字」特性を持たせる新しい回路構成

を導入した．提案回路は低消費電力で動作が可能であり，LDOレギュレータの入

出力電圧の依存性が少ない安定した制限電流及び保持電流を提供する事ができる

と確認できた．

高速起動かつ小さい突入電流特性を実現するために，「突入電流制限回路」を

提案した．システム全体を複数のブロックに分割して給電を行う電子機器におい

て，複数のブロックが同時に起動する場合には起動時の突入電流問題が発生する．

DC-DCコンバータから電力供給を受けるパワーマネージメント ICの場合，内蔵

した複数の LDOレギュレータが同時に動作すると，LDOレギュレータの安定化

コンデンサーによる突入電流の重ね合いにより，DC-DC コンバータの出力定格

を超えてしまい，出力電圧が急低下する恐れがある．この一瞬の電源電圧の低下

により，メインプロセッサが誤動作を起こし，システム全体に悪影響を及ぼしか

ねない．提案した「突入電流制限回路」は，LDOレギュレータが起動時のみに誤

差アンプの応答性を必要に応じて鈍くして突入電流を制限する新しい回路構成を

導入した．「突入電流制限回路」は起動時に負荷電流条件や安定化コンデンサーに

応じて誤差アンプへの働きを変化させるため，LDOレギュレータは小さい突入

電流のみならず，高速に起動する事ができると確認できた.

「高速化回路」，「基板バイアス制御回路」及び「補正回路」を内蔵した LDO

レギュレータを 0.18µmのCMOSプロセスで試作を行った．チップの評価結果に

より，出力電圧が 1.2Vで出力安定化容量が 4.7µFの場合，負荷電流が 0.1mA ⇔

150mAで急変しても出力電圧の降下及び上昇をそれぞれ 116mV 及び 104mV以

下に抑える事が確認できた．更に，同出力電圧で負荷電流が 50mAの時のリプル

除去率特性は，リプル周波数 10Hzと 1KHzにおいて，それぞれ 75dBと 61.8dB

が実現できた．また，負荷安定度に関しては，負荷電流が 0mAから 150mA変

化しても LDOレギュレータの出力電圧を 1%以内の変動幅に保つ事が確認でき

た．試作チップは基準電圧回路等を含めた回路全体の消費電流は軽負荷でわずか

8.5µAである．重負荷においても 35µAのみとなった．

「過電流保護回路」に関しては 0.35µmのCMOSプロセスを用いて試作して評

価を行った．単純な回路構成である為，約 0.82µAの低消費電流及び 0.0079mm2

の省面積回路で実現できた．LDOレギュレータの出力電圧は 1.2Vから 3.6Vま

で対応し，電源電圧は出力電圧+0.5Vから最大の 6.0Vまでの範囲で使用可能で

ある事が確認できた．また，出力電圧のシャットダウン特性もきれいな「フの字」

特性が得られ，ラッチアップ現象も回避できると確認できた．

「突入電流制限回路」は 0.18µmのCMOSプロセスで設計し，HSPICEによ

るシミュレーションを行った結果，LDOレギュレータの安定化容量を 10µFに設

定したにも関わらず，最大突入電流を 144.1mA以下に抑制する事ができた．更

に，出力電圧の最大起動時間もわずか 313µs 以内である．基準電圧の起動特性の

傾斜を制御する従来方式と違い，パワーMOSFETのゲート電圧を直接に制御す

る事で外付けのソフトスタート用コンデンサーが不要となり，省面積かつ低コス

トの電源システムが実現できると期待できる．

本論文では，低消費電力・低電圧動作が可能な高性能の LDOレギュレータの

設計，実装及び評価に関する研究について論じた．低消費電力化による負荷過渡

応答やリプル除去率の低減に関して「高速化回路」及び「基板バイアス制御回路」

を導入する事により解決した．ボンディングワイヤの抵抗によるLDOレギュレー

タの負荷安定度の劣化に関して「補正回路」を導入する事により優れた負荷安定

度を得る事ができた．複数の LDOレギュレータが同時起動による突入大電流を

防ぐために「突入電流制限回路」を導入する事により解決し，更に，正確な制限

電流及び安定した保持電流を持ち，入出力電圧に依存度が小さい過電流保護回路

内蔵型LDOレギュレータを提案した．低消費電力で動作しているため，分割給電

によってレギュレータの数が増えても全体の消費電流を増やす事なく，低消費電

力の電源システムを構成するために有効な回路であると期待できる．また，SoC

技術が進んだ現在，LDOレギュレータに外付けの安定化容量の使用が好ましくな

い傾向がある．安定化容量を使用しなくても，安定に動作し，高速負荷過渡応答

や高リプル除去率といった高性能の LDOレギュレータを実現する事は今後の課

題である. さら, 現在の LDOレギュレータのチップ面積の大半はパワーMOSを

占めている. 生産効率を考える場合, パワーMOSのサイズを極力に減らしてチッ

プの面積を小さくする事が重要な課題となる. プロセスの微細化によって, 省面

積でパワーMOSの駆動能力を向上させる事が可能であるが, 顕著なリーク電流

が流れる. そのようなパワーMOSに対応できるLDOレギュレータの設計の研究

も行う必要がある.

Abstract

RESEARCH ON A HIGH PERFORMANCE LDO REGULATOR

OPERATING WITH LOW-POWER AND

LOW-SUPPLY-VOLTAGE

SOCHEAT HENG

Doctoral Program in Electronic Engineering

University of Electro-Communications

The research presented in this dissertation is focused on the design

of a high performance Low Dropout Regulator (LDO) which targeted

for low-power and low-voltage electronic appliances.

Recently, with the increase in power consumption of portable elec-

tronic appliances, low power and high performance LDO is required.

High accuracy of output voltage, high speed response and low noise

have become the main keywords for the researchers. To meet the

above mentioned requirements, several advanced techniques are pro-

posed and presented in this dissertation to design a high performance

LDO with fast load transient response, high power supply rejection

ratio, small inrush current, good load Regulation and precise over

current protection.

Firstly, a Quick Response Circuit has been proposed to achieve fast

load transient response when load current abruptly changes. The cir-

cuit has been achieved through properly charging and discharging the

gate capacitor of power MOSFET. Secondly, a Bulk-Gate Control Cir-

cuit has been proposed to realize the high power supply rejection ratio

(PSRR). The circuit has been achieved through controlling the bulk-

gate of input transistor of error amplifier. Thirdly, in order to keep

the LDO output voltage drop due to bonding wire, the Compensated

Circuit has been proposed. It works to adjust the feedback voltage of

feedback network. Fourthly, an Auto Inrush Current Limiting Circuit

has also been proposed to restrain the inrush current of output capac-

itor to make sure that the malfunction of the application system due

to inrush current is avoided. Not only the small inrush current but

also the high speed start up of LDO has been achieved. Fifthly, an

Over Current Protection Circuit which is necessary to protect LDO

from the damage happened by over load current or output shortening,

is proposed. The proposed protection circuit has high accurate lim-

iting current and stable holding current without getting effects from

latchup.

The high performance LDO with proposed Quick Response Circuit,

Bulk-Gate Control Circuit, Compensated Circuit was fabricated with

0.18µm CMOS technology while the LDO with proposed Over Current

Protection Circuit was fabricated with 0.35µm CMOS technology. For

the proposed Auto Inrush Current Limiting Circuit, the implemented

chip is now being fabricated.

The experimental results of the fabricated chips show that the out-

put undershoot and overshoot of load transient response are only

116mV and 104mV for 4.7µF output capacitor and ILOAD=0.1mA

⇐⇒ 150mA. Also, the PSRR performance is up to 75dB for 10Hz and

remaining high 61.8dB for 1KHz ripple frequency for VOUT = 1.2V

and ILOAD = 50mA. The output voltage drop is restrained to less

than 1% even when the load current reaches 150mA. The quiescent

current of the whole chip is 8.5µA for no load and 35µA for full load

current. Meanwhile, the LDO with proposed Over Current Protection

Circuit has a high accurate limiting current of 200mA and a stable

holding current of 17.8mA. It can digitally shut down the output of

LDO, thus, the latchup effect is avoided.

From the simulation results, the LDO with Auto Inrush Current Lim-

iting Circuit can achieve a very small inrush current of 144.1mA and

fast start up time of 127.7µs for 10µF output capacitor.

With all the proposed and developed circuits applied, an LDO with

extremely low-power consumption, low-operation-voltage but excel-

lent characteristics can be achieved.

In recent year, with the rapid development of system-on-chip designs,

there is a growing trend toward power-management integration. The

local LDO which are utilized to power up sub-blocks of a system in-

dividually must be the On-chip. However, the external capacitors of

LDO have the equivalent series resistance (ESR) and they can ad-

versely affect the stability of the regulator. In addition, these capac-

itors and their external pins required to mount, increase the surface

area (space) which will result in the increasing of high cost for mass

production. Hence, the design of a low-voltage high-stability and fast-

transient LDO with, preferably, capacitor-free operation has become

one of the main topic in our future works. Moreover, for present LDO,

the Power MOSFET occupies the majority of the chip area. With the

advance CMOS technology scaling, the driving ability of Power MOS-

FET at the same size improves compared with the past. Concretely,

with the scaling of CMOS technology, the leak current will remark-

ably flow in the circuit. Hence, the research on a design of an LDO

which can correspond to such the Power MOSFET is the one of the

most important task to be done.

Contents

1 INTRODUCTION 1

1.1 Background and Motivation . . . . . . . . . . . . . . . . . . . . . 1

1.1.1 Power Supply IC Market Trend . . . . . . . . . . . . . . . 1

1.1.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 Classification of Voltage Regulator . . . . . . . . . . . . . . . . . 4

1.2.1 Series Regulator . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2.1.1 Low Dropout Regulator (LDO) . . . . . . . . . . 4

1.2.1.2 Standard Voltage Regulator . . . . . . . . . . . . 5

1.2.2 Switching Regulator (SMPS) . . . . . . . . . . . . . . . . . 7

1.2.3 Series Regulator versus Switching Regulator . . . . . . . . 9

1.3 Scope of the Dissertation . . . . . . . . . . . . . . . . . . . . . . . 9

2 CONVENTIONAL LDO AND ITS DESIGN ISSUES 13

2.1 Conventional LDO Topology . . . . . . . . . . . . . . . . . . . . . 13

2.2 Understanding of LDO Frequency Response . . . . . . . . . . . . 14

2.3 Load Transient Response Characteristic . . . . . . . . . . . . . . . 19

2.3.1 Definition of Load Transient Response . . . . . . . . . . . 19

2.3.2 Analysis of Load Transient Response . . . . . . . . . . . . 20

2.3.2.1 Output Capacitor . . . . . . . . . . . . . . . . . 22

2.3.2.2 Equivalent Series Resistor . . . . . . . . . . . . . 23

2.3.3 Design Obstacles of Load Transient Response . . . . . . . 23

2.4 Power Supply Rejection Ratio (PSRR) Characteristics . . . . . . 25

2.4.1 Definition of PSRR Characteristic . . . . . . . . . . . . . . 25

2.4.2 Analysis of PSRR Characteristic . . . . . . . . . . . . . . 26

2.4.2.1 Simple Model for PSRR of LDO . . . . . . . . . 26

i

CONTENTS

2.4.2.2 Model in Action over Wide Frequency Range . . 28

2.4.3 Design Obstacles of PSRR . . . . . . . . . . . . . . . . . . 31

2.5 Inrush Current Characteristic . . . . . . . . . . . . . . . . . . . . 31

2.5.1 Definition of Inrush Current . . . . . . . . . . . . . . . . . 32

2.5.2 Analysis of Inrush Current of LDO . . . . . . . . . . . . . 32

2.5.3 Design Obstacles of Inrush Current Limiting . . . . . . . . 33

2.6 Load Regulation Characteristic . . . . . . . . . . . . . . . . . . . 35

2.6.1 Definition of Load Regulation . . . . . . . . . . . . . . . . 35

2.6.2 Analysis of Load Regulation . . . . . . . . . . . . . . . . 35

2.6.3 Design Obstacles of Load Regulation . . . . . . . . . . . . 37

2.7 Over Current Protection Circuit . . . . . . . . . . . . . . . . . . . 38

2.7.1 Definition of Over Current Protections Circuit . . . . . . . 39

2.7.2 Design Obstacles of Over Current Protection Circuit . . . 40

3 HIGH PERFORMANCE LDO AND ITS SPECIFICATIONS 43

3.1 Target LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.2 Design Challenge . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.2.1 Load Transient Response . . . . . . . . . . . . . . . . . . . 46

3.2.2 Power Supply Rejection Ratio . . . . . . . . . . . . . . . . 46

3.2.3 Inrush Current . . . . . . . . . . . . . . . . . . . . . . . . 49

3.2.4 Load Regulation . . . . . . . . . . . . . . . . . . . . . . . 50

3.2.5 Over Current Protection Circuit . . . . . . . . . . . . . . . 50

4 PROPOSED HIGH PERFORMANCE LDO 51

4.1 Quick Response Technique for Fast Load Transient Response . . . 51

4.1.1 Circuit Feature . . . . . . . . . . . . . . . . . . . . . . . . 51

4.1.2 Proposed Concept and Operation Principle . . . . . . . . . 51

4.1.3 Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . 55

4.1.3.1 Error Amplifier with DC Boosting Circuit . . . . 57

4.1.3.2 Memory Circuit . . . . . . . . . . . . . . . . . . . 58

4.1.3.3 Comparators Circuit . . . . . . . . . . . . . . . . 60

4.1.3.4 PD-DISCHARGE Circuit . . . . . . . . . . . . . 62

4.1.3.5 PD-CHARGE Circuit . . . . . . . . . . . . . . . 63

4.1.3.6 VOUT-RESTRAIN Circuit . . . . . . . . . . . . 64

ii

CONTENTS

4.1.4 Effectiveness Confirmation by Simulation . . . . . . . . . . 65

4.1.4.1 Reponses at Each Node of Comparator . . . . . . 65

4.1.4.2 Response at Gate Node of Power MOSFET . . . 67

4.1.4.3 Response at VOUT . . . . . . . . . . . . . . . . . 68

4.2 Bulk-Gate Control Technique for High Power Supply Rejection Ratio 68

4.2.1 Circuit Feature . . . . . . . . . . . . . . . . . . . . . . . . 68


4.2.3 Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . 70


4.2.4.1 High PSRR by Effectiveness of Proposed Circuit 72

4.2.4.2 Stability of LDO . . . . . . . . . . . . . . . . . . 74

4.3 Auto Inrush Current Limiting Technique for High Speed Start-Up 75

4.3.1 Circuit Feature . . . . . . . . . . . . . . . . . . . . . . . . 75


4.3.3 Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . 76

4.3.3.1 Auto Inrush Current Limiting Circuit . . . . . . 76

4.3.3.2 Inrush Current Limiting Disable Circuit . . . . . 78

4.3.4 Circuit Operation . . . . . . . . . . . . . . . . . . . . . . . 79


4.3.5.1 Simulation Results of Inrush Current . . . . . . . 79

4.3.5.2 Comparison to Conventional Circuit . . . . . . . 82

4.4 Compensated Technique for High Performance Load Regulation . 83

4.4.1 Circuit Feature . . . . . . . . . . . . . . . . . . . . . . . . 83


4.4.3 Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . 86

4.4.4 Circuit Operation . . . . . . . . . . . . . . . . . . . . . . . 87


4.4.6 VTH Variation and Temperature Dependency . . . . . . . . 91

4.5 Over Current Protection Design . . . . . . . . . . . . . . . . . . . 93

4.5.1 Circuit Feature . . . . . . . . . . . . . . . . . . . . . . . . 93


4.5.3 Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . 96

4.5.3.1 Current Sampling Circuit . . . . . . . . . . . . . 96

iii

CONTENTS

4.5.3.2 Open-loop Comparator . . . . . . . . . . . . . . . 97

4.5.3.3 Schmitt Trigger Circuit . . . . . . . . . . . . . . 98

4.5.3.4 Holding Current Limiting Circuit . . . . . . . . . 99

4.5.3.5 Operation of Completed Circuit . . . . . . . . . 100


4.6 Fabrication Error . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

4.6.1 MOSFET Mismatch . . . . . . . . . . . . . . . . . . . . . 102

4.6.2 Resistor Variation . . . . . . . . . . . . . . . . . . . . . . . 103

4.6.3 Capacitor Variation . . . . . . . . . . . . . . . . . . . . . . 103

4.6.4 Offset Variation of Differential Amplifier . . . . . . . . . . 103

4.7 Design of High Performance LDO . . . . . . . . . . . . . . . . . . 104

4.7.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 104

4.7.2 LDO Circuit in Transistor Level . . . . . . . . . . . . . . . 105

4.7.3 Simulation Results of LDO Circuit . . . . . . . . . . . . . 105

4.7.3.1 Typical DC and AC Characteristics . . . . . . . . 105

4.7.3.2 Margin of DC Characteristics . . . . . . . . . . . 113

4.7.3.3 Margin of Load Transient Characteristic . . . . . 114

4.7.3.4 Margin of Power Supply Rejection Ratio . . . . . 116

4.7.3.5 Summary of Electric Performance of LDO . . . . 120

4.8 Design of LDO with Over Current Protection Circuit . . . . . . . 122

4.8.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 122

4.8.2 LDO Circuit in Transistor Level . . . . . . . . . . . . . . . 122

4.8.3 Simulation Results of LDO Circuit . . . . . . . . . . . . . 124

4.8.3.1 Typical DC Characteristics . . . . . . . . . . . . 124

4.8.3.2 Margin of DC Characteristics . . . . . . . . . . . 125

5 IMPLEMENTATION AND EXPERIMENTAL RESULTS 127

5.1 Chip Fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

5.1.1 Implementation of High Performance LDO . . . . . . . . . 127

5.1.2 Implementation of Over Current Protection Circuit . . . . 128

5.2 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . 129

5.2.1 Measurement of High Performance LDO . . . . . . . . . . 129

5.2.1.1 Load Transient Response Characteristic . . . . . 129

iv

CONTENTS

5.2.1.2 PSRR Characteristic . . . . . . . . . . . . . . . . 130

5.2.1.3 Load Regulation Characteristic . . . . . . . . . . 133

5.2.1.4 Dropout Voltage Characteristic . . . . . . . . . . 134

5.2.1.5 Line Regulation Characteristic . . . . . . . . . . 134

5.2.1.6 Quiescent Characteristic . . . . . . . . . . . . . . 136

5.2.1.7 Summary of Electrical Performance . . . . . . . . 136

5.2.2 Measurement of LDO with Over Current Protection . . . . 138

5.2.2.1 Limit Current and Holding Current . . . . . . . . 138

5.2.2.2 Electrical Performances Summary . . . . . . . . . 141

5.3 Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

5.3.1 Evaluation of High Performance LDO . . . . . . . . . . . . 142

5.3.1.1 Evaluation of Load Transient Response . . . . . . 142

5.3.1.2 Evaluation of PSRR . . . . . . . . . . . . . . . . 143

5.3.1.3 Evaluation of Load Regulation . . . . . . . . . . 144

5.3.2 Evaluation of LDO with Over Current Protection . . . . . 145

5.4 Correspondence of Simulation and Measurement Results . . . . . 146

5.4.1 Consideration of High Performance LDO . . . . . . . . . . 146

5.4.2 Consideration of LDO with Over Current Protection . . . 149

5.5 Solution to Process Variation . . . . . . . . . . . . . . . . . . . . 150

5.5.1 Sensitive Circuit to Process Variation . . . . . . . . . . . . 150

5.5.1.1 Bias Circuit . . . . . . . . . . . . . . . . . . . . . 151

5.5.1.2 Bonding Wire Compensated Circuit . . . . . . . 151

5.5.1.3 Comparators of Quick Response Circuit . . . . . 152

5.5.1.4 Bulk-Gate Control Circuit . . . . . . . . . . . . . 152

5.5.2 Trimming Technology . . . . . . . . . . . . . . . . . . . . . 153

5.5.2.1 Trimming of Offset Voltage . . . . . . . . . . . . 153

5.5.2.2 Trimming of Active and Passive Elements . . . . 156

5.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

6 CONCLUSION 161

6.1 Enabling Techniques . . . . . . . . . . . . . . . . . . . . . . . . . 161

6.1.1 Quick Response Circuit . . . . . . . . . . . . . . . . . . . . 161

6.1.2 Bulk-Gate Control Circuit . . . . . . . . . . . . . . . . . . 162

v

CONTENTS

6.1.3 Auto Inrush Current Limiting Circuit . . . . . . . . . . . . 163

6.1.4 Bonding Wire Compensated Circuit . . . . . . . . . . . . . 164

6.1.5 Over Current Protection Circuit . . . . . . . . . . . . . . . 164

6.2 Future Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

6.2.1 Fabrication and Evaluation of Auto Inrush Current Limit-

ing Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

6.2.2 Capacitor-Free LDO . . . . . . . . . . . . . . . . . . . . . 166

6.2.3 Power MOSFET Scaling . . . . . . . . . . . . . . . . . . . 168

6.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

A OTHER MEASUREMENT RESULTS 171

A.1 Load Transient Response . . . . . . . . . . . . . . . . . . . . . . . 171

A.2 Power Supply Rejection Ratio . . . . . . . . . . . . . . . . . . . . 181

B LAYOUT PHOTOGRAPH 191

B.1 LDO with Developed Circuits . . . . . . . . . . . . . . . . . . . . 191

B.2 LDO with Protection Circuit . . . . . . . . . . . . . . . . . . . . . 191

C CURRENT-MODE OPERATIONAL AMPLIFIER 195

C.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

C.2 Level-Shifter MOSFETs . . . . . . . . . . . . . . . . . . . . . . . 198

C.3 Proposed Current Mode Differential Amplifier . . . . . . . . . . . 200

C.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . 202

C.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

D LIST OF PUBLICATION 207

D.1 Journal Paper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

D.2 International Conference and Workshop . . . . . . . . . . . . . . . 208

D.3 Local Conference and Workshop . . . . . . . . . . . . . . . . . . . 209

REFERENCES 218

vi

List of Figures

1.1 LDO in power IC market. . . . . . . . . . . . . . . . . . . . . . . 2

1.2 Power IC growth rate. . . . . . . . . . . . . . . . . . . . . . . . . 3

1.3 Classification of voltage regulator. . . . . . . . . . . . . . . . . . . 5

1.4 Structure of low dropout regulator. . . . . . . . . . . . . . . . . . 6

1.5 Power lost in low dropout regulator. . . . . . . . . . . . . . . . . . 6

1.6 Structure of standard voltage regulator. . . . . . . . . . . . . . . . 7

1.7 Structure of switching regulator. . . . . . . . . . . . . . . . . . . . 8

1.8 Example operation method of switching regulator. . . . . . . . . . 8

2.1 Required functions for good performance LDO. . . . . . . . . . . 14

2.2 Structure of typical LDO. . . . . . . . . . . . . . . . . . . . . . . 15

2.3 Power PMOS transistor model. . . . . . . . . . . . . . . . . . . . 15

2.4 Frequency response of typical LDO. . . . . . . . . . . . . . . . . . 18

2.5 Load transient response of typical LDO. . . . . . . . . . . . . . . 19

2.6 Conventional problems. . . . . . . . . . . . . . . . . . . . . . . . . 24

2.7 Definition of PSRR. . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.8 Simple model for PSRR of LDO. . . . . . . . . . . . . . . . . . . 27

2.9 Inrush current of LDO in application. . . . . . . . . . . . . . . . . 32

2.10 Structure of conventional LDO circuit. . . . . . . . . . . . . . . . 33

2.11 Start-up characteristic of LDO and its inrush current. . . . . . . . 34

2.12 Typical LDO structure with bonding wire. . . . . . . . . . . . . . 36

2.13 Bonding wire in IC package. . . . . . . . . . . . . . . . . . . . . . 37

2.14 Over current protection circuit in LDO. . . . . . . . . . . . . . . . 39

2.15 Latchup effects of over current protection circuit. . . . . . . . . . 40

2.16 Problems when avoiding latch up effects. . . . . . . . . . . . . . . 41

vii

LIST OF FIGURES

3.1 PSRR deterioration by reducing power consumption. . . . . . . . 48

3.2 Power management IC system. . . . . . . . . . . . . . . . . . . . . 49

3.3 Design challenge of load regulation. . . . . . . . . . . . . . . . . . 50

4.1 Concept of proposed quick response circuit. . . . . . . . . . . . . 52

4.2 Structure of proposed circuit. . . . . . . . . . . . . . . . . . . . . 53

4.3 Completed LDO circuit with quick response circuit. . . . . . . . . 57

4.4 Completed error amplifier with DC boosting circuit. . . . . . . . . 58

4.5 Completed memory circuit used in proposed circuit. . . . . . . . . 59

4.6 Open-loop comparator circuit. . . . . . . . . . . . . . . . . . . . . 60

4.7 Completed comparator in quick response circuit. . . . . . . . . . . 62

4.8 Completed charge and discharge circuit. . . . . . . . . . . . . . . 63

4.9 Output signal of comparator at ILOAD=0.1mA-75mA. . . . . . . . 65

4.10 Output signal of comparator at ILOAD=75mA-0.1mA. . . . . . . . 66

4.11 PD node with and without quick response circuit. . . . . . . . . . 67

4.12 VOUT with and without quick response circuit. . . . . . . . . . . . 68

4.13 Structure of LDO with bulk-gate control circuit. . . . . . . . . . . 69

4.14 Channel-length modulation of MOSFET. . . . . . . . . . . . . . . 71

4.15 Effectiveness of bulk-gate control circuit to PSRR. . . . . . . . . . 73

4.16 Frequency characteristic of proposed LDO. . . . . . . . . . . . . . 74

4.17 Concept of proposed auto inrush current limiting circuit. . . . . . 76

4.18 Auto inrush current limiting circuit. . . . . . . . . . . . . . . . . . 77

4.19 Inrush current limiting disable circuit. . . . . . . . . . . . . . . . 78

4.20 VOUT and IINRUSH at ILOAD=0.1mA and VDD=VOUT +1V. . . . . 80

4.21 VOUT and IINRUSH at ILOAD=200mA and VDD=VOUT +1V. . . . . 80

4.22 VOUT and IINRUSH at ILOAD=0.1mA and VDD=5.5V. . . . . . . . 81

4.23 VOUT and IINRUSH at ILOAD=200mA and VDD=5.5V. . . . . . . . 81

4.24 Inrush current of LDO with and without the proposed circuit. . . 84

4.25 Start-up time of LDO with and without the proposed circuit. . . . 84

4.26 Proposed concept of compensated circuit. . . . . . . . . . . . . . . 86

4.27 Proposed circuit structure. . . . . . . . . . . . . . . . . . . . . . . 87

4.28 Load characteristics at VOUT =0.9V. . . . . . . . . . . . . . . . . . 89

4.29 Load regulation characteristics. . . . . . . . . . . . . . . . . . . . 90

viii

LIST OF FIGURES

4.30 Phase margin characteristics. . . . . . . . . . . . . . . . . . . . . 91

4.31 Temperature dependency. . . . . . . . . . . . . . . . . . . . . . . 92

4.32 Threshold voltage dependency. . . . . . . . . . . . . . . . . . . . . 93

4.33 Proposed solution to avoid latch-up effect. . . . . . . . . . . . . . 94

4.34 Concept of proposed over current protection circuit. . . . . . . . . 95

4.35 Proposed over current protection circuit. . . . . . . . . . . . . . . 96

4.36 VOUT shut down characteristic and quiescent current. . . . . . . . 101

4.37 Process Conner. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

4.38 Micrograph of completed proposed LDO. . . . . . . . . . . . . . . 104

4.39 Completed LDO circuit in transistor level. . . . . . . . . . . . . . 106

4.40 Line regulation performance. . . . . . . . . . . . . . . . . . . . . . 109

4.41 Dropout voltage performance. . . . . . . . . . . . . . . . . . . . . 109

4.42 Load regulation performance. . . . . . . . . . . . . . . . . . . . . 110

4.43 Quiescent current performance. . . . . . . . . . . . . . . . . . . . 110

4.44 Load transient response performance. . . . . . . . . . . . . . . . . 111

4.45 PSRR performance. . . . . . . . . . . . . . . . . . . . . . . . . . . 111

4.46 Block diagram of LDO with over current protection circuit. . . . . 122

4.47 LDO with over current protection circuit in transistor level. . . . 123

5.1 Micrograph of a completed proposed LDO. . . . . . . . . . . . . . 128

5.2 Microphotograph of proposed circuit. . . . . . . . . . . . . . . . . 129

5.3 Load transient response of target LDO. . . . . . . . . . . . . . . . 130

5.4 PSRR performance of target LDO. . . . . . . . . . . . . . . . . . 131

5.5 Effect of bulk-gate control circuit to line regulation. . . . . . . . . 132

5.6 Load regulation performance of target LDO. . . . . . . . . . . . . 133

5.7 Dropout voltage of target LDO. . . . . . . . . . . . . . . . . . . . 134

5.8 Line regulation of proposed LDO. . . . . . . . . . . . . . . . . . . 135

5.9 Quiescent current of proposed LDO. . . . . . . . . . . . . . . . . . 135

5.10 Testing circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

5.11 Over current limiting at VOUT =1.2V and VOUT =3.6V. . . . . . . . 139

5.12 VDD and VOUT dependency and quiescent current. . . . . . . . . 139

5.13 Transient response at VOUT =1.2V. . . . . . . . . . . . . . . . . . . 140

5.14 Evaluation board. . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

ix

LIST OF FIGURES

5.15 Sensitive part of bias circuit. . . . . . . . . . . . . . . . . . . . . . 151

5.16 Sensitive part of compensated circuit. . . . . . . . . . . . . . . . . 152

5.17 Sensitive part of quick response circuit. . . . . . . . . . . . . . . . 153

5.18 VOUT drop versus offset voltage of comparator. . . . . . . . . . . . 154

5.19 PSRR versus channel length modulation of MK. . . . . . . . . . . 155

5.20 Trimming techniques for better load transient response. . . . . . . 156

5.21 Trimming techniques for better PSRR. . . . . . . . . . . . . . . . 157

6.1 Layout of LDO with auto inrush current limiting circuit. . . . . . 166

A.1 ILOAD=0.1mA-50mA and COUT =0.47µF. . . . . . . . . . . . . . . 172

A.2 ILOAD=50mA-0.1mA and COUT =0.47µF. . . . . . . . . . . . . . . 172

A.3 ILOAD=0.1mA-100mA and COUT =0.47µF. . . . . . . . . . . . . . 173

A.4 ILOAD=100mA-0.1mA and COUT =0.47µF. . . . . . . . . . . . . . 173

A.5 ILOAD=0.1mA-150mA and COUT =0.47µF. . . . . . . . . . . . . . 174

A.6 ILOAD=150 mA-0.1mA and COUT =0.47µF. . . . . . . . . . . . . . 174

A.7 ILOAD=0.1mA-50mA and COUT =1µF. . . . . . . . . . . . . . . . 175

A.8 ILOAD=50mA-0.1mA and COUT =1µF. . . . . . . . . . . . . . . . 175











A.19 VOUT =0.9V, ILOAD=1mA without proposed circuit. . . . . . . . . 182

A.20 VOUT =0.9V, ILOAD=1mA with proposed circuit. . . . . . . . . . . 182

A.21 VOUT =0.9V, ILOAD=50mA without proposed circuit. . . . . . . . 183

A.22 VOUT =0.9V, ILOAD=50mA with proposed circuit. . . . . . . . . . 183



x

LIST OF FIGURES













B.1 Fabricated chip of LDO with developed circuits. . . . . . . . . . . 192

B.2 Fabricated chip of LDO with over current protection. . . . . . . . 193

C.1 MOSFET transresistance. . . . . . . . . . . . . . . . . . . . . . . 198

C.2 IIN−VGS1 characteristics for various IB. . . . . . . . . . . . . . . 199

C.3 IIN−VGS characteristics for various values of W1/L1 of M1. . . . 200

C.4 Proposed current-mode differential operational amplifier. . . . . . 201

C.5 AC characteristics (gain and phase responses). . . . . . . . . . . . 202

C.6 Micrograph of proposed circuit. . . . . . . . . . . . . . . . . . . . 203

C.7 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . 204

C.8 Load dependence of output current characteristic. . . . . . . . . . 204

xi

List of Tables

3.1 Electrical performances summary of proposed LDO. . . . . . . . . 45

4.1 Inrush current and start-up time at VDD=2.2V of LDO with and

without the proposed circuit. . . . . . . . . . . . . . . . . . . . . 82

4.2 Inrush current and start-up time at VDD = 5.5V of LDO with and

without the proposed circuit. . . . . . . . . . . . . . . . . . . . . 83

4.3 Electrical performances summary of target LDO by simulation. . . 112

4.4 Simulation list for DC characteristics. . . . . . . . . . . . . . . . . 113

4.5 Decision of margin of DC characteristics. . . . . . . . . . . . . . . 114

4.6 Margin decision of DC characteristics. . . . . . . . . . . . . . . . . 114

4.7 Simulation list for load transient response at 0mV / 10mV offset

variation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

4.8 Margin of load transient response by 0mV offset variation. . . . . 116

4.9 Margin of load transient response by 10mV offset variation. . . . . 116

4.10 Decision of margin of load transient response characteristic. . . . . 116

4.11 Simulation list for PSRR by resistor variation. . . . . . . . . . . . 117

4.12 Simulation list for PSRR by channel length variation. . . . . . . . 117

4.13 Simulation list for PSRR by capacitor variation. . . . . . . . . . . 118

4.14 Margin of PSRR by resistor variation. . . . . . . . . . . . . . . . . 118

4.15 Margin of PSRR by mismatch of channel length modulation. . . . 119

4.16 Margin of PSRR by capacitor variation. . . . . . . . . . . . . . . 119

4.17 Decision of margin of PSRR characteristic. . . . . . . . . . . . . . 120

4.18 Summary of simulation results of LDO with consideration of pro-

cess variation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

xii

LIST OF TABLES

4.19 DC Electrical performances summary of LDO with proposed over

current protection circuit. . . . . . . . . . . . . . . . . . . . . . . 124

4.20 Simulation list of LDO with over current protection. . . . . . . . . 125

4.21 Decision of margin of LDO with over current protection. . . . . . 126

4.22 Margin decision of LDO with over current protection. . . . . . . . 126

5.1 Electrical performances summary of proposed LDO. . . . . . . . . 137

5.2 Electrical performances summary of LDO with over current pro-

tection circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

5.3 Comparison of load transient response with previous LDO. . . . . 142

5.4 Comparison of PSRR with previous LDO. . . . . . . . . . . . . . 144

5.5 Comparison of load regulation with previous LDO. . . . . . . . . 145

5.6 Comparison of LDO with over current protection to previous LDO. 146

5.7 Summary of fabricated LDO and its correspondence to simulation

results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

C.1 Characteristics of various techniques [66]. . . . . . . . . . . . . . . 197

C.2 Electrical performances of proposed amplifier. . . . . . . . . . . . 205

xiii

Chapter 1

INTRODUCTION

The world around us is going mobile. It seems like a new electronic gadget

finds its way into our daily life routinely, from numerous wireless communication

gear to notebook computers, medical monitoring devices, etc. This portable

and battery-operated equipment is becoming more sophisticated with multiple

functions, and the manufacturers of these devices rely heavily on smaller and

lower-cost integrated circuits without any performing compromises. Long life

lasting battery, or longer time between charges, has become the distinguished

feature for such devices. One of the main integrated circuit functions virtually

used in all electronics equipment is the regulator.

1.1 Background and Motivation

1.1.1 Power Supply IC Market Trend

Great growth of power supply IC was accomplished by recovering demand of

digital consumer products in 2006. Referring to the research [1], the power supply

IC market in Japan of year 2006 was divided according to the product as shown in

Figure 1.1. From the figure, the sale of AC/DC converter was 35 billion yen, the

voltage detector was 14 billion yen, the power management IC was 16.9 billion

yen and the power system IC was 18.6 billion yen meanwhile the sale of the

low dropout regulator (LDO) was 52.6 billion yen which is the top share of the

1


products. This data shows the importance of LDO in power supply IC market to

which attention should be paid in the future.

Figure 1.1: LDO in power IC market.

The research [1] also estimated that the entire power supply IC will grow up

by about 12% on the annual rate average and the sale amount will reached to

28.25 billion yen in year 2011 as shown in Figure 1.2.

The growth of power IC in the world has been forecasted to be 18.5% for

five years in the future [2]. This growth is mainly because of the expansion of

Chinese market. LDO and DC-DC are still the only two main products to which

attentions are being paid in most fields related to the communication.

Compared with the switching regulators, series regulators are less noisy, less

complex, and cheaper. The explosive proliferation of battery-operated equipment

such as cellular phones, notebook computers, and palmtop computers in the past

decade have accelerated the development and the usage of LDO, and low quiescent

current series regulators. LDO is widely built in all electronic appliances by all

means not only for portable electronic devices.

2


Figure 1.2: Power IC growth rate.

1.1.2 Motivation

The number of electronic equipments which are operating in the world is pre-

sumed several hundreds million units. Assume that one LDO is operating with

200µA and 3V power supply voltage, then with five hundreds million units, hun-

dred thousand ampere of current and three hundreds kilowatt of power will be

consumed. An effort to improve the performances of LDO without increasing the

power consumption plays an important role to save the world energy.

Recently, the volume of data to be processed in portable electronic appliances

is keeping on increasing such as the image data, voice data, etc. which resulted in

the demand for high speed processing. Yet, the more the processor become larger,

the more power consumption of the equipment increases. However, based on the

CMOS technology scaling, the power-supply voltage is operated in the contradict

direction. Hence, the new demand of the LDO is required. The low power

consumption, high accuracy, high-speed response and low noise have become the

main keywords for the researchers. Such these demands have existed so far but

they are now reached a level that cannot be achieved without the revolution of

the present technology.

To meet the above mentioned requirement for the analog circuit at the deep

3

1.2 Classification of Voltage Regulator

sub-micron era, this research has been focused on how to achieve the high per-

formance LDO which is operable with low-power and low-voltage for mobile elec-

tronic applications.

The design of best performance of LDO contributes to is not only the industrial

field but also the clean environment as well.


Voltage regulation is required for various functions in most electronic systems.

Today electronic systems demand better regulating performance, higher efficiency

and lower parts count. This growing demand is mainly due to the increase of the

portable telecommunication and computer products’ consuming that require ever

higher power efficiency. Besides power efficiency, supply voltage compatibility

problems also demand the use of regulators. A large number of systems still use

5V supply voltage on the printed circuit boards (PCBs). However, for higher

integration and performance improvement, IC manufacturers usually adopt more

advanced fabrication processes which require a lower operating voltage. In this

situation, regulators are required to convert the higher voltage for I/O circuits to

a lower voltage for core circuits. There are two main kinds of voltage regulator

to be classified as shown in Figure 1.3. Both linear and switching regulators are

available in wide varieties to offer different performance with different cost.

1.2.1 Series Regulator

1.2.1.1 Low Dropout Regulator (LDO)

For years, linear type regulators have been the building block of any circuit,

however, over the past several years linear regulators have been replaced by a

device more suitable for battery-operated devices. The low dropout regulator,

better known as LDO, is a special type of regulator where the minimum required

voltage between the input-output voltage (the dropout voltage) is significantly

smaller than predecessor parts. The lower the LDO’s dropout voltage the longer

the battery life as the battery can be discharged all the way down to a few

hundreds of mV of the desired output voltage. A low dropout regulator (LDO)

4


Figure 1.3: Classification of voltage regulator.

is a DC linear voltage regulator which has a very small input-output differential

voltage. The main components are a power PMOSFET and a differential amplifier

(error amplifier). One input of the differential amplifier monitors a percentage

of the output, as determined by the resistor ratio of R1 and R2 of feedback

network. Another input to the differential amplifier is from a stable voltage

reference (bandgap reference). If the output voltage rises too high, relative to

the reference voltage, the drive to the power MOSFET changes so as to maintain

a constant output voltage [3]. See the basic LDO topology in Figure 1.4 for

references.

However, as shown in Figure 1.5, this kind of regulator has some inefficient

parts. Since the power MOSFET transistor is acting like a resistor, it will waste

electrical energy by converting it to heat. In fact, the power loss due to heating

in the transistor is the production of the current and the voltage dropped across

the transistor.

1.2.1.2 Standard Voltage Regulator

As shown in Figure 1.6, Standard Voltage Regulator has almost the same struc-

ture to LDO. The difference is power MOSFET is formed by NMOSFET. The

5


Figure 1.4: Structure of low dropout regulator.

Figure 1.5: Power lost in low dropout regulator.

advantages of this type of voltage regulator are the high responding speed and

small size of power MOSFET. Compare to this standard voltage regulator, the

power MOSFET of LDO, we have mentioned above, tends to be larger due to a

6


Figure 1.6: Structure of standard voltage regulator.

low trans-conductance of the PMOSFET and limited minimum gate potential.

However, this Standard Voltage Regulator with an NMOSFET source-follower

regulating device would not work when the maximum potential at the MOS-

FET gate is smaller than the threshold voltage of the MOSFET. This maximum

voltage can be larger than 1V due to the body-effect at the source which is not

preferable for low power applications [4].

1.2.2 Switching Regulator (SMPS)

The same function can be performed more efficiently by a switched-mode power

supply (SMPS), but it is more complex and the switching currents in it tend

to produce electromagnetic interference. All said, most modern SMPSs have a

performance that can be as good as or exceed that of series regulators. The

example of SMPS structure is shown in Figure 1.7.

Switching regulators rapidly switch a series device on and off. The duty cycle

of the switch sets how much charge is transferred to the load. This is controlled by

a similar feedback mechanism as in a linear regulator. Because the series element

is either fully conducting, or switching off, it dissipates almost no power; this is

7


Figure 1.7: Structure of switching regulator.

what gives the switching design its efficiency [5]. See Figure 1.8 for reference.

Switching regulators are also able to generate output voltages which are higher

than the input, or of opposite polarity, something not possible with a linear design.

Figure 1.8: Example operation method of switching regulator.

8

1.3 Scope of the Dissertation

Like series regulators, nearly-complete switching regulators are also available

as integrated circuits. Unlike series regulators, these usually require one external

component: an inductor that acts as the energy storage element.

1.2.3 Series Regulator versus Switching Regulator

The two types of the voltage regulators presented in the previous sub-section

have different advantages and disadvantages. Hence, it’s necessary to make well

consideration when choosing the device to use. The following comparison shows

the advantages and disadvantages of each device.

1. Series Regulator

• Series Regulator is the best when low output noise is required.

• Series Regulator is the best when a fast response to input and output

disturbances is required.

• Series Regulator consumes low levels of power.

• Series Regulator consumes low cost.

2. Switching Regulator

• Switching regulator is the best when power efficiency is critical (such

as in portable computers).

• Switching regulator is required when the only power supply is a DC

voltage, and a higher output voltage is required.

• Switching regulator consumes high levels of power.


Again, the objective of this research is to focus on how to provide the perfor-

mance of low dropout regulator (LDO) which has been researched for the low

power and low voltage operated electronic appliances. The approaches have been

done to invent the new circuit design techniques by making the maximum use

9


of the existing CMOS process technologies. As a result, more advanced future

technologies with greater benefits have been achieved.

The dissertation is organized into 6 chapters which started from research back-

ground and motivation, followed by the definition of LDO, the conventional LDO

and its design issues, the new design techniques to provide a high performance

LDO and ended up with the conclusion. Especially, Chapter 4 to Chapter 5 are

the main chapter of this dissertation in which the main concepts are emphasized

and evaluated for their appropriateness in a low voltage and low quiescent current

atmosphere. They are described in detail the necessary sequence of events that

lead up to the completed design of fully LDO’s circuit.

Chapter 1 introduces the research background and motivation. In alternative,

the type of regulator is compared to further elucidate the demand of low dropout

regulator in today’s market. It also introduces briefly the kind of power supply

IC, their classifications and their definitions. A typical circuit architecture is

illustrated along with a description of the basic characteristics and its comparison.

Chapter 2 discusses the conventional LDO and its design issue in which the

definition and the analysis of each characteristics, namely, Load Transient Re-

sponse, Power Supply Rejection Ratio, Inrush Current, Load Current, Over Cur-

rent Protection have been described. The chapter ended up with the design

obstacles which will be solved in Chapter 4.

Chapter 3 illustrates the target LDO and its specification for the research to

be achieved. It discuses also the challenge which must be overcome in order to

design the high performance LDO.

Chapter 4 discuses the design challenges and the necessary considerations to

successfully design the circuits. The new requirements to low dropout regulator,

which implicates in circuit limitations and challenges, are identified. These are

followed by the design techniques of Load Transient Response [6]-[8], Power Sup-

ply Rejection Ratio [9]-[12], Inrush Current [13]-[14], Load Regulation [15]-[16],

along with the difficulties imposed by low voltage and low quiescent current flow.

The highlighted circuits are realized in CMOS technology which are relatively

inexpensive to constrain the research orientation to generalize circuit techniques

and not to manipulate towards of the processes. This chapter also shows the new

design technique of over current protection circuit to improve the accuracy of

10


limiting current and stabilization of holding current. Not only the requirements

of better regulating performance, higher efficiency, and lower parts count LDO, a

high performance of over current protection circuit to protect the LDO from over

current damage has also become the main topic for regulators’ reliability and per-

formance [17]-[21]. In this chapter, new design methodologies of low power over

current protection circuit with accurate limiting current and stable holding cur-

rent is also described. The chapter ended up with the design of completed LDO

utilizing the developed techniques and the have been shown simulation results of

the characteristic of the proposed LDO.

Chapter 5 shows the chip fabrication and experimental results of the com-

pleted LDO in chapter 4, in which all the proposed techniques presented in the

same chapter have been implemented. The discussion on the miss-match between

simulations results and measurement results is also presented. It ended up with

the evaluation of the completed LDO with the proposed design techniques com-

paring to the conventional LDO as well as the trimming technique to restrain the

process variation.

Finally, Chapter 6 comes up with the summary of the enabling techniques

and concluding remarks of the research. The applicable of design techniques for

high performance LDO operated with low voltage and low quiescent current are

summarized and highlighted in perspective of the overall system. The chapter is

ended up with the future works of this research.

11


12

Chapter 2

CONVENTIONAL LDO AND

ITS DESIGN ISSUES

All the Low Dropout Regulator (LDO) specifications are interrelated and lead to

important tradeoff. The tradeoff of the specifications can be counted for those

of efficiency, stability, and transient response. The optimization of the above

mentioned specifications, especially with tight constraints, becomes very convo-

luted. The tradeoff will be more apparent when designing the low power LDO

regulator. However, tradeoff is not always the best solution when designing a

high performance LDO.

In this dissertation, several challenged tasks to design a high performance

LDO without a compromise are described. The challenges have been done mainly

on five characteristics which are the characteristic of Load Transient Response,

Power Supply Rejection Ratio, Inrush Current, Load Regulation and Over Cur-

rent Protection as shown in Figure 2.1.

This chapter mentions the conventional problems of each characteristic which

the designers have faced to during designing a high performance LDO.

2.1 Conventional LDO Topology

Figure 2.2 shows the essential elements of a basic LDO regulator with power

PMOSFET . The LDO regulator can be partitioned into four separate and distinct

functional blocks. The power MOSFET element, the reference voltage circuit, the

13

2.2 Understanding of LDO Frequency Response

Figure 2.1: Required functions for good performance LDO.

feedback network resistors and the error amplifier. The error amplifier is modeled

by a transconductor (ga) with a load comprised of capacitor CP and resistor RP .

The parasitic parameters (CP , RP ) represent both the output impedance of the

error amplifier and the input impedance of the series power MOSFET.

LDO design involves three primary aspects, namely, regulating performance,

current efficiency, and operating voltage. These design aspects are explicitly

stated in the following design specifications: 1) Load Transient Response, 2)

Power Supply Rejection Ratio, 3) Inrush Current, 4) Load Regulation, 5) Over

Current Protection, etc. Each of these specifications is discussed in this section.


The frequency response of typical LDO is analyzed here in order to understand

its stable operation conditions and the factors for its stability.

Figure 2.3 shows the power MOSFET (PMOS transistor) which is modeled

by a small signal model with transconductance gp.

14


Figure 2.2: Structure of typical LDO.

Figure 2.3: Power PMOS transistor model.

An output capacitor COUT with an equivalent series resistor (RESR ) and a

bypass capacitor Cb are added. From Figure 2.2, the output impedance Zo at

VOUT node of LDO is given by [22] :

15


Zo = R12p//(RESR +1

SCOUT

)//1

SCb

=R12p(1 + SRESRCOUT )

S2R12RESRCOUT + S[R12p + RESRCOUT + R12pCb] + 1(2.1)

Where,

R12p = Rds//(R1 + R2) ≈ Rds (2.2)

Typically, the output capacitor value COUT is considerably larger than the

bypass capacitor Cb. Thus, the output impedance Zo approximates to,

Zo ≈ Rds(1 + SRESRCOUT )

[1 + S(Rds + RESR)COUT ]× [1 + S(Rds//RESR)Cb](2.3)

From Equation (2.3), a part of the overall open-loop transfer function for the

regulator is obtained, and the zero and poles can be found. The first pole PO is,

− 1 = S(Rds + RESR)COUT (2.4)

fP0 =−1

2π(Rds + RESR)COUT

(2.5)

Since Rds >> RESR then,

fPo ≈ −1

2πRdsCOUT

(2.6)

The second pole Pb is obtained from Equation (2.3) again,

− 1 = S(Rds//RESR)Cb (2.7)

fPb =−1

2π(Rds//RESR)Cb

(2.8)

Since Rds >> RESR then,

fPb ≈ −1

2πRESRCb

(2.9)

16


We obtain also the zero ZESR as following,

− 1 = SRESRCOUT (2.10)

fZESR =−1

2πRESRCOUT

(2.11)

In addition, another pole Pa exists from the input impedance of the power

MOSFET (i.e., the output impedance of the amplifier, Rp, Cp). The approxi-

mated poles and the zero of the LDO regulator are then given by :

fPo ≈ −1

2π(Rds + RESR)COUT

≈ −1

2πVACOUT

(2.12)

fPa ≈ −1

2π(RpCp

) (2.13)

fPb ≈ −1

2π(Rds//RESR)Cb

(2.14)

fZESR ≈ −1

2πRESRCOUT

(2.15)

Where, Rds ≈ VA/IL, VA = 1/λ for MOS device, and λ is the channel length

modulation parameter.

Based upon the derived poles and zero, the typical frequency response of the

LDO regulator is obtained and is shown in Figure 2.4. Pole Po depends on the

load current. When load current is low, a pole response occurs at relatively low

frequencies, thereby degrading phase margin. Worst-case of stability arises at the

extreme values of the ESR and at low load currents. Pole Pa is the only one

introduced at the input of the power MOSFET, not at the output of the device.

However, The unity gain frequency and stability of the LDO circuit affect

the overall transient response of the LDO. The unity gain frequency affects the

settling time of the linear regulator circuit, where the settling time is the time

elapsed from the initial onset of the load transient to the time where the output

voltage returns to within a few percent of a steady-state value. A higher unity

gain frequency will decrease the duration of a transient condition. In most LDO,

the output capacitor and its associated equivalent series resistance (ESR) form a

dominant pole in the loop response. Although larger output capacitors tend to

decrease the magnitude of the transient response, they also tend to increase the

17


Figure 2.4: Frequency response of typical LDO.

settling time. The stability of an LDO circuit can be assessed from the gain and

phase margins of the loop response. A stable regulator will respond to a transient

in a smooth, controlled manner, while an unstable or quasi-stable regulator will

produce a more oscillatory transient response. Since the internal compensation of

an LDO is fixed, only the output capacitor can be adjusted to insure stability. To

assist in the proper selection of an output capacitor, LDO manufacturers typically

provide limits on the acceptable values of capacitance and ESR [22].

18

2.3 Load Transient Response Characteristic


2.3.1 Definition of Load Transient Response

LDO is commonly used to provide power to low voltage digital circuits, where

point-of load regulation is important. In such these applications, it is common

for the digital circuit to have several different modes of operation. As the digital

circuit switches from one mode of operation to another, the load demand on the

LDO can change quickly as shown in Figure 2.5.

Figure 2.5: Load transient response of typical LDO.

This quick change of load results in a temporary glitch of the LDO output

voltage. Most digital circuits do not react favorably to large voltage transients.

For the digital circuit designer, minimizing the transient response of the LDO

is an very important task. This means to minimize the output voltage’s under-

shoot ∆Vtr1 , over-shoot ∆Vtr2 and to shorten the settling time ∆t1 , ∆t3, ∆t3

and ∆t4.

This section explores the factor to define the characteristic of load transient

response of LDO regulators. Again, the load Transient Response is the output

voltage change in response to transient load current variation. Briefly, it is a

19


function of four parameters: system time response, maximum load current the

output capacitor and the ESR of the output capacitor.

2.3.2 Analysis of Load Transient Response

The worst-case time required for the loop to respond ( t1, which is ideally the

reciprocal of the closed-loop bandwidth) is specified by the maximum permissi-

ble output voltage variation ( Vtr1), which is a function of the output capacitor

(COUT ), the electrical series resistance ESR (RESR) of the output capacitor, the

bypass capacitors (Cb) and the maximum load current (ILOAD) [23]. It is given

by :

∆Vtr1 ≈ ILOAD

COUT + Cb

∆t1 + ∆VESR (2.16)

Thus,

∆t1 ≈ [COUT + Cb]

ILOAD

[∆Vtr1 −∆VESR] (2.17)

Where, VESR is the voltage variation resulting from the presence of the ESR

(RESR) of the output capacitor (COUT ). The effects of ESR are reduced by the

bypass capacitors (Cb), which are typically high frequency thereby exhibiting

low ESR values. In typical implementations the time t1 is not only a function of

bandwidth but also defined by the internal slew-rate associated with the parasitic

capacitance Cp of the power MOSFET in Figure 2.2. The resulting time can be

approximated to be :

∆t1 ≈ 1

BWcl

+ tsr =1

BWcl

+ Cp∆V

Isr

(2.18)

Where, BWcl is the closed-loop bandwidth of the system, tsr is the slew-rate

time associated with Cp, ∆V is the voltage variation at Cp, and Isr is the slew-

rate limited current. For instance, from Equations (2.16) and (2.17), if BWcl is

500kHz, Cp is 200pF, ∆V is 0.5V, Isr is 5µA, COUT is 10µF, RESR is 0Ω and ILOAD

is 100mA, then the maximum output voltage variation is approximately 220mV. If

20


the slew-rate current is large enough, the reciprocal of the closed-loop bandwidth

predominantly defines t1. This would be at the cost of quiescent current flow, in

other words, battery life. Once the slew-rate condition is terminated, the output

voltage recovers and settles to its final value, Vtr2 below the ideal value,

∆Vtr2 ≈ R0−regILOAD (2.19)

Where, Ro − reg is the closed-loop output resistance of the regulator. This is

essentially the effect of load regulation performance on the output. The settling

time (t2) depends up on the time required for the power MOSFET to fully charge

the load capacitors and the phase margin of the open-loop frequency response.

The slew-rate limitation is usually unidirectional in nature thereby creating the

asymmetrical response of Figure 2.5. The slew-rate condition typically occurs

when the load current steps from zero to full range. The direction for which this

condition occurs depends up on the configuration of the buffer and the output

power MOSFET. A typical topology is that of a class A buffer driving a power

PMOSFET and associated parasitic capacitance (Cp).

An example of this is illustrated in the simplified schematic of Figure 2.2

where the power MOSFET is assumed to be a PMOSFET. A class A stage yields

high current in one direction and limited DC current in the other, i.e., emitter

[source] follower biased with a DC current source. More complex topologies,

however, could be implemented for the buffer to realize high symmetrical slew-

rate currents. The portion of the time response that does not experience internal

slew-rate is dominated by the capacitors, the electrical series resistance (ESR) of

the output capacitor, the bandwidth of the system, and the low pull-down current

capability of the LDO’s output (Ipull in Figure 2.2). At first, the output voltage

variation peaks at Vtr3, whose magnitude is defined by the voltage charged on

the capacitors and the voltage generated across the ESR of the output capacitor.

This results because the momentary current supplied by the power device (ILOAD

until the circuit reacts to shut it off) flows to the output capacitor COUT and the

bypass capacitors (the current is no longer flowing to the load). Consequently,

the capacitors charge up and a temporary voltage drop is created across RESR.

This transient voltage can be approximately described by :

21


∆Vtr3 ≈ ILOAD

COUT + Cb

∆t3 + ∆VESR

≈ ILOAD

COUT + Cb

1

BWcl

+ ∆VESR (2.20)

Where, the terminology of Figures 2.2 and 2.5 is adopted. When the output

transistor is finally shut off (after t3) the variation settles down to Vtr4, the voltage

charged on the capacitors (Vtr4 ≈ Vtr3− VESR). At this point, the output voltage

takes time t4 to discharge to its final ideal value,

∆t4 ≈ COUT + Cb

Ipull

∆Vtr4

=[COUT + Cb]R1

VREF

∆Vtr4 (2.21)

The addition of high frequency bypass capacitors (capacitors with low ESR)

reduces the peaks of the transient response, Vtr and V3. This results because the

current supplied by the output capacitor (COUT ) during transient conditions is

decreased as Cb is increased thereby exhibiting a lower voltage drop across RESR.

The remaining current is furnished by the bypass capacitors, which typically have

negligible ESR voltage drops.

2.3.2.1 Output Capacitor

From Equations (2.16) and (2.20), LDO cannot respond instantaneously to a tran-

sient condition without COUT , since there is inherent delay time before the current

through the power MOSFET can be adjusted to accommodate the increased load

current. During this delay time, the output capacitor is left to supply the en-

tire transient current. Because of this, the amount of output capacitance and its

associated parasitic elements greatly impact the transient response of the LDO

circuit [24]. However, all capacitors have an equivalent series resistance (ESR).

A number of factors affect, the ESR values such as the package type, case size,

dielectric material, temperature, and frequency. The amount of capacitance, ESR

each affects the transient response in a different way.

22


2.3.2.2 Equivalent Series Resistor

From Equations (2.16) and (2.20), the voltage across the ESR of a capacitor is

also added to the transient response. The ESR voltage is equal to the product

of the capacitor current and the resistance. Before the transient, while there

is no current flowing in the capacitor, the ESR voltage is zero. As the output

capacitor begins to supply the transient current, the ESR voltage ramps down

proportionally to the rise in load current. The voltage across the ESR remains at

a steady value until the LDO begins to respond to the transient condition. After

the LDO has responded to the transient, the entire load current is again supplied

by the LDO, and the voltage drop across the ESR returns to zero. The resulting

response is a negative pulse of voltage. The magnitude of the load transient

and the amount of series resistance determine the magnitude of the ESR voltage

pulse. Because of the integrating nature of the LDO error amplifier, the LDO

responds faster to larger dips in output voltage. Basically, a larger dip in output

voltage generates a larger differential error voltage that causes the error amplifier

to drive the power MOSFET harder. Consequently, the LDO responds faster to

larger voltage drops caused by larger ESR values. As a result, the period of the

ESR-induced voltage droop decreases as the amount of ESR increases. From a

transient point of view, it is desirable to minimize the amount of ESR. However,

since the ESR and output capacitance form a dominant pole in the compensation

of most LDO, some finite amount of ESR is usually required to guarantee stability

of the LDO [24].

2.3.3 Design Obstacles of Load Transient Response

The worst-case output voltage variation is a function of the bandwidth and the

slew rate limit of the circuit. However, bandwidth and slew rate limit are highly

dependent on quiescent current flow. As bandwidth is demanded to increase, the

parasitic poles are required to increase accordingly thereby necessitating more

current flow to decrease associated impedances. Consequently, the error ampli-

fier’s quiescent current must necessarily increase to yield faster response times.

Moreover, increasing slew rate performance requires an increase in bias current

on the circuit driving the slew rate limited node. This affects the design of the

23


output stage of the amplifier. As a result, the overall minimum quiescent current

flow is limited by the maximum allowable output voltage variation arising from

full range load current steps.

In LDO design, large gate capacitance of power transistor degrades the loop-

gain bandwidth and the slew rate at the gate drive of the LDO in low-power

condition. Both low quiescent current and high-speed load transient response,

therefore, cannot be achieved simultaneously by using the generic LDO structure

[25], [26].

Figure 2.6: Conventional problems.

The recent application in portable equipments requires the high-speed load

transient response less than 0.5µs for load variation. This clearly shows that

the conventional method reported in [26] can not reach the above requirement.

The conventional method is available for only slow-speed load transient response

since it used the DC boosting technique. In DC boosting technique, the boosting

circuit monitors the change of power MOSFET gate potential and increase the

bias current of error operational amplifier in order to obtain high-speed response.

However, to obtain a high driving capability, power MOSFET is designed in a very

big size resulting in a very large gate capacity. For example, as shown in Figure

24

2.4 Power Supply Rejection Ratio (PSRR) Characteristics

2.6, to obtain the 300mA driving capability, the size of power MOSFET becomes

over than 30,000µm. Then, the gate capacity is up from 150pF to 250pF. When

load suddenly changes, the output voltage is first supplied by decupling capacitor.

Responding to that, error amplifier lowers power MOSFET gate potential in order

to rise up output voltage. But this builds up the time constant to charge the gate

capacity of power MOSFET. In other words, the load transient response of the

LDO voltage regulator is originally limited by the slew rate at the gate drive of

the power MOSFET.

Imagine the output impedance of error amplifier is 10kΩ (at 3V supply voltage

and 333µA bias current), the time constant of power MOSFET gate becomes

more than 2µs. This means that the 0.5µs of load transient response can not be

achieved. To obtain the time constant below 0.5µs, thus, the bias current must

be above 1mA. So this technique cannot actualize low power consumption.

The requirement of load transient response is not only what we mention above.

Normally, the drop voltage when load suddenly changes is demanded, if possible,

to stay in 2% or less of setting output voltage. Until recently, in order to keep the

drop output voltage at minimum value, a big output capacitor is used. But big

output capacitor needs large areas, so that it cannot mount on the small-sized

portable device.

2.4 Power Supply Rejection Ratio (PSRR) Char-

acteristics

2.4.1 Definition of PSRR Characteristic

Power supply rejection ratio (PSRR) is the ratio of the change in output voltage

VOUT to the change in input voltage supply VDD. It is also defined as the AC

voltage gain from the input node to the output node of the LDO regulator. PSRR

is simulated by performing an AC sweep of the input voltage supply and plotting

the ratio of the output voltage to the input voltage. PSRR is measured at the

frequencies of interest in dB as shown in Figure 2.7

25


Figure 2.7: Definition of PSRR.

2.4.2 Analysis of PSRR Characteristic

As we have mentioned about the important role of ripple rejection of LDO in

the electronic devices, it is therefore imperative to analyze the PSSR of LDO

over a large frequency range with the aim of establishing design guidelines and

principles for high PSRR performance. In this section, the detail analysis has

been done.

Let’s do the consideration on the power supply rejection ratio (PSRR) of

conventional LDO structure shown in Figure 2.2. In this conventional structure,

PSRR can be determined by two models which are so called Simple Model

and Model In Action Over Wide Frequency Range. The model in action

over wide frequency range are divided into three regions of frequency. They

are the PSRR at DC and a low frequency PSRRDC (several Hz), the PSRR at a

moderate frequency PSRRMF (about 10KHz), and the PSRR at a high frequency

PSRRHF [27].

2.4.2.1 Simple Model for PSRR of LDO

In its simplest form, a ratio of the output to the supply ripple rejection ratio

which is also known as the PSRR transfer function, can be viewed as the effect of

a voltage divider caused by an impedance between the supply and the regulator

output and an impedance between the output and ground. An intuitive and

26


insightful model for analyzing the power supply rejection of a typical LDO is

presented in Figure 2.8.

Figure 2.8: Simple model for PSRR of LDO.

This model consists of an impedance ladder comprising of the channel resis-

tance of the power MOSFET (rds) , and a parallel combination of the open-loop

output resistance to ground (ZO) and the shunting effect of the feedback loop

(ZO−reg). ZO is effective when loop gain is low (moderate to high frequencies)

while ZO−reg is effective when loop gain is high (low to moderate frequency).

Hence, referring to Figure 2.2, we can see that,

ZO = (ZCOUT + ZESR)//(R1 + R2) (2.22)

And,

ZO−reg =Z0//rds

Aolβ(2.23)

The model is presented in Figure 2.8. Thus, by simplifying the model in

Figure 2.2 to one in Figure 2.8, the PSRR can be seen to be,

27


PSRR =VOUT

VDD

=(ZO//Z0−reg)

rds + (Z0−reg)(2.24)

2.4.2.2 Model in Action over Wide Frequency Range

This sub-section shows a typical PSRR characteristic and the discussion of how

the intuitive model allows us to determine the PSRR performance of an LDO over

a large range of frequencies, simply by accounting for the frequency dependence

of Z0 and ZO−reg.

1. PSRR at DC and Low Frequencies

At low frequencies, the high loop gain of error amplifier (Aol−dcβ) allows

ZO−reg to shunt ZO, and since rds, for the most pan, significantly lower than

R1 + R2, the following simplification can be derived,

PSRRDC =R0−reg

rds + R0− reg

=

rds//(R1+R2)Aol−dcβ

rds + rds//(R1+R2)Aol−dcβ

(2.25)

Since Rds >> (R1 + R2) then,

PSRRDC ≈rds

Aol−dcβ

rds + rds

Aol−dcβ

≈ 1

Aol−dcβ(2.26)

Consequently, the PSRR of the regulator is intimately related to the open-

loop gain of the system. Line regulation is the output voltage change as a

result of a specific change in input voltage at a specific load current. Line

regulation is simulated by performing a DC sweep on the input voltage

and plotting the output voltage. Additionally, the two-stage operational

amplifier driver suffers from poor bandwidth due to presence of closely

spaced low frequency poles. In such a situation, a single-stage operational

28


amplifier driver is the obvious choice, due to ease of compensation. However,

due to lower DC gain, the single-stage operational amplifier driver circuit

suffers from poor line regulation and temperature performance.

2. PSRR at Moderate Frequencies

The shunting effect of the feedback loop, however, deteriorates at frequen-

cies beyond the bandwidth of the amplifier, BWA (or dominant pole, PoA),

thereby causing an increase in the regulated output impedance, ZO−reg.

This leads to a rise in the output ripple and, consequently, the dominant

PSRR breakpoint in the form of a PSRR zero (Z1). The resultant degra-

dation in the PSRR can be obtained by replacing Aol−dc in Equation (2.26)

with the bandwidth limited response of the loop at frequencies where is

greater than one, i.e. between DC and the unity-gain frequency (UGF ) of

the system. This leads to,

PSRRMD(f≤UGF ) ≈ Z0−reg

rds + Z0−reg

(2.27)

≈ rds

(Aolβ)rds + rds

(2.28)

≈ rds

( Aol−dc

1+ sP0−A

β)rds + rds

(2.29)

≈1 + s

P0−A

(1 + Aol−dcβ)[1 + s(1+Aol−dcβ)P0−A

](2.30)

≈ 1 + sBWA

(Aol−dcβ)(1 + sUGF

)(2.31)

The presence of a PSRR pole (p1) at the unity-gain frequency, as predicted

by Equation (2.31), can be easily understood when we note that the deterio-

ration of the PSRR due to increasing closed-loop output resistance ceases at

the UGF . At this stage, the shunting effect of the feedback loop no longer

exists and the PSRR is determined simply by the frequency-independent

resistive divider between the channel resistance of the power MOSFET (rds)

and resistors (R1 + R2) of feedback network. The PSRR is given by :

29


PSRRMD(f=UGF ) ≈ Z0

rds + Z0

(2.32)

≈ R1 + R2

R1 + R2 + rds

(2.33)

≈ 1 (2.34)

At these frequencies, the PSRR of the system is the weakest since the closed

loop output resistance is not decreased by the feedback loop and the output

capacitor cannot shunt the output ripple to ground.

3. PSRR at High Frequencies

When the output capacitor starts shunting (R1 + R2) to ground, a smaller

ripple appears at the output, thereby causing an improvement in the PSRR

(since Z0 decreases with increasing frequency) and the second PSRR pole

(p2).

Thus,

PSRRHF (f>UGF ) ≈ Z0

rds + Z0

(2.35)

≈ ZCOUT

ZCOUT + rds

(2.36)

The effectiveness of the output capacitor is, however, restricted by its ESR.

At very high frequencies, since this capacitor is an AC short, ZO is deter-

mined by the ESR, which limits PSRR to,

PSRRfÀUGF ≈ Z0

rds + Z0

(2.37)

≈ RESR

RESR + rds

(2.38)

Thereby leading to the formation of an effective PSRR zero at,

Z2 =1

2πRESRCOUT

(2.39)

30

2.5 Inrush Current Characteristic

Though the simple model depicted in Figure 2.8 provides an intuitive un-

derstanding of the relationship between PSRR and the open-loop gain of the

regulator, it does not take into account the effect of the conduction of the supply

ripple through the amplifier itself. This ripple feed through bas significant impli-

cations for high PSRR design and is critical for determining the optimal amplifier

topology for a particular type of output stage.

2.4.3 Design Obstacles of PSRR

To reduce ripple noise voltage, needless to say, it is required to maintain a proper

response speed of the error amplifier. This is the main reason why the bias

current of the error amplifier cannot be reduced. As a result, a low power LDO

having a high PSRR performance can not be realized with a conventional LDO

structure [28]-[31]. From Equations (2.26) and (2.31), we can find that the PSRR

of each region can be improved by using a high loop gain and wide bandwidth

error amplifier. However, it is a very hard work to achieve this kind of amplifier.

That is, to achieve a high loop gain amplifier, it is needed to increase the number

output stages. And, this will not only increase the power consumption of the LDO

but also result in a narrow bandwidth and a complicated phase compensation. A

narrow bandwidth also means slow response time of the LDO. Hence, more bias

current will be needed. Such that contradicts to our purpose of achieving a low

power consumption LDO.


LDO is widely built into all electronic appliances by all means not only for

portable electronic devices. In order to save the power consumptions of the

devices, the power management system has become more important. This means

stopping partly the internal clock for an inactive block to lower consumed cur-

rent and restarting the operation according to the need. However, the problem

of inrush current of the system is becoming a new topic for the users.

31


Figure 2.9: Inrush current of LDO in application.

2.5.1 Definition of Inrush Current

Generally, the inrush current refers to the maximum, instantaneous input current

drawn by an electrical device when it first turned on.

Let’s consider the characteristic of inrush current of the conventional structure

of the LDO at start-up moment. As shown in Figure 2.9, to ensure that LDO

operates stably and has the good performance of load transient response, the

bigger output capacitor COUT is commonly utilized. At VOUT start-up moment,

the bigger COUT is, the bigger inrush current will occur. Inrush current is included

not only the rush current flowed into COUT , but also the current flowed into input

capacitor CIN . However, CIN is comparatively smaller than COUT and is fixed at

any using condition. Hence, when discussing about inrush current of LDO, rush

current of COUT is the only main factor to be discussed.

2.5.2 Analysis of Inrush Current of LDO

Figure 2.10 shows the structure of the conventional LDO [32]. Let’s consider the

start-up characteristic of this kind of LDO when chip enable CE or VDD turns

on.

32


Figure 2.10: Structure of conventional LDO circuit.

Figure 2.11 shows an example of the start-up manner of a conventional LDO.

At start-up moment, first, the reference voltage VREF rises up. However, the

feedback voltage VFB which is divided from VOUT by feedback network, is still in

low state. This makes the error amplifier mistakes that the output voltage VOUT

is in low state and pulls down the power MOSFET gate PD to ground as hard as

possible. At this moment, the large inrush current will flow through the power

MOSFET to charge the output capacitor after a short delay [33].

2.5.3 Design Obstacles of Inrush Current Limiting

The conventional circuit in reference [32] solved the above problems by adjusting

the rise time of VREF . It is realized by using the charge time of the on-chip

33


Figure 2.11: Start-up characteristic of LDO and its inrush current.

current source ISS into the off-chip capacitor CSS connected to SR terminal in

Figure 2.10. This time is defined by :

TSS =VREF × CSS

ISS

(2.40)

However, this method has some demerits. Since CSS is an off-chip element, it

is needed to secure the area for CSS and so the cost for mass production can not

be decreased. It is unsuitable for the integrated circuit. In addition, if the value

of CSS is decided, the start-up time of the output voltage is decided regardless of

the output capacitor and the load current. This also means the output of LDO

cannot be started at high speed. Moreover, big CSS of several nF is needed to

achieve the small inrush current and the start-up time is up to several ms.

34

2.6 Load Regulation Characteristic


2.6.1 Definition of Load Regulation

Load regulation is the ratio of the change in output voltage VOUT to the change

in load current ILOAD. Load regulation is simulated by performing a DC sweep

on the load current and plotting the output voltage. Then the load regulation of

the regulator is represented by :

Ro−reg =∆VOUT

∆ILOAD

(2.41)

2.6.2 Analysis of Load Regulation

Load regulation is limited by the frequency response of a typical low dropout

regulator architecture under loading conditions. Load regulation is defined as

the output voltage variation resulting from a unit load current change, which is

equivalent to the output resistance of the regulator Ro−reg.

Ro−reg =∆VOUT

∆ILOAD

(2.42)

=RON−PWT

1 + Aol × β(2.43)

Where, ∆VOUT and ILOAD are the output voltage and the load current changes

respectively. RON−PWT is the output resistance of the power MOSFET. Aol is the

open-loop gain of the system while β is the feedback factor. Thus, load regulation

performance is determined by the open-loop gain of the system. Unfortunately,

the DC gain is limited by the frequency response of the regulator.

Figure 2.12 shows the most typical LDO structure with power MOSFET as a

PMOS power transistor.

The power MOSFET exists between the input pad Vip and output pad Vop.

The error amplifier works as a gain stage in the feedback loop to maintain a

predefined output voltage. It works by comparing the reference voltage VREF

and the feedback voltage VFB determined by resistor R1 and R2.

35


Figure 2.12: Typical LDO structure with bonding wire.

Let’s define the symbols used in this chapter. Vip and Vop stand for the input

and output voltage at the IC pad of the LDO. VDD and VOUT stand for the

input and output voltage at the package pin of the LDO. VREF and ILOAD are

the reference voltage and the load current, respectively. RWI is the boding wire

resistance. Generally, the load regulation of the LDO means that at the output

pin of the LDO package, and is represented by∆VOUT

∆ILOAD

which can be expressed

as follows.

∆VOUT

∆ILOAD

=∆Vop −RWI ×∆ILOAD

∆ILOAD

(2.44)

Where, ∆VOUT and ∆Vop are the fluctuation of VOUT and Vop, respectively, when

the load current ∆ILOAD changes. Therefore, ∆Vop and RWI are the main factors

to determine the load regulation characteristics. The output voltage Vop of LDO

at the IC pad is defined as follows.

Vop =R1 + R2

R2VREF (2.45)

From Equation (2.45), it seems that Vop has no relation with ILOAD. However,

the output voltage Vop decreases according to the increasing of the load current

36


Figure 2.13: Bonding wire in IC package.

ILOAD. This is due to the operating current of the NMOS transistor at the input

stage of the differential amplifier becomes unbalance. Then, the offset occurred

at the gate-source of the two transistors. By enlarging the gate size of power

MOSFET, it is possible to prevent the decrease of the output voltage Vop when

the load current ILOAD increases. That is, by doing this, the output ability of the

power MOSFET is increased.

2.6.3 Design Obstacles of Load Regulation

Figure 2.13 shows the Au (Gold) bonding wire in SOT-23 package. It lies between

an IC pad and a package pin and supposed to have impedance of 0.556nH and

92mΩ [34].

Suppose that an LDO is designed for a load current of 300mA, then with the

above bonding wire impedance, a drop between the output pin and the IC pad

37

2.7 Over Current Protection Circuit

will be 27.6mV. This drop voltage preponderantly exceeds the permitted range of

2% fluctuation of the LDO output voltage. A compensation for this drop voltage

by some ways becomes necessary. The problem can be solved by increasing a pin

for detection of the output voltage at the IC package pin. However, it gives some

disadvantages such as an enlargement of the package size and an increment of a

production cost.

Additionally, the two-stage operational amplifier driver suffers from poor

bandwidth due to presence of closely spaced low frequency poles. In such a situa-

tion, a single-stage amplifier driver is the obvious choice, due to ease of compensa-

tion. However, due to lower DC gain, the single-stage amplifier driver circuit suf-

fers from poor load regulation, line regulation and temperature performance[35].

In this work, we do not to discuss about the possibility of the proposed circuit

to compensated such this problem. We design the size of power MOSFET large

enough, so that, basically almost no fluctuation of Vop will occur when the load

current changes. For example, in case of 0.18µm CMOS process, at the smallest

channel length and 30,000µm channel width, the fluctuation of output voltage

∆Vop is not bigger than 3mV when the load current ILOAD changes from 0mA to

300mA. Suppose that ∆Vop=0, then only the bonding wire resistance RWI will

deteriorate the load regulation characteristic.

At this time, from Equation (2.44), the load regulation of the LDO becomes

as follows.

∆VOUT

∆ILOAD

=−RWI ×∆ILOAD

∆ILOAD

(2.46)

This shows that the load regulation characteristic of LDO relays mainly on

the bonding wire resistance RWI between IC pad and Package lead. Hence, the

technique to recover the drop voltage by this wire is one of many obstacles in

LDO design.


An important aspect to consider when designing regulators is a protection against

undesirable factors that are inherent to the working environment of the applica-

38


tion. Since the power MOSFET device dissipates the most power, protection

usually revolves around its operating conditions. Protection circuitry is typi-

cally inactive during safe operating conditions and becomes active only if a safety

limit is violated. The most common forms of protection include overload current

protection, reverse battery protection, thermal shutdown protection, and electro-

static discharge (ESD) protection. However, caution must be exercised not to

significantly degrade the performance of the regulator during normal conditions

by the mere presence of the protection.

2.7.1 Definition of Over Current Protections Circuit

Over current protection ensures that the current through the power MOSFET

stays within a specified range. A violation of this could result in damage or

destruction of the device. So far, there are only few papers published on the

design of Over Current Protection Circuit, especially on the design method for

precise and stable holding current circuits as well as limiting current circuits in

LDO. It, however, has been discussed in some previous works [36]-[38].

Figure 2.14: Over current protection circuit in LDO.

Figure 2.14 shows the Over Current Protection Circuit in the most basic LDO

structure. Generally, the Over Current Protection Circuit works by monitoring

39


the gate voltage of power transistor which is equivalent to load current. This

circuit works to shut down VOUT when the load current exceed limit current and

reduce the output current to a holding current to avoid large power dissipation.

2.7.2 Design Obstacles of Over Current Protection Cir-

cuit

The problem which mostly occurs is the malfunction of Over Current Protection

Circuit that makes VOUT unable to start up.

Figure 2.15: Latchup effects of over current protection circuit.

The method of current control can usually be classified as either “constant-

current” or “current-fold back” current limiting. In the case of overload or short

to ground, constant current limiting will limit the output current at a maximum

rate which will cause large power dissipation. Alternately, with another scheme,

the allowable current will fold back as VOUT falls due to increasing overload, until

it reaches some much lower value. Thus, the power dissipation is reduced. But

this protection scheme is potentially subject to latch-up because of the nonlinear

loads’ influence to VOUT during the start-up of regulators[39]-[42].

Latchup occurs when the static load line intersects the fold back current curve

as shown in Figure 2.15 because the load draws more current than the regulator

40


Figure 2.16: Problems when avoiding latch up effects.

can supply at the voltage where the curves intersect [43],[44]. Generally, this

problem can be solved by enlarging the slope of the fold back curve to avoid the

intersection. But this will sacrifice the internal power dissipation and lower the

fold back characteristic.

Reference [39] presents a protection circuit which can avoid latch-up effect

by combining the fold back current limiting with constant current limiting to

change the slope of fold back curve such as shown in Figure 2.16. The latch-up

effect might be solved by the previous circuit [39]. However, as shown in Figure

2.16, VOUT first falls to the middle level voltage before it completely shuts down.

This kind of characteristic is not favorable for most of applications. Reference

[41] presents a protection circuit which can avoid latch-up effect by connecting a

power pass device outside. However, this kind of circuit is not suitable for on-chip

LDO design.

41


42

Chapter 3

HIGH PERFORMANCE LDO

AND ITS SPECIFICATIONS

3.1 Target LDO

Voltage regulation is required for various functions in most electronic systems. To-

day’s electronic systems demand better regulating performance, higher efficiency

and lower parts count. This growing demand is mainly due to the increasing de-

mands for portable telecommunication and computer products that require ever

higher power efficiency. Besides power efficiency, supply voltage compatibility

problems also demand the use of regulators.

The explosive proliferation of battery-operated equipment such as cellular

phones, notebook computers, and palmtop computers in the past decade have

accelerated the development and usage of LDO and low quiescent current linear

regulators. LDO is widely built into all electronic appliances by all means not

only for portable electronic devices. The number of electronic equipments which

are operating in the world is presumed several hundreds million units. Assume

that one LDO is operating with 200µA and 3V power supply voltage, with five

hundreds million units, it becomes a hundred thousand ampere of current and

three hundreds kilowatt of power will be consumed. An effort to improve the per-

formances of LDO without increasing the power consumption plays an important

role to save the world energy.

43

3.1 Target LDO

Recently, in order to save power consumptions, a system that was originally

supplied by one LDO is divided into many blocks and supplied by many LDOs.

This means that the power is supplied only to operating blocks and non-operating

blocks are made into standby mode. So the power consumption can be saved for

the whole system. This means stopping partly the internal clock for an inactive

block to lower consumed current and restarting the operation according to the

need. In this condition, seeing from LDO side, the load changes instantaneously

from un-loaded to full loaded states. Hence, the high speed load transient re-

sponse is required to LDO.

When an operation voltage of electronic devices is supplied by a DC-DC con-

verter, it is impossible to avoid ripple noise voltage that comes along a power

supply line. For the communication devices such as mobile phones which have

transmission and reception circuits operating at a high frequency, the ripple noise

of power supply line has bad influence on the stability at transmission frequency.

The instability at transmission frequency will result in a deteriorated voice or

communication quality. Hence, it is necessary to reduce the ripple noise voltage

as much as possible. Furthermore, when considering the matter from a different

angle, the close proximity of analog and digital circuits in SoC environments can

cause them to be overwhelmed by spurious switching noise signals propagated

through supply lines, interface nodes, and substrate injection. In these VLSI

circuits, LDOs form an indispensable component of the power management sys-

tem. They generate stable voltages while supplying a wide range of currents to a

variety of circuits. They also filter the fluctuations in the power supply, thereby

shielding their load circuits from supply ripple. Thus, in circuits like DRAMs,

PLLs and EPROMs, where power supply noise directly translates to degrada-

tion in system performance, power supply rejection is a key figure of merit for a

voltage regulator [28].

Suppose a power management IC contains a DC-DC converter followed by

several channels of LDO shown in Figure 3.2 which is reported in [45]. When two

or more LDOs start up at the same time, the inrush current which flowed into

the output capacitor will superimpose each other resulted in a very large inrush

current. This current might exceed the driving ability of the DC-DC converter.

Hence, the output voltage of DC-DC converter badly falls down for the start-up

44

3.1 Target LDO

instant. This will lead to the malfunction of the device in case the main processor

is supply by the same DC-DC converter.

Table 3.1: Electrical performances summary of proposed LDO.

Technology 0.18µm CMOS

Output Voltage Range (VOUT ) 0.9∼ 1.5V

Input Voltage Range (VDD) 0 ∼ 2.5V

Maximum Output Current 150mA

Dropout Voltage

(VOUT = 1.2V, ILOAD = 150mA) <600mV

Quiescent Current (No load) <10µA

Quiescent Current (Full load) <40µA

Line Regulation

(ILOAD = 50mA) <0.3%/V

Load Regulation

(VDD = VOUT + 1V) <0.1mV/mA

Load Transient

(ILOAD = 0.1 ⇐⇒ 150mA, COUT =4.7µF) <100mV

PSRR @ 10Hz

(VOUT = 1.2V, ILOAD = 50mA) >70dB

PSRR @ 1KHz

(VOUT = 1.2V, ILOAD = 50mA) >60dB

Output Capacitor Range (COUT ) 0.47∼ 4.7µF

Inrush Current IINRUSH (COUT =4.7µF) <150mA

Attendant upon a scaling of semiconductor process in recent years, an oper-

ating voltage of a signal processing integrated circuit such as CPU has decreased

steadily and finally it became lower than 1V. Because of this, a demand for a new

output voltage precision appeared vis-a-vis the power circuit. For example, if the

power supply voltage is 0.9V, 2% precision of an output voltage of an LDO is

permitted only to 18mV. With a high load current flows through an LDO which

uses a power MOSFET, it is impossible to ignore a resistance of a bonding wire.

45

3.2 Design Challenge

As mentioned above, totally, the target LDO of this research is to design a

high performance of low drop-out (LDO) regulators for battery powered electron-

ics. This is targeted to fulfill the present commercial requirements as well as the

projected demands of the future. Such an endeavor makes certain characteris-

tics necessary such as low quiescent current flow for increased battery life, low

voltage operation, and high output current. The techniques that are proposed to

overcome the aforementioned obstacles of the prevailing LDO circuit architecture

and as a result each of its main characteristics such as load transient response,

power supply rejection ratio, inrush current characteristic, and load regulation

are together enhanced.

The research is done with existing standard CMOS technologies. Thus, the

designs take full advantage of all physical aspects of the process while maintaining

fabrication cost to acceptable and competitive levels. Moreover, the new design

techniques will be able to further exploit the benefits of more advanced technolo-

gies in the future. The target LDO has the electrical specifications as shown in

table 3.1


3.2.1 Load Transient Response

As mentioned in chapter 2, in LDO design, large gate capacitance of power MOS-

FET degrades the loop-gain bandwidth and the slew rate at the gate drive of the

LDO in low power condition. Both low quiescent current and high-speed load

transient response, therefore, cannot be achieved simultaneously by using the

generic LDO structure. Here, the design of low operating current LDO, with

high-speed load transient response but not utilizing big capacitor, has come out.

And that is the main purpose and the design challenge of the research.

3.2.2 Power Supply Rejection Ratio

Refer to the analysis of PSRR characteristic, for the conventional LDO structure,

the power supply rejection ratio (PSRR) can be determined in three regions of

46


frequency. They are the PSRR at DC and low frequency PSRRDC (several Hz),

the PSRR at a moderate frequency PSRRMF (about 10KHz), and the PSRR at

a high frequency PSRRHF which are summarized as follows [54].

1. The first region of the PSRR at DC and low frequency is intimately related

to the open-loop gain of the system and expressed by :

PSRRDC ≈ 1

Aol−dcβ(3.1)

Here, Aol−dc is the open-loop gain of the system and β is defined by R2/(R1+

R2).

2. The second region of the PSRR at a moderate frequency is intimately re-

lated to the open-loop gain of the system and the bandwidth of the amplifier.

It is, thus, expressed by :

PSRRMF ≈1 +

s

BWA

(Aol−dcβ)(1 +

s

UGF

) (3.2)

3. The third region of the PSRR at a high frequency is intimately related to

the feedback network, the output capacitor COUT and the equivalent series

resistor RESR. It is, thus, expressed by :

PSRRHF(f) ≈

1, (f = UGF )

ZCOUT

ZCOUT+ rds

, (f > UGF )

RESR

RESR + rds

, (f >> UGF )

(3.3)

Here, BWA is the bandwidth, UGF is the unity-gain frequency of the error

amplifier, rds is the ON resistor of Power MOSFET of the LDO.

47


Figure 3.1: PSRR deterioration by reducing power consumption.

From Equations (3.1) and (3.2), the PSRR of each region can be improved

by using a high loop gain and wide bandwidth error amplifier. However, it is a

very hard work to achieve this kind of amplifier. That is, to achieve a high loop

gain amplifier, it is needed to increase the number output stages. And, this will

not only increase the power consumption of the LDO but also results in a narrow

bandwidth and a complicated phase compensation. A narrow bandwidth also

means slow response time of the LDO. Hence, more bias current will be needed

which conflicts the purpose of achieving a low power consumption LDO.

Figure 3.1 shows the deteriorates of PSRR by reducing the power consumption

of error amplifier. Thus, the design of low operating current LDO to recover the

PSRR deteriorated by lowering current consumption, is the main purpose and

the design challenge of the research.

48


In this work, we had focused on improving of PSRRDC and PSRRMF which

are generally demanded by most of applications. The proposed circuit should

be the circuit of which the open-loop gain and open-loop bandwidth of the error

amplifier as well as the unity gain frequency are not necessarily considered.

3.2.3 Inrush Current

Suppose a power management IC contains a DC-DC converter followed by several

channels of LDO shown in Figure 3.2 which is reported in [45]. When two or more

LDOs start up at the same time, the inrush current which flowed into the output

capacitor will superimpose each other resulted in a very large inrush current.

This current might exceed the driving ability of the DC-DC converter. Hence,

the output voltage of DC-DC converter badly falls down for the start-up instant.

This will lead to the malfunction of the device in case the main processor is

supplied by the same DC-DC converter.

Figure 3.2: Power management IC system.

To avoid the problems mentioned, an inrush current limiting circuit for LDO

with a high speed soft start time and a low inrush current is needed. The design

challenges are to find the method of limiting inrush current without using the

49


external capacitor CSS. So, the cost for mass production can be decreased and it

is suitable for the integrated circuit. Moreover, the designed circuit should be the

circuit which enables LDO to have high speed start-up at any using condition.

And that is the main purpose and the design challenge of the research.

3.2.4 Load Regulation

In order to improve the load regulation of the LDO, the design challenge here is

to compensate the drop of VOUT which is caused by RWI as shown in Figure 3.3.

Hence, a flat load regulation characteristic can be realizable.

Figure 3.3: Design challenge of load regulation.

3.2.5 Over Current Protection Circuit

Since the over current protection plays an important role in protecting LDO

from damages, the design of low operating current LDO with high accuracy over

current limiting circuit and stable holding current without latch-up problem has

come out. And that is the main purpose and the design challenge of the research.

50

Chapter 4

PROPOSED HIGH

PERFORMANCE LDO

4.1 Quick Response Technique for Fast Load Tran-

sient Response

4.1.1 Circuit Feature

In this section, a design technique of low power fully CMOS low dropout regulator

(LDO) based on Quick Response Circuit to provide a fast load transient response

is proposed. the LDO with proposed circuit can catch instantaneous load fluctu-

ation even though it is in low-power operating condition. Furthermore, no matter

how fast the load changes, safe mechanism is proposed in order that LDO does

not fall to unstable state. Implemented in 0.18µm CMOS technology, the LDO

with proposed Quick Response Circuit can achieve a fast load transient responses

with less transient overshoot or undershoot when driving a large load current.

4.1.2 Proposed Concept and Operation Principle

To solve the problem of load transient response, a Quick Response Circuit is

proposed to charge and discharge the charge in gate of power MOSFET adding to

the conventional boosting technique [46]. The proposed circuit is placed between

the Error Amplifier and power MOSFET as shown in Figure 4.1.

51

4.1 Quick Response Technique for Fast Load Transient Response

Figure 4.1: Concept of proposed quick response circuit.

Excluding the proposed DC Boosting circuit and PD Charge/Discharge

circuit, Figure 4.1 shows the structure of the conventional LDO used to eval-

uate and confirm the effectiveness of the proposed concept and full circuit in

this section. It is the LDO regulated by one stage amplifier with NMOS input

stage. Capacitor Cc1, Cc2 and resistance Rc are working together as the phase

compensation circuit to stabilize the LDO.

As mentioned in previous section, the objective of this work is to find the way

to control the gate capacitance of power MOSFET which does not depend on the

error amplifier speed when load current immediately changes. So, here, the bias

current of the error amplifier is designed to the lowest value and the transient

response of error amplifier to help recover VOUT from the drop by load current

change, is not expected.

So far, there were many reports described on how to fasten the control speed of

power MOSFET’s gate in order to achieve the high speed load transient response.

For example, a method reported in [47] is realized by inserting a voltage buffer

driver between the error amplifier and the power MOSFET. The voltage buffer

should improve both the loop-gain bandwidth and slew rate at the gate drive of

52


the power transistor, while the buffer dissipates small quiescent current in the

static state. However, it is difficult to realize a good voltage buffer to meet the

requirements perfectly in practice [47]. It means that it is necessary to analyze

and assure that at any load condition, the driver would not make the LDO fall

to unstable state.

Figure 4.2: Structure of proposed circuit.

In this work, Quick Response Circuit is proposed in order to dynamically

charge and discharge the parasite capacitor contained in the gate of power MOS-

FET. The proposed Quick Response Circuit is designed to react when only the

load current dynamically changes. Thus, at normal load current state, LDO gets

no effect from the proposed circuit [6]-[8].

53


Figure 4.2 shows the block circuits of proposed Quick Response Circuit. It is

built up with a memory circuit in MEMORY, two comparators with input offset

voltage in COMPARATORS, a power MOSFET gate (PD) charge circuit in

PD-CHARGE, a PD discharge circuits in PD-DISCHARGE, and VOUT dis-

charge circuits in VOUT-RESTRAIN followed by a conventional bias boosting

circuit in DC-BOOSTING.

Let’s summarize the operation principle of the LDO with proposed Quick

Response Circuit adopted as following.

1. At stable load current state

At stable load current state, the output voltage of the regulator VOUT is

memorized by the memory circuit MEMORY. The comparators circuit

will compare the memorized output voltage VME and the present output

voltage VOUT by monitoring these two nodes differential voltage (VOUT -

VME) to its input offset voltage. Let’s make the differential voltage of the

two nodes as ∆Vpm=VOUT -VME, the input offset voltage of first comparator

COM1 as Vio1 and the input offset voltage of second comparator COM2 as

Vio2.

At this state, since the load current is stable, the different voltage between

VOUT and VME is almost zero. Hence, ∆Vpm < Vio1 and ∆Vpm < Vio2. The

charge circuit of power MOSFET gate capacitor PD-CHARGE , and dis-

charge circuit PD-DICHARGE as well as output voltage discharge circuit

VOUT-RESTRAIN are designed to be active when only the condition

∆Vpm > Vio1 or ∆Vpm > Vio2 is reached. So, at stable load current state,

all of them are turned to inactive mode and let the error amplifier works

to regulate VOUT as normal. The static power of LDO can be saved for the

full LDO circuit.

2. When load current changes from light to heavy load

When load current changes from light to heavy Load, the output voltage

will sharply drop due to the late response of low power error amplifier. At

this time, the comparators so-called COM1 and COM2 compare the level

of memorized voltage VME to the drop of present output voltage VOUT and

54


define whether the load current changes from the light current to heavy

current or vice versa.

If the load current changes from light to heavy, we got ∆Vpm > Vio1 and

the comparator COM1 reacts. By getting the signal from COM1, the dis-

charge circuit PD-DISCHARGE will respond immediately to discharge

the charge at power MOSFET gate. Since PD is pulled down to ground,

power MOSFET future turns ON to recover VOUT , so that the output volt-

age drop can be minimized at the smallest drop level.

3. When load current changes from heavy to light load

At the same manner, when load current changes from light to heavy load,

the output voltage will sharply overshoot due to the late response of low

power error amplifier. At this time, the comparators so-called COM1 and

COM2 compare the level of memorized voltage VME to the drop of present

output voltage VOUT and define whether the load current changes from the

light current to heavy current or vice versa.

If the load current changes from heavy to light, we got ∆Vpm > Vio2 and

comparator COM2 reacts. By getting the signal from COM2, the charge

circuit PD-CHARGE will respond immediately to discharge the charge

at power MOSFET gate and restrain VOUT from overshoot. Since PD is

pulled up to VDD, power MOSFET future turns OFF to reduce overshoot

of VOUT . At the same time, VOUT-RESTRAIN reacts by signal from

COM3 which is the inverse signal of COM2. Then, VOUT overshoot is

restrained by VOUT-RESTRAIN. So the overshoot of output voltage

VOUT can be minimized at the smallest overshoot level.

4.1.3 Circuit Design

In this section, the completed LDO with adopted proposed Quick Response Cir-

cuit is discussed in transistor level.

Figure 4.3 shows the designed LDO with completed circuit of proposed Quick

Response Circuit implemented. The designed LDO contains five main blocks,

which are discussed in transistor level in next subsection. The reference voltage

55


and bias generation block which are comparatively not related to proposed Quick

Response Circuit, are abbreviated. The five blocks contain the following circuits.

1. Voltage Reference and Current Source: The voltage reference gener-

ation circuits are added for supplying the reference voltage to LDO system.

2. Error Amplifier and Power MOSFET: The core circuit of LDO in

which error amplifier, DC boosting circuit, power MOSFET as well as phase

compensation circuit are added.

3. Feedback Network: The feedback resistance R1 and R2 are formed in

series to provide the feedback voltage VFB which is divided from VOUT .

4. Memory and Comparators: A part of proposed Quick Response Circuit

in which the memory circuit and comparator circuits are added.

5. PD-Charge and PD-Discharge and VOUT-RESTRAIN: A part of

proposed Quick Response Circuit in which the charge and discharge circuit

of power MOSFET’s gate as well as the restrain circuit of VOUT are together

added.

56


Figure 4.3: Completed LDO circuit with quick response circuit.

4.1.3.1 Error Amplifier with DC Boosting Circuit

Figure 4.4 shows the completed circuit of the error amplifier with DC boosting

technique used with our proposed Quick Response Circuit. It is a very simple

structure like general one stage amplifier LDO.

The DC boosting circuit is formed by MA6, MA7, MA8 and MA9. It operates

as following. At low load current (here, the low load is defined to ILOAD < 2mA),

the amplifier works with low bias current Ib1. When load current increases, the

gate voltage PD of power MOSFET decreases to further turn ON power MOSFET

to supply the shortage current. This decreasing of PD will invert the single-end

amplifier (MA8, MA9) from low level VSS to VDD when PD goes across the

57


threshold voltage VBOOST of this amplifier. The threshold voltage VBOOST is

designed to be equal to PD level at which the load current ILOAD=2mA. When

single-end amplifier (MA8, MA9) turns from VSS to VDD, MA7 turns ON and the

bigger bias current Ib2 which is generated by MA6 will be available to maintain

the other characteristic such as power supply rejection ratio, noise, etc [61].

Figure 4.4: Completed error amplifier with DC boosting circuit.

This boosting technique is not enough to achieve a high speed load transient

response since there is the limit of bias current of error amplifier, single-end

amplifier to keep the system operates stability with low power system. Thus, we

will add the PD-CHARGE and PD-DISCHARGE circuit to help LDO have

enough load response speed.

4.1.3.2 Memory Circuit

Figure 4.5 shows the memory circuit utilized in proposed Quick Response Circuit.

The memory circuit is formed by transistor MD1, MD12, MD13 and the capacitor

CD1. In this circuit, the capacitor CD1 works to memorize VOUT at static state.

Let’s make the bias current flow through MD1 as Ib.

58


Figure 4.5: Completed memory circuit used in proposed circuit.

This structure will provide the charge or discharge time of VOUT into or out

from capacitor CD1 and is defined by the constant current Ib and VOUT itself.

Generally, it is the time constant of CD1 and ON resistance of MD12. Since

MD12 and MD13 are formed in current miller, current flows through MD12 is

also Ib. Hence, we got ON resistance of MD12 and the charge time τ of VOUT as

following.

RonMD12 =VOUT

Ib(4.1)

τ = RonMD12 × CD1 (4.2)

=VOUT

Ib× CD1 (4.3)

In this work, the setting target of rise and fall time of load current fluctuation

is less than 0.5µs. In order to makes it possible to memorize VOUT , the time

constant τ must be designed to be greater than 0.5µs. An example in this work,

CD1 is set to 10pF and Ib to 100nA. So we got τ = VOUT × 1ms which is big

enough to memorize VOUT .

59


4.1.3.3 Comparators Circuit

The basic comparator utilized in the proposed circuit is generally known as an

open-loop comparator which is shown in Figure 4.6. There are two important

points of the requirements of the comparator circuit to apply in the proposed

Quick Response Circuit. First, it must have the high gain stage to drive its output

between VOL and VOH for small input voltage changes. Second, it must have the

variable offset voltage of transmission characteristic. In this meaning, the two-

stage operational amplifier without compensation is an excellent implementation

of a high gain, variable offset voltage open-loop comparator.

Figure 4.6: Open-loop comparator circuit.

The performance of this kind of comparator should be similar to the uncom-

pensated two-stage operational amplifier. Since the circuit is used in feed forward,

it is not necessary to operate in high frequency range. Thus, we abbreviated the

discussion on its poles as well as frequency characteristic. The emphasis on the

comparator performances can be expressed as following.

• The minimum output voltage

VOL ≈ VSS (4.4)

60


• The maximum output voltage

VOH ≈ VDD (4.5)

• Small-signal voltage transmission

V CO = (VG9gmMH9 − VG10gmMH10

gdsMH1 + gdsMH10

)

× (gmMH11

gdsMH11 + gdsMH13

) (4.6)

Small-signal voltage transmission reached the above equations because the

aspect ratio (W/L)MH9 and (W/L)MH10 are designed into different size. By

doing this way, the flexible offset voltage of comparator can be obtained just

by adjusting the size of these two transistors. So, the output stage of this new

comparator can be decided by the following condition.

• If VME × gmMH9 < VOUT × gmMH10 then, V CO ≈ V SS

• If VME × gmMH9 > VOUT × gmMH10 then, V CO ≈ V DD

Let’s implement the above mentioned comparator to the comparator block of

the proposed Quick Response Circuit.

As shown in Figure 4.7, two comparators COM1 and COM2 are illustrated.

They work to detect the load current by comparing the two voltages of ∆Vpm (the

differential voltage between memorized output voltage VME and present output

voltage VOUT ) and the comparator input offset voltage Vio1 as well as Vio2 . The

output of comparators COM1 and COM2 can be considered as following.

• If ∆Vpm > Vio1 then, COM1= L to H

• If ∆Vpm > Vio2 then, COM2= H to L

• If ∆Vpm > Vio2 then, COM3= L to H ( COM3=COM2)

Hence, we can obtain three signals for power MOSFET’s charge circuit PD-

CHARGE and discharge circuit PD-DISCHARGE as well as VOUT restrain

circuit VOUT-RESTRAIN that we are going to mention in the next subsection.

61


Figure 4.7: Completed comparator in quick response circuit.

4.1.3.4 PD-DISCHARGE Circuit

The power MOSFET’s discharge circuit PD-DISCHARGE of the proposed

Quick Response Circuit are shown in Figure 4.8.

PD-DICHARGE circuit is formed by transistor MD2, MD7, MD8, MD9

and capacitor CD3 as shown in Figure 4.8(a). At load stable stage COM1=L and

MD9 turns OFF, PD is released and regulator operates normally. Let’s make

the current Id flows through MD9 as a current to discharge the gate capacitor of

power MOSFET. Then, let’s make the current flow through MD7 as Ib4. This

current will determine the discharge time of PD.

MD8 is originally turning ON at stable state since MD7 is turning OFF and

MD8 gate is pulled up to VDD by MD2. When load current changes from light to

heavy, COM1 will turn high (COM1=H) and MD9 turns ON. The current Id will

discharge the gate capacitor of Power MOSFET resulted in the recovery of VOUT

which is undershot by fluctuation of load current. However, Id might too much

turn ON the power MOSFET which let to the ringing oscillation or instability of

VOUT .

To avoid this problem, a discharge time tdi must be limited. As shown in

62


Figure 4.8(a), the discharge time tdi is defined by the time constant CD1 and the

ON resistance Rds−MD7 of MD7. The charge contains in CD1 will discharge to

VSS by Ib4. This will make the gate potential of MD8 go down to VSS and thus,

MD8 eventually turns OFF.

By adjust the charge time tdi and discharge current Id to suit the power

MOSFET’s gate capacitance, then a fast and stable load transient response is

obtained.

Figure 4.8: Completed charge and discharge circuit.

4.1.3.5 PD-CHARGE Circuit

The power MOSFET’s charge circuit PD-CHARGE of the proposed Quick

Response Circuit is shown in Figure 4.8.

PD-CHARGE circuit is formed by transistor MD3, MD4, MD5, MD6 and

capacitor CD2 as shown in Figure 4.8(a). At load stable stage COM2=H and

MD5 turns OFF, PD is released and regulator operates normally. Let’s make

the current Ic flows through MD5 as a current to discharge the gate capacitor of

power MOSFET. Then, let’s make the current flow through MD3 as Ib3. This

current will determine the charge time of PD.

63


MD4 is originally turning ON at stable state since MD3 is turning OFF and

MD4 gate is pulled down to VSS by MD6. When load current changes from

heavy to light, COM2 will turn low (COM2=L) and MD5 turns ON. The current

Ic will charge the gate capacitor of power MOSFET resulted in the recovery of

VOUT which is overshot by fluctuation of load current. However, Ic might be too

much to turn OFF the power MOSFET which lets to the ringing oscillation or

instability of VOUT .

To avoid this problem, a charge time tch must be limited. As shown in Figure

4.8(a) The charge time tch is defined by the time constant CD2 and the ON

resistance Rds−MD3 of MD3 . The charge contains in CD2 will discharge to VDD

by Ib3. This will make the gate potential of MD4 go up to VDD and thus, MD4

eventually turns OFF.

By adjust the charge time tch and charge current Ic to suit the power MOS-

FET’s gate capacitance, then a fast and stable load transient response is obtained.

4.1.3.6 VOUT-RESTRAIN Circuit

The discharge circuit of LDO output voltage VOUT-RESTRAIN of the pro-

posed Quick Response Circuit is shown in Figure 4.8.

VOUT-RESTRAIN circuit is formed by transistor MD10, MD11 as shown

in Figure 4.8(b). It functions as discharge circuit to pull down VOUT when PD-

CHARGE circuit turns OFF the power MOSFET. When load current changes

from heavy to light, COM2 will turn low (COM2=L) and COM3 which is the

inverse signal of COM2 will turn high. MD10 turns ON to discharge the super-

abundant charge of output capacitor COUT and restrain VOUT overshoot.

Transistor MD11 is added in diode connection to avoid the inrush current flow

through MD10 drain before COM3 completely got into operating condition. This

current occurs especially when VDD is starting up. At stable load stage, MD10

turns OFF and Ie current is zero. Thus, the static power is saved.

64


4.1.4 Effectiveness Confirmation by Simulation

4.1.4.1 Reponses at Each Node of Comparator

In this subsection, the simulation results of the proposed circuit before and after

implementing to the conventional LDO are showed. The simulation was done

with the following conditions. The output voltage of LDO is set to VOUT =1.2V

with 1µF capacitor at both input and output nodes. The load current varies from

0.1mA to 75mA with 0.5µs rise and fall time.

Figure 4.9 shows the signal at each node of proposed Quick Response Circuit

when the load current rises from 0.1mA to 75mA. VOUT falls down to a level lower

than memorized voltage (Figure 4.9(d)) .

Thus, the comparator COM1 starts to reacts and output a pulse signal to

PD-DISCHARGE circuit (Figure 4.9(c)). Yet, while VOUT recovers from the

maximum drop level to standard level, the rebound of VOUT will create some

small overshoot.

Figure 4.9: Output signal of comparator at ILOAD=0.1mA-75mA.

65


Figure 4.10: Output signal of comparator at ILOAD=75mA-0.1mA.

At this time, VOUT is bigger than memorized voltage. Hence, the comparator

COM2 reacts and outputs a pulse signal to PD-CHARGE circuit as well as the

VOUT-RESTRAIN circuit (Figure 4.9(b)). So the overshoot by rebounding

is prevented and as a result, we can achieve a minimum drop level of VOUT with

short settling time.

Figure 4.10 shows the signal at each node of proposed Quick Response Circuit

when the load current falls from 75mA to 0.1mA. VOUT goes up to a level higher

than memorized voltage ( Figure 4.10(d)) .

Thus, the comparator COM2 starts to react and to output a pulse signal to

PD-CHARGE as well as to the VOUT-RESTRAIN circuit( Figure 4.10(b)).

While VOUT recovers from the maximum overshoot level to regulated level, there is

no rebound of VOUT . Thus, the comparator COM1 does not react and there is no

output pulse signal to PD-DISCHARGE circuit was created (Figure 4.10(C)).

As a result, we can achieve a minimum overshoot level of VOUT with short settling

time.

66


4.1.4.2 Response at Gate Node of Power MOSFET

Figure 4.11: PD node with and without quick response circuit.

In this subsection, the effect of Quick Response Circuit at PD node by simu-

lation after implementing to the conventional LDO structure is shown.

Let’s take a look at Figure 4.11. The figure shows the signal wave at PD of

power MOSFET gate before and after adapting the proposed Quick Response

Circuit.

The simulation was done with the following conditions. The output voltage of

LDO is set to VOUT =1.8V with 1µF output capacitor at both input and output

nodes. The load current varies from 0.1mA to 75mA with 0.5µs rise and fall time.

From the figure, PD potential changes with high speed compare to the conven-

tional circuit. It is because of the effect of PD-CHARGE and PD-DISCHARGE

circuits.

67

4.2 Bulk-Gate Control Technique for High Power Supply RejectionRatio

4.1.4.3 Response at VOUT

Figure 4.12 are the comparison graphs of the load transient response between the

basic LDO with and without the proposed Quick Response Circuit. From these

graphs, 82mV output drop and 56µs settling time for 0.1mA to 150mA as well as

94mV output overshoot and 45µs settling time for 150mA to 0.1mA load current

are observed for the LDO with proposed Quick Response Circuit.

Figure 4.12: VOUT with and without quick response circuit.

4.2 Bulk-Gate Control Technique for High Power

Supply Rejection Ratio


In this section, a Bulk-Gate Control Circuit for improving power supply rejection

ratio (PSRR) of a Low Dropout Voltage Regulator (LDO) deteriorated due to

lowering of power consumption is proposed. The proposed Bulk-Gate Control

Circuit is applied to the input transistors of the error amplifier to achieve the

68


high PSRR performance. With the proposed circuit, although the operation

current of the error amplifier is dramatically reduced, it is possible to remove the

big ripple noise and improve the PSRR performance of the LDO. Moreover, the

proposed circuit is composed of a few elements which is suitable for LSI design

and implementation.


Figure 4.13: Structure of LDO with bulk-gate control circuit.

The power supply rejection measures the LDO’s ability to suppress the power

supply noise from its output. Assuming that the contribution of the supply noise

due to the bandgap reference is negligible and by using the methodology as shown

in [48], the small signal variations of VOUT due to the supply noise VDD is given

by [49]:

VOUT

VDD

=

1−(

VOA

VDD

)

Aβ+

1

gmprds

× 1

Aβ

(4.7)

69


Where, A is the gain of error amplifier, gmp is the transconductance of the power

MOSFET, rds is the ON resistance of the power MOSFET and VOA is the error

amplifier output voltage.

From Equation (4.7), the only way to improve the PSRR without considering

the gain or the bandwidth of the error amplifier is to make the value of VOA/VDD

to be near to the value of 1. That is, the error amplifier output voltage VOA

needs to be closed to the supply voltage VDD, i.e., having the error amplifier

output voltage VOA tracking the supply voltage VDD at the source terminal of

the power MOSFET. In other words, in this work, we proposed a circuit which

can track the error amplifier output voltage VOA with the variation of the supply

voltage VDD, so that a high PSRR without increasing the power consumption of

the whole circuit can be expected.


Figure 4.13 shows the conventional LDO employing the proposed circuit. The

proposed circuit is composed only of three elements: transistor MK, resistor RK

and capacitor CK. The operation of the proposed circuit is described as follows.

Generally, as shown in Figure 4.14, the channel-length modulation of a MOS-

FET is given by :

ID =1

2µnCox

W

L(VGS − VTH)2(1 + λVDS) (4.8)

From the circuit shown in Figure 4.13, the drain voltage of the transistor MK

can be expressed as follows.

V MKD = RK × 1

2µnCox

W

L(VGS − VTH)2(1 + λVDS) (4.9)

When the transistor MK is designed to operate in saturation region, the vari-

ation of the drain voltage V MKD of the transistor MK with respect to the supply

voltage VDD is simplified as follows.

∆VMK−D = kλ∆VDD (4.10)

70


Figure 4.14: Channel-length modulation of MOSFET.

Where,

k = RK × 1

2µnCox

W

L(VGS − VTH)2 (4.11)

Let’s do the same consideration for the input transistor M4 of the error am-

plifier. And, when the supply voltage VDD varies, e.g., from low to high, with

Equation (4.9), the bulk-gate voltage of transistor M4 will increase. This results

in decreasing the threshold voltage of the transistor M4 due to the body effect of

the MOSFET. Generally, the error amplifier works to balance the reference volt-

age VREF and the feedback voltage VFB of the feedback network. For a constant

reference voltage VREF , when the threshold voltage of the transistor M4 becomes

lower, the current that flows through transistors M4 and M1 will increase. Since

the transistor M2 is connected in current mirror to the transistor M1, the current

flowing through transistors M2 and M3 will also increase. This results in increas-

ing the error amplifier output voltage VOA. Hence, an error amplifier which can

generate its output voltage VOA to track the supply voltage VDD is achieved. In

the same manner, when the supply voltage VDD goes from a high voltage to a

71


low voltage, the error amplifier output voltage VOA will decrease according to the

VDD.

To cope with the channel-length modulation characteristic of the MOSFET,

the channel size (W/L) of the transistor M4 is adjusted in order to obtain the

variation voltage ∆VMK−D which matches with the requirement of the variation

of the error amplifier output voltage VOA.

However, this effect can only demonstrate its performance in DC and a low

frequency region. In order to achieve a high PSRR in a moderate frequency

region, the capacitor CK in parallel to the transistor MK is added. Therefore,

the variation voltage ∆VMK−D in moderate frequency region can be expressed as

follows.

∆VMK−D ≈ ∆VDD(RK +

1

jωCK

)RK (4.12)

With the capacitor CK, the improvement of the PSRR in the frequency range

from several Hz to about 10KHz can be achieved.

As shown in Figure 4.13, the bulk voltage of the differential input transistor

M3 has not been driven by the drain voltage VMK−D of the transistor MK. If the

bulk voltage of the differential input transistor M3 is driven by the drain voltage

VMK−D of the transistor MK, the threshold voltage of the transistor M3 would go

down when the supply voltage VDD moves from a low voltage to a high voltage.

At the same VREF value, the drain current of the transistor M3 would increase,

and the error amplifier output voltage VOA would move down which is against our

requirement to have the error amplifier output voltage VOA tracking the supply

voltage VDD. Lowering down of the error amplifier output voltage VOA will result

in increasing of the output voltage VOUT and will also worsen the line regulation

of the LDO.


4.2.4.1 High PSRR by Effectiveness of Proposed Circuit

The simulation of LDO to confirmed the effectiveness of the proposed circuit is

done with the following conditions. The feedback resistances are set to R1=R2=1.5MΩ,

72


the reference voltage VREF =0.6V, and the output voltage VOUT =1.2V. The supply

voltage VDD is set to VOUT +1V with the ripple voltage Vrip=200mV.

Figure 4.15: Effectiveness of bulk-gate control circuit to PSRR.

The load current is assumed as ILOAD=50mA and the input-output capacitors

are CIN=COUT =1µF (ESR =0Ω). The improvement of the line regulation gave

the high PSRR at a low frequency region. Figure 4.15 shows the improvement

of PSRR characteristic at which curves (1) and (2) represent the characteristic

of PSRR when the bias current of the error amplifier is set to 1/10 of the con-

ventional one. The deterioration of the PSRR of about 10dB at 1KHz frequency

was confirmed. However, the PSRR of the LDO after adapted with the proposed

circuit was much more improved as can be seen in the curve (3) of the same fig-

ure. At DC and a low frequency(10Hz), the PSRR was 40dB improved. From the

same curve, the PSRR at a moderate frequency (1KHz) was also 20dB improved

even thought the bias current was kept to 1/10 of the conventional one.

73


4.2.4.2 Stability of LDO

Figure 4.16: Frequency characteristic of proposed LDO.

In addition, we have confirmed the deterioration of the bandwidth of the error

amplifier by lowering its bias current. The simulation result is shown in curves (1)

and (3) of Figure 4.16. However, the immutability of the frequency characteristic

after adoption of the proposed circuit is shown in curves (2) and (4) of the same

figure. As a result, the proposed circuit achieves an improvement in the PSRR

characteristic without degrading the stability of the LDO.

74

4.3 Auto Inrush Current Limiting Technique for High Speed Start-Up

4.3 Auto Inrush Current Limiting Technique for

High Speed Start-Up


In this section, an Auto Inrush Current Limiting Circuit, to improve the soft start

time of fully low dropout regulator (LDO) used in the applications such as power

management IC system, is proposed. The proposed Auto Inrush Current Limiting

Circuit works to control directly the gate of power MOSFET not to over turn ON

abruptly, but varies the start-up speed according to the output capacitor. The

proposed circuit contains mainly three simple one-stage amplifiers. Without using

the external soft-start capacitor, the proposed Auto Inrush Current Limiting

Circuit contributes many advantages to small portable application design such as

space and product cost.


To keep LDO performing in better way such as load transient response or power

supply rejection ratio (PSRR), the error amplifier must have a wide bandwidth

[11]. This also means the driving ability to drive power MOSFET becomes

stronger and easily to pull down the power MOSFET’s gate PD to ground during

the start-up. As a result, the large inrush current occurs.

To solve this problem, we proposed an Auto Inrush Current Limiting Circuit

which is used to control PD not to over turn ON abruptly. Figure 4.17 shows

the concept of the proposed circuit. The proposed circuit contains mainly three

simple one-stage amplifiers AMP1, AMP2, AMP3 which will be described in next

section.

The operation of the proposed circuit is as following. When LDO is starting

up, the Inrush Current Limiting Disable Circuit (ICLDC) monitors VFB and

VREF . During the start-up, VREF is smaller than VFB. Hence, ICLDC still turns

ON the MSW unless VFB reaches the reference voltage VREF . This duration

lets the Auto Inrush Current Limiting Circuit works to control PD not to drop

abruptly by turning ON the MA12. The gate of MA12 is controlled by output of

75


Figure 4.17: Concept of proposed auto inrush current limiting circuit.

second amplifier AMP2 which amplifies the differential voltage between the two

input-voltage of first amplifier AMP1. This differential voltage is created by PD

potential memorized by first amplifier’s slew rate characteristic and PD itself. So,

the bigger PD drops, the more MA12 turns ON and PD is lift up. This balance

will determine the inrush current of the LDO.

After started up, the ICLDC will turn OFF the MSW and cut OFF the MA12

drain from PD after VFB (or VOUT ) reached the stable value. Hence, the Auto

Inrush Current Limiting Circuit is disable. By disabling the Auto Inrush Current

Limiting Circuit, the effects to LDO regulation by this circuit after started up

are completely avoided.


4.3.3.1 Auto Inrush Current Limiting Circuit

As shown in Figure 4.18, the proposed Auto Inrush Current Limiting Circuit is

formed by two simple one-stage amplifiers and two PMOSFETs.

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The first amplifier AMP1 (MA1∼MA5) works to detect the abruptly change

of the power MOSFET’s gate signal. By using its slew rate time τ characteristic

of MOS amplifier in [50], we will be able to get the differential voltage between

PD and MA2D when PD abruptly changes.

τ =dVMA2D

dt=

IMA5D

CMA9G

(4.13)

Where, VMA2D, IMA5D

, CMA9Gare the drain voltage of MA2 and the drain current

of MA5 and the gate capacitance of MA9, respectively.

Figure 4.18: Auto inrush current limiting circuit.

This differential voltage is amplified by the second amplifier AMP2

(MA6∼MA10) before it is connected to the PD pull-up transistor MA12. The

AMP2 has the offset voltage α at the input stage to make the system operate

stably. This means the differential voltage from AMP1 has to exceed a limit

value α before AMP2 reacts to turn ON the MA12. This limit value α will define

the maximum inrush current of the LDO. α can be realized easily by making the

input transistor pair MA8 and MA9 into different size. In this work, the sizes of

the two transistors are designed to (W/L)MA8<(W/L)MA9.

77


4.3.3.2 Inrush Current Limiting Disable Circuit

The method of the proposed circuit is applying a slew rate circuit to make the

fluctuations of the gate voltage of the power MOSFET slower. However, this

also makes the response time of LDO such as load transient response get worse.

To avoid these problems, we provide an Inrush Current Limiting Disable Circuit

(ICLDC) to disable the Auto Inrush Current Limiting Circuit after the inrush

current disappears.

Figure 4.19: Inrush current limiting disable circuit.

The ICLDC circuit is shown in Figure 4.19. The simple one-stage ampli-

fier(ML1 ∼ ML5) which has the offset voltage β, works as an open-loop com-

parator to compare VREF and VFB. β can be achieved by designing the ML3 and

ML4 into different size. This offset voltage is needed for avoiding the interference

to LDO’s main error amplifier.

This comparator will turn high when feedback voltage VFB reaches VREF -β,

i.e., VOUT almost completely started up. After it turned high, MSW turns OFF.

So, MA12 is cut OFF from PD making the Auto Inrush Current Limiting Circuit

becomes unavailable.

By applying this circuit, the faster VOUT starts up, the faster comparator

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inverses and the inrush limiting circuit become disable. This will enable LDO

operates promptly soon after it started up.

4.3.4 Circuit Operation

Let’s summary the operation of the proposed circuit as following. When the LDO

is starting up, ICLDC turns ON the MSW and both amplifier AMP1, AMP2 are

in operating mode. Due to VFB is at low state, the error amplifier try to pull

down PD abruptly to ground. At the same time, because of the slew rate of

AMP1, the differential voltage between PD and VMA2−D will occur. The amount

of this voltage is depended on the drop level and speed of PD. The faster and

bigger PD drops, the bigger differential voltage occurs. This differential voltage

will be amplified by the AMP2 and drive the gate of MA12. MA12 will turn ON

and pull up PD toward VDD which is contrary to error amplifier. The two forces

cancel each other and as a result PD goes down smoothly to raise up VOUT .

We found that the time to settle PD is not fixed and varied according to PD

itself. For small output capacitor, the drop level and drop time of PD are small,

so the time to settle PD also short. This means, that we can achieve a high speed

start-up time but with small inrush current.


4.3.5.1 Simulation Results of Inrush Current

This section shows the simulation results of the effect of the proposed circuit af-

ter it is adopted to the conventional LDO. The simulations have been done with

the following conditions. The output voltage VOUT of LDO is set to VOUT =1.2V

with the reference voltage VREF =0.6V. The input capacitor is CIN=1µF while

we change the output capacitor for various values from COUT =1µF to 10µF

(RESR=0Ω). The load current was chosen as the smallest and biggest for the

general LDO, i.e., ILOAD=0.1mA and ILOAD=200mA which are the critical con-

ditions for LDO’s start-up moment. Also, the power supply voltage VDD was

set to a normal operation voltage VDD=VOUT +1V and the maximum voltage

VOUT =5.5V. The bias current of main error amplifier was set to 50µA.

79


Figure 4.20: VOUT and IINRUSH at ILOAD=0.1mA and VDD=VOUT +1V.

Figure 4.21: VOUT and IINRUSH at ILOAD=200mA and VDD=VOUT +1V.

80


Figure 4.22: VOUT and IINRUSH at ILOAD=0.1mA and VDD=5.5V.

Figure 4.23: VOUT and IINRUSH at ILOAD=200mA and VDD=5.5V.

81


Figure 4.20 and 4.21 shows the inrush current I INRUSH of LDO simulated

at supply voltages VDD=VOUT +1V and load current ILOAD=0.1mA and 200mA,

respectively.

Figure 4.22 and 4.23 show the inrush current IINRUSH of LDO simulated

at supply voltages VDD=VOUT +1V and load current ILOAD=0.1mA and 200mA,

respectively.

4.3.5.2 Comparison to Conventional Circuit

Comparing to the conventional LDO which has no Auto Inrush Current Limiting

Circuit adopted, we get the comparison results shown in Table 4.1 and 4.2.

Table 4.1: Inrush current and start-up time at VDD=2.2V of LDO with and

without the proposed circuit.

ILOAD COUT No Adopted No Adopted Adopted Adopted

Iinr (mA) Time(µs) Iinr(mA) Time(µs)

1µF 74.6 313 66.7 34.7

0.1mA 4.7µF 274.1 313 106.3 80.5

10µF 549.6 313 144.1 127.7

1µF 56.27 313 34.3 190

200mA 4.7µF 262.5 313 51.8 202

10µF 490.4 313 60.3 231

Let’s make the start-up times of the conventional circuit as the start-up time

of the reference voltage.

If we take the maximum start-up time of proposed circuit as the reference

value to make the comparison, then from Figure 4.23, the maximum start-up

time for conventional circuit is 313µs.

Table 4.1 shows the inrush currents and start-up times at VDD=2.2V and

Table 4.2 shows the maximum supply voltage VDD=5.5V of LDO before and after

adopting the proposed circuit. To make it easier to understand the effectiveness

of the proposed Auto Inrush Current Limiting Circuit, the data of table are

82

4.4 Compensated Technique for High Performance Load Regulation

Table 4.2: Inrush current and start-up time at VDD = 5.5V of LDO with and

without the proposed circuit.

ILOAD COUT No Adopted No Adopted Adopted Adopted

Iinr(mA) Time(µs) Iinr(mA) Time(µs)

1µF 65.65 313 33.1 82

0.1mA 4.7µF 267.1 313 82.9 150

10µF 549.9 313 135.2 206

1µF 49.6 313 7.3 262

200mA 4.7µF 245.2 313 29.6 286

10µF 507.4 313 63.3 313

illustrated in to Figure 4.24 and Figure 4.25. Figure 4.24 is for inrush current

characteristic while Figure 4.25 is for start-up time characteristic.

From the figure, we found that the proposed circuit has better performances

both the start-up time and the inrush current comparing to the conventional

circuit. The DC power consumption of the proposed inrush limiting circuit is

totally 4µA of which 0.5µA is for the Inrush Current Disable Circuit AMP3,

0.5µA is for the first amplifier AMP1 and 2.5µA is for the second amplifier AMP2.

4.4 Compensated Technique for High Performance

Load Regulation


In this section, a Compensated Circuit considered the resistance of bonding wire

for improving the load regulation of low dropout regulator (LDO) is presented.

The circuit is designed with conventional 0.18µm CMOS process that provides

a high performance of load regulation for LDO despite of high load current and

high bonding wire resistance. The proposed Compensated Circuit can improve

the performance of the load regulation of one-stage error amplifier LDO without

increasing any pins for detecting the output voltage. The proposed circuit is

83


Figure 4.24: Inrush current of LDO with and without the proposed circuit.

Figure 4.25: Start-up time of LDO with and without the proposed circuit.

less dependent on the LDO’s input or output voltage as well as a variation of

temperature and threshold voltages of transistors. This characteristic plays an

important role for the design of LDO at low output voltage with high load current.

84



Let us define the symbols used in this section. Vip and Vop stand for the input

and output voltage at the IC pad of the LDO. VDD and VOUT stand for the input

and output voltage at the package pin of the LDO. VREF and ILOAD are the

reference voltage and the load current respectively. RWI and Rh are the boding

wire resistance and the compensated resistance respectively. Generally, the load

regulation of the LDO means that at the output pin of the LDO package, and is

represented by ∆VOUT

∆ILOADwhich can be expressed as follows.

∆VOUT

∆ILOAD

=∆Vop −RWI ×∆ILOAD

∆ILOAD

(4.14)

Where, ∆VOUT and ∆Vop are the fluctuation of VOUT and Vop respectively, when

the load current ∆ILOAD changes. Therefore, ∆Vop and RWI are the main factors

to determine the load regulation characteristics. The output voltage Vop of LDO

at the IC pad is defined as follows.

Vop =R1 + R2

R2VREF (4.15)

From Equation (4.14), it seems that Vop has no relation with ILOAD. However,

the output voltage Vop decreases according to the increasing of the load current

ILOAD. This is due to the operating current of the NMOS transistor at the input

stage of the differential amplifier becomes unbalance. Then, the offset occurred

at the gate-source of the two transistors. By enlarging the gate size of power

MOSFET, it is possible to prevent the decrease of the output voltage Vop when

the load current ILOAD increases. That is, by doing this, the output ability of the

power MOSFET is increased.

In this work, we do not discuss about the possibility of the proposed circuit

to compensate such this problem. We design the size of power MOSFET large

enough, so that, basically almost no fluctuation of Vop will occur when the load

current changes. For example, in case of 0.18µm CMOS process, at the smallest

channel length and 30,000µm channel width, the fluctuation of output voltage

∆Vop is not bigger than 3mV when the load current ILOAD changes from 0mA to

85


Figure 4.26: Proposed concept of compensated circuit.

300mA. Suppose that ∆Vop=0, then only the bonding wire resistance RWI will

deteriorate the load regulation characteristic.

At this time, from Equation (4.14), the load regulation of the LDO becomes

as follows.

∆VOUT

∆ILOAD

=−RWI ×∆ILOAD

∆ILOAD

(4.16)

From Equation (4.16), in order to improve the load regulation of the LDO, we

proposed a Compensated Circuit as show in Figure 4.26 that creates a positive

∆Vop which is proportional to ILOAD, so that, a zero load regulation can be

realizable.


Figure 4.27 shows the structure of the proposed Compensated Circuit. As shown

in Figure 4.27, by monitoring the gate voltage of the power MOSFET, the volume

of the load current is detected. The drop voltage of VOUT due to the resistance

of bonding wire is compensated. The compensation is done by reducing the R2

86


Figure 4.27: Proposed circuit structure.

resistance. The compensated amount is calculated by predicting the drop voltage

of VOUT when the load current changes.

4.4.4 Circuit Operation

If the voltage rising by the compensation of R2 is designated as Va, the load

regulation after compensating becomes as follows.

∆VOUT

∆ILOAD

=Va −RWI ×∆ILOAD

∆ILOAD

(4.17)

In other words, we can actualize the 0mV load regulation, just by adding

Va = RWI ×∆ILOAD to Vop.

From Equation (4.17) and for reaching the above demand, the variable Rh

according to load current is added in parallel to R2 as shown in Figure 4.26.

Rh works in the way to increase Vop when ILOAD changes. Then, the new

output voltage at the IC pad Vop becomes as follows.

87


Vop =R1 +

R2Rh

R2 + RhR2Rh

R2 + Rh

VREF

=R1

RhVREF +

R1 + R2

R1VREF (4.18)

Then, Va is expressed as follows.

Va =R1

RhVREF (4.19)

By adjusting Rh to obtain Va = RWI×∆ILOAD , we can easily obtain the 0mV

load regulation. From Equation (4.19), we found that Va does not depend on R2.

Generally, VOUT is decided by trimming R2 after R1 was determined. This means

that when R1 is determined, the compensated voltage Va theoretically does not

depend on neither VDD nor VOUT . Then Rh becomes as follows.

Rh =R1

RWI ×∆ILOAD

VREF (4.20)

Rh can be realized using M8 and M10 transistors as shown in Figure 4.27.

M11 transistor monitors the gate voltage of power MOSFET transistor M12, for

detecting the volume of the load current. The copied current is inputted to the

drain terminal of M7 and M9 transistor, and this current is transfer to M8 and

M10 transistors which are formed in current mirror connection. From Figure

4.27, the drain currents of M8 and M10 transistors are proportional to that of

M11 transistor or ILOAD, and is expressed as follows.

IdM8−M10 =∆ILOAD

k1k2(4.21)

Where, k1 = (W/L)M12

(W/L)M11and k2 = (W/L)M7−M9

(W/L)M8−M10.

Then, Rh becomes as follows.

Rh =VFB

IdM8−M10

=VFB × k1k2

∆ILOAD

(4.22)

88


Since the error amplifier works to make VFB = VREF , then Rh becomes as follows.

Rh =VREF

IdM8−M10

=VREF × k1k2

∆ILOAD

(4.23)

From Equations (4.20) and (4.23), the 0mV load regulation can be realized

by setting k1 and k2 as follows.

k1k2 =R1

RWI

(4.24)


Figure 4.28: Load characteristics at VOUT =0.9V.

The simulations have been done with the following conditions. The reference

voltage VREF is set to 0.6V. The bonding wire resistance RWI is 92mΩ and R1

is 1.5MΩ. The output voltage VOUT is changed by R2 from 0.9V to 3.0V.

89


Figure 4.28 shows the load characteristic of the LDO when VOUT =0.9V. As

a result, the drop of output voltage due to the bonding wire resistance is much

improved.

Without the Compensated Circuit, the output voltage VOUT badly falls es-

pecially when the load current becomes large. However, when the Compensated

Circuit is adapted, the VOUT is considerably near to the ideal one.

To verify the effect of the proposed circuit, we adapted it to other output

voltages as shown in Figure 4.29. At any VOUT from 0.9V to 3.0V, the fluctuation

of VOUT is less than 1%, while the load current changed from 0mA to 300mA.

This value is good enough for designing of LDO having a high accuracy of VOUT .

Figure 4.29: Load regulation characteristics.

In addition, in order to verify the stability of the regulator, the phase margin is

evaluated with VOUT =0.9V, VDD=VOUT +1V, and the input and output capacitor

CIN=COUT =1µF.

As shown in Figure 4.30, at all load current territories, the phase margin

characteristics are not smaller than -180 degree. This shows that the LDO is

90


operating stably after adopted the proposed Compensated Circuit.

Figure 4.30: Phase margin characteristics.

4.4.6 VTH Variation and Temperature Dependency

Suppose that RWI and R1 have almost the same temperature coefficient. From

Equation (4.20), with the division of R1 and RWI , the temperature coefficients

of both of them are neglected. For realizing the 0mV load regulation, it needs to

make Rh independent to temperature. From Equation (4.23), we found that Rh

is only the function of VREF . Normally, the reference voltage VREF of the LDO

is designed to have a zero temperature coefficient. Totally, Rh is temperature

independent as well as threshold voltage VTH of transistors.

M7 and M9 transistors as well as M10 and M11 transistors are built in cascade

structure, then the fluctuation of IdM8−M10 when there is a variation of VREF is

expressed as follows.

91


Figure 4.31: Temperature dependency.

∆IdM8−M10 =∆VREF

(gm8 × ro8)ro10

(4.25)

Where, gm8 is transconduction of M8 transistor and ro8, ro10 are drain resistances

of M8 and M10 transistor, respectively. Therefore, the effect of VREF fluctuation

to IdM8−M10 can be minimized.

Figure 4.31 shows simulation results of the temperature dependency of the

load regulation. Figure 4.32 shows simulation results of the effect of the VTH

variation to the load regulation after adapting the proposed Compensated Circuit.

Both of simulations have been done with VOUT =0.9V and VDD=VOUT +1V. As a

result, the proposed Compensated Circuit does not influence by variations of

temperature as well as variations of threshold voltage VTH .

92

4.5 Over Current Protection Design

Figure 4.32: Threshold voltage dependency.


In this section, a low power current protection circuit implemented in LDO is

presented. The proposed circuit, designed in 0.35µm CMOS process, provides a

precise limiting current as well as holding current with low dependency on both

supply voltage and regulator output voltage.


A low power and high accuracy Over Current Protection Circuit for LDO designed

with 0.35µm CMOS process is presented. The proposed circuit is composed of

very simple basic analog and digital circuits. Adding to its wide range of VDD and

VOUT , the proposed circuit does a precise current limiting and stable operation.

It can be implemented with the small chip size and consumes very low power

consumption. The proposed circuit has no effect on LDO regulation when the

over current has not taken place. It starts up and works to reduce output voltage

and load current to a stable holding current when load current has exceeded a

93


maximum rated value in the way with which LDO can be protected from latch-up

effect. After it starts up, it cuts OFF the negative feedback loop of the regulator,

so that LDO is prevented from damage.


To solve the conventional problems, we proposed a protection circuit which can

avoid latch-up effect and improve VOUT shut down characteristic without sacri-

ficing the foldback characteristic. The problems have been solved by proposing

a protection circuit which can digitally shut down VOUT from point X to Y as

shown in Figure 4.33.

Figure 4.33: Proposed solution to avoid latch-up effect.

The concept of our proposed Over Current Protection Circuit for LDO to

realize this kind of characteristic is shown Figure 4.34. It is built up with two

blocks of main sub-circuits. They are “Current Sampling Circuit” which includes

sampling circuit, open-loop comparator with variable input offset, Schmitt Trig-

ger inverter and “Current Control Circuit” known as PTG control circuit. The

concept of the proposed circuit is as follows.

1. At low load current, VOUT is normally regulated by error amplifier at a set

output level. In this state, if VOUT turns ON, the transistor MS3 and the

94


current sampling circuit are in active mode. Yet, V TO is at L state. So,

the PTG control circuit stays in standby mode to let the LDO operate

normally.

2. When load current increases, PD goes down increasing the current flow

through MS1 and MS2. This makes the voltage at node a and b go up.

Since RS1 and RS2 are designed to be of different values (RS1<RS2), we

get different voltages between node a and b and it is supposed to be α.

Let’s suppose the input offset voltage of open-loop comparator as β. So,

when the load current exceeds the limit current, α will become bigger than

β and as a result V TO turns to H. This makes PTG control circuit starts

to operate to lift up PD node and VOUT is reduced.

3. After overload current occurs, PTG control circuit keeps PD at a value

that determines the holding current of LDO after VOUT is shut down. This

current also indicates the VOUT recovery point when the over load current

is released.

Figure 4.34: Concept of proposed over current protection circuit.

95



Figure 4.35 shows the proposed Over Current Protection Circuit. It is mainly

divided into four parts as we have mentioned above. They are the current sam-

pling circuit, the open-loop comparator, the Schmitt Trigger inverter, and the

PD control circuit. The operation of each circuit is as follows.

Figure 4.35: Proposed over current protection circuit.

4.5.3.1 Current Sampling Circuit

As shown in Figure 4.35, the current sampling circuit used in the proposed circuit

is formed by MS1, MS2, MS3 and RS1, RS2. The two PMOS transistors MS1

and MS2 copy the load current from power transistor and transform to voltage

by resistors RS1 and RS2. Suppose the NMOS transistor MS3 is working as a

switch. It is designed to be quite large so that the drain-source voltage of this

transistor is small enough to be ignored. Then, when VOUT is at high state, the

voltage at node a and b can be expressed by the following relations.

V a = IL× (W/L)MS1

(W/L)PWT

×RS1 (4.26)

V b ≈ IL× (W/L)MS2

(W/L)PWT

×RS2 (4.27)

96


If we consider α = V b−V a then this value will determine the limit current IL

of LDO. So, by designing (W/L)MS1 = (W/L)MS2 then we got the relationship

between IL and α as follows.

α ≈ IL× (W/L)MS1

(W/L)PWT

× (RS2−RS1) (4.28)

Therefore, the limit current can be adjusted by changing the value of resistance

RS1 and RS2. Here, the value of RS1 and RS2 are set to 200kΩ and 350kΩ

which provides the maximum voltages at node V a and V b of about 72mV and

127mV, respectively. Thus, MS1 and MS2 are still operating in saturation region

when over current takes place. As a result, the drain current of both transistors

are less dependent on the variation of RS1 and RS2.

4.5.3.2 Open-loop Comparator

As shown in Figure 4.35, the open-loop comparator used in the proposed circuit

is formed by MH1, MH2, MH3, MH4, MH5, MH6 and MH7. The requirements

of comparator applied here are a high gain to drive its output between H and

L and variable input offset voltage. Hence, the two-stage operational amplifier

without compensation is an excellent option for implementation.

Hereunder is the emphasis on comparator performances [64].

• The minimum output voltage

V CO ' VSS (4.29)

• The maximum output voltage

V CO ' VDD (4.30)

• Small-signal voltage transmission

V CO = (VbgmMH2 − VagmMH3

gdsMH3 + gdsMH5

)

× (gmMH7

gdsMH6 + gdsMH7

) (4.31)

97


If (W/L)MH2 and (W/L)MH3 are two different values, then the small-signal

voltage transmission equation as shown above can be obtained. By just adjusting

the size of these two transistors, the offset voltage of comparator can be adjusted;

that is, we can obtain flexible offset voltage of the comparator. Hence, the output

of this new comparator can be decided from the following conditions.

• If VbgmMH2 < VagmMH3 then, V CO ' VDD

• If VbgmMH2 > VagmMH3 then, V CO ' VSS

Let’s make the input offset voltage of this comparator as β. β will become the

differential voltage between Va and Vb at inverting terminal of the comparator.

So, β can be expressed by the following.

β = Vb − Va (4.32)

4.5.3.3 Schmitt Trigger Circuit

As shown in Figure 4.35, the Schmitt Trigger circuit applied in the proposed

circuit is composed of MT1, MT2, MT3, MT4, MT5 and MT6. The hysteresis

characteristic of Schmitt Trigger implies that the Schmitt Trigger has some mem-

ory [64] with the upper switching point V TO+ and lower switching point V TO−are found as follows.

V TO+ =V THMT6 +

√β3/β1VDD

1 +√

β3/β1(4.33)

V TO− =

√β5/β6(VDD − V THMT1)

1 +√

β5/β6(4.34)

Where, β1, β3, β5, β6 are the aspect ratios of MT1, MT3, MT5, MT6 respec-

tively.

The Schmitt Trigger circuit used here plays an important role, not only to

operate as an inverter but also to provide the hysteresis to the comparator to

avoid the malfunction of the circuit before and after load current goes across

98


the limit current. At the moment of load current going across the limit current,

PTG control circuit will operate and PD is lift up. If there would be no hysteresis

characteristics of waiting until VOUT goes completely to L state, the comparator

would consider the load current returning to light load while VOUT is dropping.

After VOUT goes down completely, MS3 will turn OFF and node b is lifted up to

VDD. This makes comparator not to reverse back unless the overload current is

released.

Generally, the kind of Schmitt Trigger circuit used in the proposed Over Cur-

rent Protection Circuit does not consume the static current. However, a pene-

tration current may flow from V DD through the Schmitt Trigger circuit to the

ground during a transitional state. As penetration current is large, it would in-

crease the power consumption of the whole circuit. According to the simulation

results, about 49µA (at V DD=2.2V) of the penetration current flows during the

transitional state. It is overwhelmingly bigger than the consumption current of

the whole circuit. Fortunately, this penetration current occurs just only when the

load current exceeds a limitation of several hundreds mA. Hence, this penetration

current becomes a negligible quantity for most applications.

4.5.3.4 Holding Current Limiting Circuit

As shown in Figure 4.35, the holding current limiting circuit in the proposed

circuit is formed by MF1, MF2, MF3, MF4, MF5 and MF6. Suppose that the

over current has taken place. At this time V TO becomes H and MF4 is fully

ON. MF4 is designed to be quite large, so that this transistor can be considered

as a switch. When MF4 is ON, the current IDMF5 starts to flow through MF5.

Supposed that PD is still going down after the load current goes across the limit

current. Then, IDMF5 increases and the gate voltage of MF6 increases. This

makes the inverter MF6, MF1 invert from H to L. So MF2 starts to turn ON

and rises PD up. The falling of PD by load current and the raising of PD by

MF2 set PD to a stable voltage. This voltage determines the current flowing

through power MOSFET (PWT). This current is known as holding current for

the LDO. Adjusting the bias current of transistor MF1 can change the holding

current value since this current determines the gate voltage of MF2.

99


4.5.3.5 Operation of Completed Circuit

Combination of the circuits that we mentioned in previous subsections make our

proposed Over Current Protection Circuit. Let’s summary the operation of the

circuit as follows.

• At low load current, α<β, V TO is L. Regulator works to regulate VOUT to

a setting output voltage as normal.

• When load current reaches the limit current, α>β, V TO is H and PTG

control circuit starts working to lift up PD. This limit current can be ad-

justed by trimming the resistance RS1 either RS2.

• When the load current exceeds the limit current, VOUT will go down to

several milli volts and MS3 turns OFF. Node b is lifted up to VDD that

brings V TO to H state until overload current is released. While V TO is

at H, PD is lifted up permanently by PTG control circuit to a level that

determines the holding current. This holding current can be adjusted by

bias current V B of MF1.


The simulation of the LDO with proposed circuit is done with the lowest VOUT =1.2V

and the highest VOUT =3.6V under the following condition. The reference voltage

is set to V REF=0.7V and feed back resistance R1=1MΩ while R2 is adjusted to

reach a required output voltage. The decoupling capacitor at input and output

node to stabilize the circuit is 1µF for each.

Figure 4.36(a) shows the shut down characteristic of VOUT of proposed LDO

with over current protection at VOUT =1.2V for VDD changing from VOUT +0.5V

to 5.2V. The quiescent current of proposed Over Current Protection Circuit only

is shown in Figure 4.36(b).

Base on these results, the limiting current of the proposed circuit is less de-

pendent on V DD. Moreover, the proposed circuit also has a very stable holding

current at any V DD and V OUT setting. Here, this limiting current is set to

about 300mA while the holding current is around 20mA.

100

4.6 Fabrication Error

Figure 4.36: VOUT shut down characteristic and quiescent current.

The simulations result has shown that the quiescent current of the proposed

circuit itself is 0.82µA for V OUT=1.2V, V DD=2.2V and ILOAD=200mA. The

low consumption power is achieved because most parts of the circuit such as the

Schmitt Trigger circuit and PTG control circuit consume no power before over

current takes place.


Conventionally, process variations and mismatch have been considered to be the

error sources over which a circuit designer has not yet controlled over. Their

harmful effects have therefore been mitigated primarily through careful layout

followed by intensive trimming during the manufacturing process [59]. The vari-

ation and mismatch of the devices can be classified and discussed as following.

101


4.6.1 MOSFET Mismatch

This error arises from a mismatch in MOSFET devices which form in current

mirrors. In turn, it leads to a deviation in the desired ratio of the mirror currents.

Figure 4.37: Process Conner.

The mismatch may occur due to a disparity in the aspect ratio W/L or thresh-

old voltage VTH of the MOSFET pair. Normally, from the distribution of MOS-

FET characteristic in an integration circuit, the process corner can be defined.

Let we take the X axis as the threshold voltage of NMOS and Y axis as that of

PMOS. Let we make the CMOS model at low threshold voltage as FAST and

that at high threshold voltage as SLOW. Figure.4.37 shows the process corner of

the threshold voltage VTH . From the figure, we got five combinations of threshold

voltage variation of NMOS and PMOS as following.

• TT : NMOS=TYPE , PMOS=TYPE

• SS : NMOS=SLOW , PMOS=SLOW

• SF : NMOS=SLOW , PMOS=FAST

• FS : NMOS=FAST , PMOS=SLOW

• FF : NMOS=FAST , PMOS=FAST

102


4.6.2 Resistor Variation

Process variations lead to a large deviation in resistor value which is often known

as large as 20∼30%. This error can be reduced by choosing a material for the

resistor that does not exhibit significant spread in resistivity over process, voltage,

and temperature. Poly silicon resistor, for example, typically exhibits a smaller

variation of resistance with voltage and temperature than n-well resistors. While

resistor variations, which occur as a result of deviations in sheet resistance from

one die to another, cannot be controlled, they have a minimal impact on the

accuracy of the circuit.

4.6.3 Capacitor Variation

In CMOS process, capacitor can be realized in several ways. MIM capacitors

basically a parasitic capacitor between the metal layers (MIM ⇒ Metal Insulator

Metal). Generally CTM mask layer is used for insulation. The accuracy of this

kind of capacitance is high but it takes lot of area. Apart from this, another

capacitor is MOS capacitors which is formed between POLY layer and Nwell

layer(Poly Nwell Cap) gives more capacitance in less area but the bigger variation.

Some processes also support PIP (PIP ⇒ Poly Insulator Poly) capacitor which is

formed between POLY1 and POLY2. Process variations lead to a large deviation

in capacitor values which is often known as large as 5% ∼10% for PIP capacitor.

4.6.4 Offset Variation of Differential Amplifier

Adding to above mentioned variations of MOSFET, resistor and capacitor, the

variation of the offset voltage of the differential amplifier also influence strongly

the characteristic of the proposed circuit, especially the characteristic of load

transient response. The offset variation occurs by the variation of the symmetrical

input transistor of the amplifier. This variation is supposed to be maximum

10mV. Hence, it is necessary to consider this kind of variation when we determine

the specification of the LDO.

With the above mentioned device’s variation, it is impossible to avoid the

errors between the design on computer (simulation) and the real chip fabrication.

103

4.7 Design of High Performance LDO

The next section will show the simulation results of proposed high performance

LDO with the consideration of the above mentioned process variation.


4.7.1 Block Diagram

The proposed techniques to achieve the low dropout regulator (LDO) with fast

load transient response, high PSRR, high performance load regulation and low

quiescent current presented in this chapters 4 are used to assemble the system

illustrated in Figure 4.38.

Figure 4.38: Micrograph of completed proposed LDO.

Beside the conventional LDO structure which contains the Error Amplifier,

power MOSFET and Feedback Network, the proposed Quick Response Circuit

for fastening the load transient response is added to help Error Amplifier charge

and discharge the power MOSFET’s gate capacitor.

Also, the proposed Bulk-Gate Control Circuit is added to control the bulk-

gate of input transistor (feedback side) of the Error Amplifier. Bulk-Gate Control

104


Circuit helps the Error Amplifier to track its output to input voltage VDD in a

manner that the ripple at output VOUT node are canceled.

Not only the above two circuits, the proposed Compensated Circuit for en-

hancing the load regulation is also utilized to make sure that the variation of

output voltage while load current changes is restrained to VOUT±1%. The Com-

pensated Circuit works to adjust the feedback voltage of feedback network in a

way that the drop of VOUT by bonding wire is compensated.

The proposed Auto Inrush Current Limited Circuit in this chapter 4 is also

applicable for the whole LDO system by simulation. However, for fabrication’s

reason, the implementation and experimental result are not available in this work.

The evaluation of this circuit is supposed to be done in next fabrication.

4.7.2 LDO Circuit in Transistor Level

The completed circuit of LDO in transistor level is shown in Figure 4.39. It is

comprised of several parts described in this chapter 4 which can be divided as

following. Firstly, they are the biasing and voltage reference which are defined

by conventional PTAT generator block. Secondly, it is the error amplifier with

DC boosting circuit to boost the bias current of amplifier when load increases.

Thirdly, it is the proposed Quick Response Circuit which is formed by compara-

tors block, memory block and power MOSFET’s gate charge/discharge circuit as

well as VOUT overshoot restraining circuit. Fourthly, it is the proposed Bulk-Gate

Control Circuit which is formed by three elements, namely, RK, CK and MK.

Fifthly, it is the proposed Compensated Circuit which is formed by five elements,

namely, MC7 ∼ MC11. Last of all, it is the LDO basic components count for

power MOSFET, feedback resistor (R1 and R2), etc.

4.7.3 Simulation Results of LDO Circuit

4.7.3.1 Typical DC and AC Characteristics

Figures 4.40 through Figure 4.45 describe the performance achieved by the de-

signed system. They illustrate the circuit realization of the system shown in Fig-

ure 4.39 with the exception of the Auto Inrush Current Limiting Circuit. They

105


Figure 4.39: Completed LDO circuit in transistor level.

106


were simulated in 0.18µm CMOS technology with 6 metals and 2 poly layers.

The plots of the layout are illustrated in appendix B.

The Auto Inrush Current Limiting Circuit was not included in the circuit

because it is the latest research which has been completely done after the layout

data was taped out. However, this limiting circuit is now being fabricated and

will be evaluated in the next fabricated schedule and that is one of our future

work.

Figure 4.40 illustrates the line regulation performance of the control loop,

roughly 0.05%/V (0.5mV/V) for no load current, 0.217%/V (2.17mV/V) for

50mA load current and 0.649%/V (6.49mV/V) for 150mA load current. The

performance was approximately the same with and without the implementation

of the proposed techniques.

The dropout voltage performance is depicted by Figure 4.41. The circuit

achieved a dropout voltage of 0.5mV for no load current, 147mV for 50mA load

current and 359mV for 150mA load current.

The circuit achieved a load regulation performance of roughly 0.009mV/mA

for VDD=2.2V (VDD=VOUT + 1V) and maximum input voltage 2.5V which is

illustrated in Figure 4.42. For 92mΩ bonding wire of SOT-23 package, the drop

will be at lease 13.8mV for 150mA load current. This means, an approximately

60% of load regulation has been improved over its non bonding wire compensated

version.

Figure 4.43 shows the quiescent current flows as a function of load current.

Quiescent current at zero load current was 5.7µA measured at VDD=VOUT +1V

whereas its peak was 26.8µA during maximum load current conditions at the

same VDD. The increase in current is expected because the DC boosting circuit

worked to boost the bias current of error amplifier in order to maintain other

characteristics such as noise, PSRR, etc. The DC boosting circuit is designed to

start operating at a load current of approximately 2mA.

Figure 4.44 illustrates the transient performance of the circuit upon a load cur-

rent step transition. The load current was stepped from 0.1mA to 150mA and vice

versa. The maximum output voltage variation of the circuit was 54.5mV, shown

by the trace of VOUT . The same circuit but without the aid of proposed Quick

107


Response Circuit and DC boosting circuit showed a variation of 558mV. There-

fore, the benefits of the current efficient buffer in the LDO for a given amount

of quiescent current flow can be roughly quantified to yield an improvement of

90.3%. In other words, the output voltage variation is significantly reduced by

utilizing the proposed Quick Response Circuit along with DC Boosting Circuit.

Figure 4.45 shows the PSRR performance of the control loop with proposed

Bulk-Gate Control Circuit adopted. The power supply rejection at 1KHz fre-

quency are roughly 57dB for no load, 76.11dB for 50mA load current.

108


Figure 4.40: Line regulation performance.

Figure 4.41: Dropout voltage performance.

109


Figure 4.42: Load regulation performance.

Figure 4.43: Quiescent current performance.

110


Figure 4.44: Load transient response performance.

Figure 4.45: PSRR performance.

111


Table 4.3 summarizes the performances which were achieved by the proposed

techniques such as the Quick Response Circuit, the Bulk-Gate Control Circuit,

the Bonding Wire Compensated Circuit. The special point of the proposed tech-

niques is that the large quiescent current flows only during high load current

conditions. It helps to expand the battery life during the system changes to

standby mode.

Table 4.3: Electrical performances summary of target LDO by simulation.


Output Voltage Range (VOUT ) 0.9∼ 1.5V

Input Voltage Range (VDD) 0∼ 2.5V


Dropout Voltage

(VOUT = 1.2V, ILOAD = 150mA) 359mV

Quiescent Current (No load) 5.6µA

Quiescent Current (Full load) 26.8µA

Line Regulation

(ILOAD = 50mA) 0.217%/V

Load Regulation

(VDD = VOUT + 1V) 0.009mV/mA

Load Transient Undershoot

(ILOAD = 0.1 ⇐⇒ 150mA, COUT =4.7µF) -54.5mV

Load Transient Overshoot

(ILOAD = 150 ⇐⇒ 0.1mA, COUT =4.7µF) 48.4mV

PSRR@10Hz

(VOUT = 1.2V, ILOAD = 50mA) 92.80dB

PSRR@1KHz


Output Capacitor Range (COUT ) 0.47∼ 4.7µF

112


4.7.3.2 Margin of DC Characteristics

The DC characteristics here are counted for the characteristic of dropout voltage,

the characteristic of quiescent current, the characteristic of line regulation as well

as the characteristic of load regulation.

(1) Variation Parameters for DC Simulation

Since it is a simulation of DC characteristic, the variation of capacitor is not

included to the simulation. Also, the offset voltage of the operational amplifier is

excluded from the variation parameters since it has influence to the characteristic

of load transient response only. Hereunder is the list of the simulations to be

running.

Table 4.4: Simulation list for DC characteristics.

VTH Resistor=R ± 0% Resistor=R - 30% Resistor=R + 30%

TT O O O

SS O O O

SF O O O

FS O O O

FF O O O

(2) DC Margin Decision

The simulation results of DC characteristics for all the variation of VTH and

Resistor ( R ± 30%) are shown in Table 4.5. The simulations were done with

VOUT =1.2V type LDO, load current ILOAD= 0mA ∼ 150mA, VDD= VOUT + 1V

for evaluating the characteristic of Quiescent Current and Load Regulation. For

the simulation of Dropout Voltage, the load current was set to ILOAD= 150mA

and VDD= 0∼ 2.5V.

From Table 4.5, we can define the minimum and maximum value of the men-

tioned DC characteristic after consideration of the process variation as shown in

Table 4.6

113


Table 4.5: Decision of margin of DC characteristics.

Characteristic Res=R ± 0% Res=R - 30% Res=R + 30%

MIN MAX MIN MAX MIN MAX

Dropout Voltage (mV) 291.6 437.5 299.0 477.3 288.5 432.6

Quiescent Current∗ (µA) 5.65 5.73 8.20 8.34 4.34 4.40

Quiescent Current∗∗ (µA) 26.09 27.93 35.45 38.37 18.53 19.87

Line Regulation (%/V) 0.217 0.300 0.263 0.293 0.162 0.199

Load Regulation (mV/mA) 0.009 0.014 0.014 0.016 0.011 0.014

Note: Res = Resistor, ∗ = At no load, ∗∗ = At full load

Table 4.6: Margin decision of DC characteristics.

Characteristic MIN TYPE MAX

Dropout Voltage (mV) 291.6 359.0 447.3

Quiescent Current∗ 4.34 5.65 8.34

Quiescent Current∗∗ 18.53 26.78 38.37

Line Regulation (%/V) 0.162 0.217 0.300

Load Regulation (mV/mA) 0.009 0.009 0.016

Note: Res = Resistor, ∗ = At no load, ∗∗ = At full load

4.7.3.3 Margin of Load Transient Characteristic

The same to DC characteristics, the load transient response characteristic is also

suffered from the variation of manufacturing, especially, the threshold voltage

VTH of MOSFET, resistor, capacitor. Beside these variations, the load transient

response will be also suffered from the offset voltage of comparators.

(1) Variation Parameters for Load Transient Simulation

For the ideal comparator, the layout is critical for minimizing the input-

referred offset voltage that is dominated by a mismatch between the pair of input

114


trans-conductors. As such, the input NMOS transistors are critically matched

through a common-centroid, cross-coupled layout that minimizes relative vari-

ations in the two transistors over process variations in both x and y directions

(and any combination) along the die. Yet, the offset of the comparator still occurs

due to the limitation of present CMOS technology. The offset voltage of input

transistor pair of the general CMOS comparator is well known as 5mV ∼ 10mV.

One of the main components to decide the performance of the proposed Quick

Response Circuit is the comparators. The offset voltage of the comparators are

provided to detect the variation of ILOAD by monitoring VOUT fluctuation. How-

ever, this offset voltage will change according to the process variation. This

change will affect seriously to the load transient response characteristic of the

proposed LDO. Hereunder is the list of the simulations to be running.

Table 4.7: Simulation list for load transient response at 0mV / 10mV offset

variation.


TT O/O O/O O/O

SS O/O O/O O/O

SF O/O O/O O/O

FS O/O O/O O/O

FF O/O O/O O/O

(2) Margin Decision of Load Transient Response

The consideration is done on the errors of VOUT transient voltage drop when

load changes from 0.1mA to 150mA at output capacitor COUT =4.7µF.

Table 4.8 and Table 4.9 show the variation of load transient response of the

LDO when there is 0mV and 10mV variation of offset voltage occurred at the

comparators block of proposed Quick Response Circuit.

From Table 4.8 and Table 4.9, we can totally decide the margin of load tran-

sient response characteristic when there are the process variation both the resistor

and comparators’ offset voltage. Table 4.10 shows the margin (the minimum and

115


Table 4.8: Margin of load transient response by 0mV offset variation.



VOUT undershoot (mV) -35.33 -58.4 -34.75 -51.72 -36.61 -63.62

VOUT overshoot (mV) 42.31 49.53 41.15 46.32 43.67 52.15

Note: Res = Resistor

Table 4.9: Margin of load transient response by 10mV offset variation.



VOUT undershoot (mV) -98.22 -109.9 -102.4 -129.5 -94.75 -103.1

VOUT overshoot (mV) 83.37 104.4 68.90 88.77 80.04 89.58


maximum value) of load transient response characteristics which are summarized

from both Table 4.8 and Table 4.9.

Table 4.10: Decision of margin of load transient response characteristic.


VOUT undershoot (mV) -34.75 -54.50 -129.5

VOUT overshoot (mV) 41.45 48.40 104.4

4.7.3.4 Margin of Power Supply Rejection Ratio

The same to DC characteristics, the PSRR characteristic is also suffered from the

variation of manufacturing, especially, the threshold voltage VTH of MOSFET,

Resistor, Capacitor. Beside these variation, the PSRR will be also suffered from

the channel length modulation of MOSFET.

116


(1) Variation Parameters for PSRR Simulation

Refer to the previous mention about the MOSFET mismatch, the PSRR error

arises from a mismatch of MK to the PMOS transistor in constant current source

circuit formed in current mirrors. It leads to a deviation in the desired ratio of

the mirror currents. Let’s consider the variation of PSRR in Figure 5.19. When

(W/L) of MK varies, the PSRR becomes worse and worse. This is because the

channel modulation of MK and the current flowed into RK are changed. The

change will lead to the un-match in volume to cancel the ripple of power supply

line as discussed in Figure 5.5. Hereunder is the list of the simulations to be

running.

Table 4.11: Simulation list for PSRR by resistor variation.


TT O O O

SS O O O

SF O O O

FS O O O

FF O O O

Table 4.12: Simulation list for PSRR by channel length variation.

VTH L=2µm (W/o Mismatch) L=1.5µm (W/th Mismatch)

TT O O

SS O O

SF O O

FS O O

FF O O

(2) Margin Decision of PSRR

117


Table 4.13: Simulation list for PSRR by capacitor variation.

VTH Cap= C - 10% Cap= C + 10%

TT O O

SS O O

SF O O

FS O O

FF O O

Table 4.14 to 4.16 show the PSRR of proposed LDO measured by the simu-

lation. The evaluated condition is set to VOUT =1.2V, VDD= 2.2V, Vrip= 200mV

and ILOAD=50mA as well as COUT =1µF.

Firstly, Table 4.14 shows the simulation of PSRR when there is the ± 30%

variation of resistor occurred at every resistors of the whole circuit included RK

of the proposed Bulk-Gate Control Circuit. From the table, we can find the

minimum and maximum value of PSRR at each condition.

Table 4.14: Margin of PSRR by resistor variation.



PSRR @ 10Hz (dB) 91.71 94.15 82.19 85.47 77.92 81.58

PSRR @ 1KHz (dB) 76.11 77.93 70.29 72.25 70.37 72.55

Note: Res = Resistor, Measured at COUT=1µF, Vrip=200mV

Secondly, Table 4.15 shows the simulation of PSRR when there is the variation

of channel length occurred at transistor MK of the proposed Bulk-Gate Control

Circuit from L=2µm to L=1.5µm . The simulation was done at the condition that

the resistor has -30% variation. This is because from Table 4.14, this condition

showed the worst PSRR value which is necessary to predict the worst case of

PSRR characteristic.

118


Table 4.15: Margin of PSRR by mismatch of channel length modulation.

Characteristic L=2µm (W/o Mismatch) L=1.5µm (W/th Mismatch)

MIN MAX MIN MAX

PSRR @ 10Hz (dB) 77.92 81.58 69.37 73.44

PSRR @ 1KHz (dB) 70.37 72.55 68.00 71.24

Note: Res = Resistor, Measured at COUT=1µF, Vrip=200mV

Thirdly, the variation of capacitor also has the bad influence to the PSRR

characteristic, especially, for the PSRR at moderated and high frequency. Table

4.16 shows the variation of PSRR when there at the ±10% variation of capaci-

tor occurred at every capacitor of the whole circuit included CK of the proposed

Bulk-Gate Control Circuit. The simulation was done at the condition that the re-

sistor has -%30 variation and the channel length of MK was changed to L=1.5µm.

This is because from Table 4.15 and Table 4.15, these conditions showed the worst

PSRR value which is necessary to predict the worst case of PSRR characteristic.

Table 4.16: Margin of PSRR by capacitor variation.

Characteristic Cap= C - 10% Cap= C + 10%

MIN MAX MIN MAX

PSRR @ 10Hz (dB) 70.21 74.21 69.06 73.08

PSRR @ 1KHz (dB) 70.12 73.99 63.68 66.24

Note: Cap = Capacitor, Measured at COUT=1µF, Vrip=200mV

Totally, from Table 4.14 to Table 4.16, we can decide the margin of PSRR

characteristic when there are the process variation of the transistor and resistor

and capacitor. Table 4.17 shows the margin (the minimum and maximum value)

of PSRR characteristics summarized from Table 4.14 to Table 4.16.

119


Table 4.17: Decision of margin of PSRR characteristic.


PSRR @ 10Hz (dB) 69.06 92.88 94.15

PSRR @ 1KHz (dB) 63.68 76.11 77.93

4.7.3.5 Summary of Electric Performance of LDO

Table 4.18 shows the summary electrical performances of the high performance

LDO with utilizing the proposed techniques. Referring to the margin of each

characteristics defined in previous subsection, the summary of simulation results

of designed LDO with consideration of the process variation is found. The worse

case of each characteristic due to process variation is represented by the value

MIN or MAX of the table. TYPE value shows the characteristics of which no

process variation is considered.

120


Table 4.18: Summary of simulation results of LDO with consideration of process

variation.

Characteristics Simulation

MIN TYPE MAX 　　　Technology CMOS 0.18µm

Output Voltage Range (VOUT )(V) 0.9 - 1.5

Input Voltage Range (VDD)(V) 0 - 2.5

Maximum Output Current (mA) 150

Dropout Voltage (mV)

(VOUT = 1.2V, ILOAD = 150mA) 291 359 447

Quiescent Current (No load)(µA) 4.3 5.6 8.3

Quiescent Current (Full load)(µA) 18.5 26.7 38.3

Line Regulation (ILOAD = 50mA)(%/V) 0.162 0.217 0.293

Load Regulation (VDD = VOUT + 1V) (mV/mA) 0.009 0.009 0.016

Load Transient Undershoot(mV)

(ILOAD = 0.1 ⇐⇒ 150mA, COUT =4.7µF) -34.7 -54.5 -129.5

Load Transient Overshoot(mV)

(ILOAD = 150 ⇐⇒ 0.1mA, COUT =4.7µF) 41.1 48.4 104.4

PSRR @ 10Hz (dB)

(VOUT = 1.2V, ILOAD = 50mA) 69.06 92.80 94.15

PSRR @ 1KHz (dB)

(VOUT = 1.2V, ILOAD = 50mA) 63.68 76.11 77.93

Output Capacitor Range (COUT ) (µF) 0.47 - 4.7

121

4.8 Design of LDO with Over Current Protection Circuit

4.8 Design of LDO with Over Current Protec-

tion Circuit

4.8.1 Block Diagram

The proposed technique to achieve the low dropout regulator (LDO) with high

performance Over Current Protection Circuit which is presented in this chapters

4 is used to assemble the system illustrated in Figure 4.46.

The LDO with the proposed Over Current Protection Circuit here is operable

with low power, low voltage operation and has a high accuracy limiting current

as well as stable holding current.

Figure 4.46: Block diagram of LDO with over current protection circuit.

4.8.2 LDO Circuit in Transistor Level

The completed circuit of LDO with proposed Over Current Protection Circuit in

transistor level is shown in Figure 4.47. It is comprised of the main regulation

circuit of LDO which counts for error amplifier and power MOSFET and the over

current protection parts described in this chapter. The feedback resistors R1 and

122


R2 are external designed in order to achieve several VOUT for the experimentation.

The biasing and voltage reference are also external input.

Figure 4.47: LDO with over current protection circuit in transistor level.

123


Table 4.19: DC Electrical performances summary of LDO with proposed over

current protection circuit.


Output Voltage Range (VOUT ) 1.2 ∼ 3.6V

Input Voltage Range (VDD) 0 ∼ 6V


Dropout Voltage

(VOUT = 1.2V, ILOAD = 150mA) 296.3mV

Quiescent Current

(External Current Source) 6µA

Line Regulation

(ILOAD = 50mA) 0.142%/V

Load Regulation


Limit Current

(VOUT = 1.2V, VDD = 2.2V) 300mA

Limit Current Variation

(±30% of RS1, RS2 Variation) ±23.3%

Holding Current

(VOUT = 1.2V, VDD = 2.2V) 20mA

Holding Current Variation

(±30% of RS1, RS2 Variation) ±0%

Output Capacitor Range (COUT ) 0.47∼4.7µF

4.8.3 Simulation Results of LDO Circuit

4.8.3.1 Typical DC Characteristics

Table 4.19 shows the summary of electrical performances of LDO with proposed

Over Current Protection Circuit. The LDO is operable in the regulator out-

put voltage range from V OUT=1.2V to V OUT=3.6V and supply voltage range

from V DD=V OUT+0.5V to V DD=5.6V. It consumes about 6µA quiescent cur-

rent for the whole circuit. The bias current of the LDO is supplied by exter-

124


nal current source. The line regulation at ILOAD=50mA and load regulation at

ILOAD=0mA to 50mA are 0.142%/V and 0.095mV/A respectively. The drop

voltage at VOUT =1.2V, ILOAD=150mA is 296.3mV.

4.8.3.2 Margin of DC Characteristics

The DC characteristics here are counted for the characteristic of limiting current

and the characteristic of holding current.

(1) Variation Parameters for DC Simulation

Since it is a simulation of DC characteristic, the variation of capacitor is not

included to the simulation. Hereunder is the list of the simulations to be running.

Table 4.20: Simulation list of LDO with over current protection.


TT O O O

SS O O O

SF O O O

FS O O O

FF O O O

(2) DC Margin Decision

The simulation results of DC characteristics for all the variation of VTH and

Resistor ( R ± 30%) are shown in Table 4.21. The simulations were done with

VOUT =1.2V type LDO, load current ILOAD= 0mA ∼ 500mA, VDD= VOUT + 1V

and COUT =1µF.

From Table 4.21, we can define the minimum and maximum value of the

mentioned DC characteristic after consideration of the process variation as shown

in Table 4.22

The bias current of the error amplifier and that of the proposed Over Cur-

rent Protection Circuit are provided by the external current source. Hence the

125


Table 4.21: Decision of margin of LDO with over current protection.



Limiting Current (mA) 293 310 420 449 215 238

Holding Current (mA) 18.4 21.3 18.4 21.3 18.4 21.3


Table 4.22: Margin decision of LDO with over current protection.


Limiting Current (mA) 215 300 449

Holding Current (mA) 18.4 20 21.3


quiescent current of the whole LDO almost has no dependency to the resistor

variation. According to the structure of LDO, the load and line regulation are

also not dependent on the resistor variation.

For ±30% variation of resistor and the same VTH , the limit current changes

for ±23.3%. The holding current changes for ±0% for ±30% variation of resistor.

This is because, the limiting current are defined by the resistance RS1 and RS2

but the holding current has not function to these resistors. The holding current

is defined by the bias voltage VBP which provided by external current source.

126

Chapter 5

IMPLEMENTATION AND

EXPERIMENTAL RESULTS

5.1 Chip Fabrication

5.1.1 Implementation of High Performance LDO

To validate the results of the proposed schemes, the proposed LDO was imple-

mented and fabricated using 0.18µm CMOS process technology. A chip micro-

graph is shown in Figure 5.1(See Appendix B for Layout). The chip comprises

of all three primary modules of the system, namely, the Quick Response Circuit

for fast load transient response, the Bulk-Gate Control circuit for high PSRR

and the bonding wire compensated circuit for high performance load regulation.

The proposed Auto Inrush Current Limiting Circuit as well as Over Current Pro-

tection Circuit are implemented in other chips due to the fabrication schedule.

The die area of the fabricated chip is 634µm × 489µm. It includes that of the

reference circuit as well as feedback network. etc.

127

5.1 Chip Fabrication

Figure 5.1: Micrograph of a completed proposed LDO.

5.1.2 Implementation of Over Current Protection Circuit

Figure 5.2 shows the microphotograph of proposed over current protection circuit

designed and fabricated in 0.35µm CMOS process (See Appendix B for Layout).

The completed chip includes Power MOSFET, LDO control circuit and the pro-

posed over current protection circuit (0.0079mm2). The voltage reference circuit

and feed back network (resistances) of LDO are externally designed to achieve

several testing conditions.

128

5.2 Experimental Results

Figure 5.2: Microphotograph of proposed circuit.


5.2.1 Measurement of High Performance LDO

5.2.1.1 Load Transient Response Characteristic

The measurement was done with the following conditions. The output voltage of

LDO is set to VOUT =1.2V with 1µF input capacitor at input node and 1µF, 4.7µF

output capacitors at output node. The load current as stepped from 0.1mA to

150mA and vice versa with 0.5µs rise and fall time.

Figure 5.3 illustrates the transient performance of the proposed LDO with

Quick Response circuit adopted upon a load-current step transition. The top

tracks of Figure 5.3(a) shows the load transient response for COUT =1µs. From

the figure, the output undershoot and overshoot are only 196mV and 172mV

while the settling time is approximately 60µs and 65µs respectively.

129


Figure 5.3: Load transient response of target LDO.

For 4.7µF output capacitor, as shown in the bottom tracks of Figure 5.3(b),

the output undershoot and overshoot are only 116mV and 104mV while the

settling time is approximately 65µs and 45µs respectively.

For other experimental results of load transient response characteristic of the

above chip measured at various load currents such as ILOAD=0.1mA ⇐⇒ 50mA,

ILOAD=0.1mA ⇐⇒ 100mA and COUT =0.47µF, COUT =1µF are illustrated in ap-

pendix A.

5.2.1.2 PSRR Characteristic

For the experiment of PSRR characteristic, the chip was measured with the three

samples of LDO output voltage, i.e., VOUT = 0.9V, 1.2V and 1.5V. The reference

voltage circuit is fixed to VREF =0.6V and the feedback resistances are adjusted

130


Figure 5.4: PSRR performance of target LDO.

to achieve each of the above output voltages. The supply voltage VDD is set to

VOUT +1V with the AC ripple voltage Vrip= 200mV. The load current is assumed

as ILOAD=1mA, ILOAD=50mA and ILOAD=100mA. The input-output capacitors

are fixed to CIN=COUT =1µF (RESR=0Ω).

Figure 5.4(a), 5.4(b), 5.4(a) illustrated the PSRR characteristic of the pro-

posed LDO with Bulk-Gate Control Circuit at load current ILOAD=1mA, ILOAD=50mA

and ILOAD=100mA, respectively.

From Figure 5.4(a), it shows that for light load condition (ILOAD = 1mA), the

PSRR is worse than in other conditions. This is because the bias current of error

131


Figure 5.5: Effect of bulk-gate control circuit to line regulation.

amplifier was reduced to save the power consumption which resulted in a poor

performances of low loop gain and narrow bandwidth of the amplifier. However,

the light load current condition means the application, to which the LDO supplies

power, is no longer in active mode. Thus, for general portable applications, the

high PSRR is neither expected nor required at this condition. On contrary, the

power consumption of the circuit is given the most priority for expanding the

battery life. The track in Figure 5.4(a), shows the performance of PSRR being

up to 60dB for 10Hz and badly down to 43.5dB for 1KHz ripple frequency.

From Figure 5.4(b), it is found that the PSRR characteristic is better than

in other conditions. This is because of the effectiveness of DC boosting circuit

and proposed Bulk-Gate Control Circuit. When load current becomes bigger

ILOAD>2mA, first DC boosting circuit works to boost the bias current of error

amplifier, which resulted in a better loop gain and a wider bandwidth. At the

same time the proposed Bulk-Gate Control Circuit works to cancel the ripple

at VDD by making use of the channel length modulation and AC connection

of capacitor. Totally, the high PSRR at both low and moderated frequency is

achieved. The track in Figure 5.4(b), shows the performance of PSRR being up

132


to 75dB for 10Hz and remaining high 61.8dB for 1KHz ripple frequency.

From Figure 5.4(c), the PSRR performance at moderate frequency 1KHz is

still maintaining while, at low frequency, getting worse compare to that of 50mA

load current in Figure 5.4(b). This is because, the cancel amount of proposed

Bulk-Gate Control circuit to the variation of VDD becomes un-match like shown

in Figure 5.5. However, the proposed circuit still helps maintaining the PSRR at

moderate frequency 1KHz at 64.2dB even though at 10Hz, the PSRR is restrained

to 58dB.

For other PSRR experimental results of the above chip measured at various

output voltage VOUT such as 1.2V type and 1.5V type are shown in appendix A.

5.2.1.3 Load Regulation Characteristic

Figure 5.6: Load regulation performance of target LDO.

The experimental results shows the LDO with adopted proposed bonding wire

compensated circuit achieved a load regulation performance of roughly 0.036mV/mA

for VDD=2.2V (VDD=VOUT + 1V) and maximum input voltage 2.5V which is il-

lustrated in Figure 5.6.

133


In case of 92mΩ bonding wire of SOT-23 package, the drop will be at lease

13.8mV for 150mA load current. This means, an approximately 60% of load

regulation has been improved over its non-bonding wire compensated version.

5.2.1.4 Dropout Voltage Characteristic

The drop-out voltage performance is depicted by Figure 5.7. The circuit achieved

a drop-out voltage of 0.5mV for no load current, 241mV for 50mA load current

and 633mV for 150mA load current.

Figure 5.7: Dropout voltage of target LDO.

5.2.1.5 Line Regulation Characteristic

Figure 5.8 shows DC characteristics of LDO by changing VDD from 0.5V to 2.5V

at various load currents ILOAD=0mA, ILOAD=50mA and ILOAD=150mA. The

LDO is regulating VOUT properly without any effects of the proposed circuits.

The circuit achieved a line regulation performance of roughly 0.231%/V.

134


Figure 5.8: Line regulation of proposed LDO.

Figure 5.9: Quiescent current of proposed LDO.

135


5.2.1.6 Quiescent Characteristic

Figure 5.9 shows the quiescent current flow as a function of load-current. Quies-

cent current at zero load current was 8.5µA measured at VDD=VOUT +1V whereas

its peak was at 35µA during maximum load current conditions at the same VDD.

The increase in current is expected because the DC boosting circuit worked to

boost the bias current of error amplifier in order to maintain other characteristics

such as noise, PSRR, etc. The DC boosting circuit is design to start operating

at a load current of approximately 2mA.

5.2.1.7 Summary of Electrical Performance

Table 5.1 shows the summary of the electrical performances of the complete LDO

with proposed Quick Response Circuit, Bulk-Gate Control Circuit, Bonding Wire

Compensated Circuit.

136


Table 5.1: Electrical performances summary of proposed LDO.



Input Voltage Range (VDD) 0 ∼ 2.5V


Dropout Voltage

(VOUT = 1.2V, ILOAD = 150mA) 633mV

Quiescent Current (No load) 8.5µA

Quiescent Current (Full load) 35µA

Line Regulation

(ILOAD = 50mA) 0.231%/V

Load Regulation


Load Transient Undershoot

(ILOAD = 0.1 ⇐⇒ 150mA, COUT =4.7µF) -116mV

Load Transient Overshoot

(ILOAD = 150 ⇐⇒ 0.1mA, COUT =4.7µF) 104mV

PSRR @ 10Hz

(VOUT = 1.2V, ILOAD = 50mA) 75dB

PSRR @ 1KHz


Output Capacitor Range (COUT ) 0.47 ∼ 4.7µF

137


5.2.2 Measurement of LDO with Over Current Protection

5.2.2.1 Limit Current and Holding Current

The testing of the proposed circuit is done with the lowest VOUT =1.2V and the

highest VOUT =3.6V under the following conditions. The reference voltage is set

to VREF =0.7V and feed back resistance R1=1MΩ while R2 is adjusted to reach

a required output voltage. The decoupling capacitor at input and output node

to stabilize the circuit is 1µF for each. As shown in testing circuit in Figure 5.10,

the load current is created by PMOSFET whose gate is controlled by a function

generator.

Figure 5.10: Testing circuit.

Figure 5.11 shows the DC testing results of over current protection at VOUT =1.2V

and VOUT =3.6V for VDD changed from VOUT +0.5V to 5.2V and from VOUT +0.5V

to 5.6V respectively. The dependency of limit current and holding current for

each input voltage and output voltage of LDO is shown in Figure 5.12(a), while

the quiescent current of proposed circuit is shown in Figure 5.12(b).

Figure 5.13 shows the shut down characteristic of VOUT =1.2V type at VDD

= VOUT +1V while over current took place. We got the limit current as about

200mA and the holding current as 17.8mA.

138


Figure 5.11: Over current limiting at VOUT =1.2V and VOUT =3.6V.

Figure 5.12: VDD and VOUT dependency and quiescent current.

Base on these results, the limiting current of the proposed circuit is less depen-

dent on VDD. However, the variation of the limiting current at VDD=VOUT +0.5V

is bigger comparing to the variation at VDD>VOUT +1V. That is because of the

insufficient differential voltage between VDD and VOUT which is necessary to drive

139


Figure 5.13: Transient response at VOUT =1.2V.

Power MOSFET in saturation region. Although, the accuracy of the conventional

circuits is not available, the limiting current of the proposed circuit is considered

more accurate in comparison to that of the conventional circuits. Different from

the proposed current sensing method described in this paper, the conventional

circuit [38] utilized the single-end amplifier to detect the over current. How-

ever, the single-end amplifier is greatly influenced by the temperature and device

parameter.

The proposed circuit also has a very stable holding current at any VDD and

VOUT setting. The stable holding current is achieved because it is determined

by the constant current made by MF1. The proposed method is different from

that of [38],[39] in which the foldback circuit utilizes the resistance to decide the

holding current. These kind of circuits are considered more sensitive to operating

conditions. The holding current plays an important role for VOUT to revert to

initial value after the over current is released.

The calculation from the testing result has shown that the quiescent current

of the proposed circuit itself is about 0.82µA for VOUT =1.2V, VDD=2.2V and

ILOAD=200mA. The low consumption power is achieved because most parts of

the circuit such as the Schmitt Trigger circuit and PTG control circuit consume

no power before over current takes place.

140


5.2.2.2 Electrical Performances Summary

Table 5.2: Electrical performances summary of LDO with over current protection

circuit.



Input Voltage Range (VDD) 0 ∼ 6V


Dropout Voltage

(VOUT = 1.2V, ILOAD = 150mA) 478.5mV

Quiescent Current 6µA

Line Regulation

(ILOAD = 50mA) 0.13%/V

Load Regulation


Limit Current

(VOUT = 1.2V, VDD = 2.2V,) 200mA

Holding Current

(VOUT = 1.2V, VDD = 2.2V,) 17.8mA

Output Capacitor Range (COUT ) 0.47 ∼ 4.7µF

Table 5.2 shows the summary of electrical performances of the proposed cir-

cuit. The LDO is operable in the regulator output voltage range from VOUT =1.2V

to VOUT =3.6V and supply voltage range from VDD=VOUT +0.5V to VDD=5.6V.

It consumes only 6µA quiescent current for the whole circuit. The line and

load regulation are 0.13%/V and 0.11mV/A respectively. The drop voltage at

VOUT =1.2V, ILOAD=150mA is 478.5mV.

141

5.3 Evaluation

5.3 Evaluation

5.3.1 Evaluation of High Performance LDO

In this section, the evaluation of designed target LDO with proposed techniques

in comparison to the conventional circuits as well as the past reports are de-

scribed. The evaluation and comparison are done mainly on the three charac-

teristics which have been proposed and implemented in this research. They are,

namely, the characteristic of load transient response, power supply rejection ratio,

load regulation and over current protection.

5.3.1.1 Evaluation of Load Transient Response

The load transient response characteristic of target LDO is evaluated in compar-

ison to the past report [62],[63],[25],[53].

Table 5.3: Comparison of load transient response with previous LDO.

[62] [63] [25] [53] This Work

Year 2000 2003 2005 2006 2008

CMOS (µm) 1.0 0.6 0.09 0.35 0.18

VOUT (V) 1.8 1.3 0.9 1.8 1.2

VDD (V) - - 1.2 - 2.2

ILOAD (mA) 200 100 100 200 150

ISS (mA) 0.030 0.038 6 0.020 0.0085

Ieff (%) NA 99.96 94.3 99.8 99.99

∆VOUT (mV) 220 130 90 54 196

TR (µs) 1.1 2 0.00054 0.27 1.3

COUT (µF) 1 10 0.00060 1 1

ESR Required Yes Yes No No No

FOM (ns) 0.165 4.9 0.035 0.027 0.073

* ISS= Quiescent Current of LDO at no load

142

5.3 Evaluation

To make it fair in comparison, we define the following characteristics to be

the same as those in [53]. However, the overshoot of the output voltage VOUT is

not included in the comparison table since the previous reports discussed mainly

on only the drop voltage.

• Current Efficiency Ieff = ILOAD(max)ILOAD(max)+ISS(max)

• TR = COUT×∆VOUT

ILOAD(max)

• FOM = TR×ISS

ILOAD(max)

Where, ISS, ILOAD are the quiescent current and load current respectively. Even

though, FOM (Figure of Merit) of the proposed circuit can not compare to

[25],[53], the current efficiency of the proposed circuit is much improved com-

paring to the past reports.

Comparing to the LDO which are reported in [62],[63],[25],[53], we got the

comparison shown in Table 5.3.

5.3.1.2 Evaluation of PSRR

The power supply rejection ratio (PSRR) characteristic of target LDO is evalu-

ated in comparison to the past report [56],[58]. The comparison is also done with

the same LDO but without utilizing the proposed Bulk-Gate Control techniques

in order to confirm its effectiveness on PSRR characteristic.

The quiescent current is the main important point when making the compar-

ison of PSRR value. This is because, as mentioned in previous chapter, the high

PSRR can be achieved by increasing the power consumption of error amplifier.

But this will conflict to the research objective which aims to have a high PSRR

without consuming more power.

From the table, the PSRR of proposed LDO with Bulk-Gate Control circuit

has been improved at maximum 16.1dB if compare to [56] at 1KHz ripple fre-

quency even though the quiescent current has much more reduced. If compare to

the same LDO but without utilizing the Bulk-Gate Control circuit, at lease 8dB

at 10Hz and 25.4dB at 1KHz of PSRR have been together enhanced.

143

5.3 Evaluation

Table 5.4: Comparison of PSRR with previous LDO.

[56] [57] [58] This Work This Work

w/o BGC(1) w/i BGC(1)

Year 2004 2006 2007 2008 2008

CMOS (µm) BICOMS 0.13 0.35 0.18 0.18

VOUT (V) 1.2 3.6 2.8 1.2 1.2

VDD (V) 1.7 4.5 3.0 2.2 2.2

ILOAD (mA) 150 150 50 150 150

ISS (mA) 0.550 0.098 0.065 0.008 0.0085

COUT (µF) 0.01 1 0.0001 1 1

ESR Required No 10mΩ No No No

PSRR(2) @ 10Hz (dB) N/A 70dB (3) 53　 67 75

PSRR(2) @ 1KHz (dB) 45 70dB (3) 57 36.4 61.8

(1) BGC=Bulk-Gate Control(2) Measured at ILOAD=50mA, VDD=2.2V, Vrip =200mV(3) Read from Graph

5.3.1.3 Evaluation of Load Regulation

The load regulation characteristic of target LDO is evaluated in comparison to

the past report [52].

The chip reported in [52] is fabricated in the SOT2-3 package in which the

bonding wire resistance is supposed to be 92mΩ. The comparison is shown as in

Table 5.5.

From the table, comparing to the report in [52], approximately 73% of load

regulation has been enhanced with the effectiveness of proposed Bonding Wire

Compensated circuit.

144

5.3 Evaluation

Table 5.5: Comparison of load regulation with previous LDO.

[51] [52] This Work

Year 2006 2008 2008

VOUT (V) 1.3 1.2 1.2

VDD (V) - 2.2 2.2

CMOS (µm) 0.11 BICOMS 0.18

ILOAD (mA) 960 300 150

ISS (mA) 12 0.080 0.0085

COUT (µF) 0.08 1 1

ESR Required No No No

PSRR∗ @ 1KHz (dB) - 70 61.8

LOAD REGULATION∗ (mV/mA) 0.101 0.133 0.036

* Measured at VOUT=1.2V , VDD=2.2V

5.3.2 Evaluation of LDO with Over Current Protection

Table 5.6 shows the comparison of proposed circuit to the conventional circuits.

From the table, the proposed over current circuit performs better than the con-

ventional circuit both in power consumption and operating conditions.

145

5.4 Correspondence of Simulation and Measurement Results

Table 5.6: Comparison of LDO with over current protection to previous LDO.

Name Evaluated Conditions [38] [39] This Work

Year - 2005 2006 2007

CMOS Process (µm) - 0.5 0.6 0.35

VDD Range (V) - - - 1.7-5.6

VOUT Range (V) - 1.8 2.5 1.2-3.6

Quiescent Current (µA) Protection Circuit Only 8.5 - 0.82

Limit Current (mA) VDD=VOUT +1V 320 200 200 (∗)

Holding Current (mA) VDD=VOUT +1V 30 40 17.8 (∗)

LCP(%) 20 % of RS1,RS2 Variation - - 15.5

HCP(%)　 20 % of RS1,RS2 Variation - - 0

LCP(%) 　 Temp= -40∼85C - - 27.2

HCP(%) Temp= -40∼85C - - 13.1

Response Times (µs) VOUT =1.2V, VDD=2.2V - - 230

Chip Size (mm2) Protection Circuit Only - - 0.0079

Note: VOUT=1.2V, (∗): adjustable, LCP= Limit Current Precision,

HCP=Holding Current Precision

5.4 Correspondence of Simulation and Measure-

ment Results

5.4.1 Consideration of High Performance LDO

In this subsection, the correspondence of fabricated chip to the simulation results

is discussed. The correspondence can be classified in to four levels of judgment.

o© : Absolutely inside the margin

© : Almost inside the margin

∆ : Outside the margin but acceptable

× : Absolutely outside the margin

146

5.4 Correspondence of Simulation and Measurement ResultsTab

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147


By referring to the data in Table 5.7, then, we found that even though the

characteristic of the fabricated chip were not realized at the target values but

almost all of them are achieved inside the margin which were predicted by the

simulation.

However, there are few characteristics which their values are outside the mar-

gin. They are the characteristics of dropout voltage and load regulation. Here-

under is the consideration of the two characteristics.

(1) Characteristics of Load Regulation

From Table 5.7, though the target load regulation (<0.1mV/mA) is perfectly

achieved by 0.036%/V, the load regulation of proposed LDO by experimental

results is about 2 times greater than that of simulation results (0.016mV/A).

The factors, which can be considered as the causes of the error, counts for the

unknown bonding resistance at IC pad, the error of bonding wire resistance, etc.

However, the error of load regulation here is compromised when considering about

the present CMOS process variation.

(2) Characteristics of Dropout Voltage

From Table 5.7, the dropout voltage at ILOAD=150mA of proposed LDO by

measurement result is 633mV while that of simulation result is 447mV (worst

case). About 186mV of error has occurred. Like shown in Figure 5.14, the

dropout voltage of LDO relies on five factors as following.

(a) The ON resistance to Power MOSFET (Predictable by Simulation).

(b) The boding resistance between PAD and LEAD (Almost Predictable).

(c) The connecting resistance between PAD and Bonding Wire (Unpredictable).

(e) The connecting resistance between Chip and Socket (Unpredictable).

(f) The wire resistance of evaluation board (Unpredictable).

We found that from (c) to (d), all the resistances are the parasite resistances

which depend on the size or the shape of package, evaluation board, wire length,

etc. Thus, it is almost impossible to predict the value of dropout voltage just

148


by doing the simulation. For example, in case that the above mentioned para-

site resistances reach 1Ω, then the dropout voltage caused by these resistances

will become 1× 150mA = 150mV which is nearly equal to the error between

measurement and simulation (186mV).

Moreover, the dropout voltage 633mV is a practical value and compromised

when looking at the commercial products in [60] in which the dropout voltage is

approximately 1V for the same VOUT = 1.2V type and at ILOAD= 150mA.

Figure 5.14: Evaluation board.

5.4.2 Consideration of LDO with Over Current Protec-

tion

As shown in Equation (4.28), the precision of limiting current of the proposed

over current protection circuit exactly depends on the absolute value of RS2-RS1.

Thus, the precision of the limiting current will proportionally change according

to the manufacturing variation of high poly resistor. Suppose the manufactur-

ing variation of high poly resistor in CMOS process is ±30%. According to the

simulation results, the variation of limiting current is maximum 23.3%. To re-

strain this variation, it is needed to restrain the variation of poly resistance by,

for example, using the bigger scale of the sheet resistor.

From simulation and experimental results, we found that the limiting current

by simulation is 300mA while that of measurement result is 200mA. Although, the

worst case of RS2 and RS1 variations are considered, the lowest limiting current

149

5.5 Solution to Process Variation

must be bigger than 300mA×(1−0.233) = 230.1mA. The error can be considered

as the manufacturing variation and mismatch of Power MOSFET and (MS1,

MS2) pair which are formed in current mirrors. In turn, it leads to a deviation in

the desired limiting current. The mismatch may occur due to a disparity in the

aspect ratio (W/L) or threshold voltage VTH of the MOSFET pair. The aspect

ratio of MS1 and MS2 are designed to (W/L)MS1=(W/L)MS2=2µ/30µ which is

overwhelmingly smaller than (W/L)PWT =30,000µ/1µ of power MOSFET. Thus,

the error of the copied current is inevitable. However, it is possible to achieve

the target limiting current by trimming RS1 or RS2 in revising the mismatch

current. The mismatch between MS1 and MS2 also influences the accuracy of

limiting current. Nevertheless, MS1 and MS2 are critically matched through a

common-centroid, cross-coupled layout that minimizes relative variations in the

two transistors over process variations in both x and y directions along the die.

Also, the dropout voltage at ILOAD=150mA of proposed LDO with over cur-

rent protection circuit by measurement result is 478.5mV while that of simulation

result is 296.3mV (worst case). About 182.2mV of error has occurred. However,

like shown in Figure 5.14, this error can be considered as the cause of the parasite

resistances of the packet, evaluation board, etc.

Other measurement results of other characteristics such as the characteristic

of line regulation, load regulation, holding current are acceptable for the present

CMOS technology. The quiescent current of the LDO is the same both simulation

and measurement results (6µA) because it is defined by the external current

source.


5.5.1 Sensitive Circuit to Process Variation

So far, the trimming technology has been developed to control the influence of

the element variation of an analog circuit. The proposed circuits in this research

also needs the trimming fuse to be placed on an appropriate place in order to

reach the target value.

150


The below presented circuits are the circuits which are sensitive to process

variation and needed to consider the trimming.

5.5.1.1 Bias Circuit

The biasing circuit is a circuit that decides the current consumption of the entire

LDO, and to maintain various characteristics of LDO.

Figure 5.15: Sensitive part of bias circuit.

Thus, an accurate current of the bias circuit is required to be output. The biasing

circuit used in this research is an existed circuit as shown in Figure 5.15, and this

kind of circuit depends on resistance RB to decide the bias current. Therefore,

by providing a RB which can be trimmed, we can control the increasing and

decreasing of the current consumption of LDO by changing the value of RB.

5.5.1.2 Bonding Wire Compensated Circuit

The ON resistance of M8 and M10 in the Figure 5.16 functions to compensate

the bonding wire resistance RWI .

Though this circuit is designed not to depend on the variation of VTH and

the temperature, however, to prevent the deterioration of the load regulation

characteristic caused by the process variation or the contact resistance, etc., it is

preferable to design both transistors with trim-able state.

151


Figure 5.16: Sensitive part of compensated circuit.

5.5.1.3 Comparators of Quick Response Circuit

The part which can be considered as the most sensitive part to the process varia-

tion, is supposed to be the variation of the offset of comparator shown in Figure

5.17.

Figure 5.17 shows an example of load transient response when the offset of

voltage of COM1 changes from Vio1 to Vio1 + 10mV . From the figure, we learned

that the drop voltage of VOUT will vary hugely from -54.5mV to -102.6mV.

To prevent the deterioration in this load transient response characteristic, the

comparator which has variable offset voltage should have chosen. Fortunately, the

offset voltage of the open-loop comparator used in this research can be adjusted

easily by changing the size of MA9 and MH10.

5.5.1.4 Bulk-Gate Control Circuit

The part which can be considered as the most sensitive part to the process vari-

ation, is supposed to be the variation of CK and RK and the channel length

modulation of MK as shown in Figure 5.19.

152


Figure 5.17: Sensitive part of quick response circuit.

The figure also shows an example of PSRR characteristic when the channel

length modulation of MK changes from 2.0µm to 1.5µm. From the figure, we

found that the PSRR badly deteriorated from over 90dB to below 70dB at DC

and low frequency region.

To prevent the deterioration in this PSRR characteristic, the transistor MK ,

resistor RK and capacitor CK should be designed to be trim-able.

5.5.2 Trimming Technology

5.5.2.1 Trimming of Offset Voltage

The efforts to compress the offset voltage error of the comparator by ameliorating

layout technique is indispensable for the precision of load transient response of

target LDO.

However, this effort has its limitation that needs to improve by trimming.

Briefly, trimming is a kind of technique to adjust the size of devices by cutting

the poly (or metal) fuse to fit to the target value. The trimming can be done on

MOSFET device, resistor and capacitor.

153


Figure 5.18: VOUT drop versus offset voltage of comparator.

As shown the in Figure 5.20, the original transistor MH9 can be divided in

to several transistors and join together via the FUSE. By cutting some fuses,

the total size of MH9 will decrease resulted in the increasing of offset voltage of

MH10-MH9 pair.

Since the size of MOSFET can not increase by trimming, it is necessary to

design bigger size of MH9 and reduce its size by trimming according to the need.

For example, if the design target of MH10 and MH9 is (W/L)MH10= 4.5/1 and

154


Figure 5.19: PSRR versus channel length modulation of MK.

(W/L)MH9= 4/1, then the layout should be done at (W/L)MH10= 4.5/1 and

(W/L)MH9= 4.5/1 ((W/L)MH9−a+ (W/L)MH9−b + (W/L)MH9−c).

The decision of trimming is as follows. If the fabricated chip has negative

offset voltage, then there is no need to trim. However, in case the finished chip

has the zero or positive offset voltage, then MA-c or MA-b or both of them might

need to be trimmed to reach the target value.

By doing this way, the target of input offset is achieved and the target load

155


Figure 5.20: Trimming techniques for better load transient response.

transient response can also be obtained.

5.5.2.2 Trimming of Active and Passive Elements

The solution can be reached by trimming technique which mention in previous

subsection. As shown in Figure 5.21, the original MK is divided in to several

parts and all of them connect together via the fuses.

Thus, the channel length modulation (≡ 1/L) can be adjusted to fit the cancel

amount of power supply line ripple by changing the size of MK (fuse trimming).

156


Figure 5.21: Trimming techniques for better PSRR.

Yet, as process variations lead to a large deviation in resistor and capacitor

values which are often known as large as 30% and 10% respectively, the resistor

RK and capacitor CK might need to adjust and fine when there are the process

variation. In this meaning, the same to MK, RK, CK should also be designed

and done the lay out as in Figure 5.21.

157

5.6 Summary

5.6 Summary

In this chapter, a new design techniques implemented in 0.18µm CMOS tech-

nology to improve the load transient response of LDO have been demonstrated.

Compared to other designs, the proposed LDO achieves a fast response time

and low output fluctuation but low power dissipation with only 8.5µA for light

load and 35µA for heavy load at VOUT =1.2V and VDD=VOUT +1V. This includes

the reference circuit, feedback network as well as other proposed circuits. For

1µF output capacitor and 0.1mA ⇐⇒ 150mA load current change, the output

undershoot and overshoot are 196mV and 172mV while the settling time is ap-

proximately 60µs and 65µs, respectively . For 4.7µF output capacitor and the

same 0.1mA ⇐⇒ 150mA load current change, the output undershoot 116mV and

overshoot 104mV are observed.

The Bulk-Gate Controlled Circuit for the low dropout regulator (LDO) to im-

prove the PSRR characteristic has been proposed and implemented in the same

chip. As a result, a low power LDO can be achieved with a high PSRR character-

istic up to 75dB and 61.8dB at 10Hz and 1KHz respectively by implementation

of proposed Bulk-Gate Controlled Circuit even if the consumption current of the

completed LDO is reduced to 8.5µA for no load and 35µA for full load. The pro-

posed circuit has been designed with very few elements which makes it suitable

for efficient LSI design and implementation.

The structure of the Compensated Circuit which improves the load regulation

of the LDO has also been presented and implemented. According to the mea-

surement results, it could actualize the excellent load regulation by maintaining

VOUT at less than 1% fluctuation when the load changes from 0mA to 150mA.

The load regulation after adapted the proposed compensated circuit could main-

tain almost the same performance despite of temperature and threshold voltage

VTH variations.

The total die area of the completed LDO is less than 634µm × 489µm in-

cluding the reference circuit, feedback network as well as all the above proposed

circuit. The summary of the achievement of proposed LDO by simulation and

fabrication is shown in Table 5.7.

158

5.6 Summary

Also, the low power and high accuracy over current protection circuit for

LDO designed with 0.35µm CMOS process is presented. The proposed circuit is

composed of a very simple basic analog and digital circuits. Adding to its wide

range of VDD and VOUT , it offers precise current limiting and stable operation.

The chip size of our proposed circuit is only 0.0079mm2 and consumes very low

power of only 0.82µA. The proposed circuit has no effects on LDO regulation

before the over current takes place. It starts up and works by reducing output

voltage and load current to a stable holding current when the load current has

exceeded a maximum rated value in the way with which LDO can be protected

from latch-up effect. After it starts up, it cuts off the negative feedback loop of

the regulator, so that LDO is prevented from damage.

159

5.6 Summary

160

Chapter 6

CONCLUSION

The research experiences described in this dissertation are summarized. Regard-

ing to the world which overflowed with mobile electronic equipments, the portable

and battery-operated equipment is becoming more sophisticated with multiple

functionality. Longer battery life, or longer time between charges, has become

the differentiating feature for such devices. Needless to say, LDO which is one of

the main integrated circuit functions used virtually in all electronic equipments,

has to be designed in low power consumption but without any performance com-

promising.

Respond to the above requirements, the novel circuit techniques were designed

and that exploited the characteristics of the given process technology. This is not

only beneficial to designs in existing technologies but also to future and more

advanced processes by being fully exploited.

6.1 Enabling Techniques

6.1.1 Quick Response Circuit

The main objective of the technique is to allow low dropout regulator to work in a

battery operated environment. This is driven by the market demand for portable

and compact products, such as cellular phones, pagers, camera recorders, etc.

Many applications demand low load current for the majority of the time while

high load currents are only demanded briefly. As a result, a low quiescent current

161


at low load currents to achieve high current efficiency is an important parameter

to determine the longevity of a battery.

In the proposed technique, a new design of Quick Response Circuit to improve

the load transient response of low dropout regulator using a 0.18µm CMOS tech-

nology is demonstrated. The idea is to add a charge and discharge circuit to help

the Error Amplifier’s operation only during the transient conditions. The Quick

Response Circuit essentially uses a charge and discharge circuit to drive the big

gate capacitor of power MOSFET. Since it get into active mode when only during

transient response, as a result, a minimized quiescent current but with high speed

load transient response is realized.

Compared to other designs, the proposed LDO achieves a fast response time

and low output fluctuation with low power dissipation of only 8.5µA for light

load and 35µA for heavy load at VOUT =1.2V and VDD=VOUT +1V. This includes

the reference circuit as well as feedback network. For 4.7µF output capacitor and

0.1mA ⇐⇒ 150mA load current change, the output undershoot and overshoot

are 116mV and 104mV respectively while the settling time is approximately 65µs

and 48µs respectively.

This proposed circuits is expected to play an important role in field of power

supply circuit for such portable device included mobile phone system, PDA, game

machine, etc. And it is one of many approaches to save the world energy by

reducing the power consumption of each device.

6.1.2 Bulk-Gate Control Circuit

The power supply rejection ratio(PSRR) performance is limited by the DC open-

loop gain of the control loop. This open-loop gain, in turn, is limited by the

required bandwidth of the system and the frequency response implications of

the loading circuits. The bandwidth is then limited by the transient response

requirements and the parasitic poles of the system. The parasitic poles tend to

be at lower frequencies because the circuits are designed with minimum quiescent

current flows. As a result, PSRR performance is also limited.

In the proposed technique, a new design of Bulk-Gate Control Circuit for

LDO to improve the PSRR characteristic has been showed and also fabricated in

162


0.18µm CMOS process. The idea is to add the control circuit to the bulk-gate

of input transistor (Feedback side) to enable the output of error amplifier track

VDD. As a result, without increase the bias current (quiescent current) the ripple

noise is canceled.

A low power LDO can be achieved with a high PSRR characteristic up to 75dB

and 61.8dB at 10Hz and 1KHz respectively by implementation of the proposed

Bulk-Gate Control Circuit. Yet, the consumption current of the completed LDO

is reduced to 8.5µA for no load and 35µA for full load.

6.1.3 Auto Inrush Current Limiting Circuit

To ensure that LDO operates stably and has the good performance of load tran-

sient response, the bigger output capacitor COUT is commonly utilized. Hence, at

VOUT start-up moment, the bigger COUT is, the bigger inrush current will occur.

The badly fall of VDD due to this rush current will cause the malfunction of other

peripheral circuits. The conventional circuit solved the problems by adjusting the

raise time of VREF . It is realized by using the duration of charge time from the

on-chip current source ISS into the off-chip capacitor CSS. However, this method

has some demerits. Since CSS is an off-chip element, it is needed to secure the

area for CSS and so the cost for mass production can not be decreased. It is

unsuitable for the integrated circuit. In addition, if the value of CSS is decided,

the start-up time of the output voltage is decided regardless the output capacitor

and the load current. This also means the output of LDO cannot be started at

high speed. Moreover, big CSS of several nF is needed to achieve the small inrush

current and the start-up time is up to several ms.

In the proposed technique, a new design of auto limiting of the inrush current

of LDO using a 0.18µm CMOS technology is demonstrated. The idea is to monitor

the changes of power MOSTFET gate PD during the start-up moment. The

bigger PD is pulled down to ground, the bigger inrush current flows. Thus, the

auto limiting circuit will work to pull up PD to VDD to reduce the inrush current.

Compared to the conventional LDO structure, the regulator with proposed

circuit adopted, achieves a very low inrush current with the maximum high

speed start-up time only 313µs for output capacitor 10µF and load current

163


ILOAD=200mA, supply voltage VDD=5.5V. Moreover, the maximum inrush cur-

rent is restrained to less than 144.1mA for 10µF output capacitor and load current

ILOAD=0.1mA, supply voltage VDD=2.2V. The proposed circuit will display more

its ability for bigger COUT and lower ILOAD. The proposed circuit also consumes

a DC low power of only 4µA which is applicable to low power LDO design. The

merits of the proposed circuit accounts for the wide range of usable output ca-

pacitor, the small inrush current and the high speed start-up time of output

voltage.

6.1.4 Bonding Wire Compensated Circuit

For LDO itself, the load regulation performance is limited by the DC open-

loop gain of the control loop. However, when the LDO is implemented in to

IC package, this performance relies mostly on the characteristic of bonding wire

of the IC package rather than the DC open-loop. This is because the drop of

VOUT by the resistance of bonding wire is extremely big comparing to the drop

by poor DC open-loop. In the proposed technique, a new design of the bonding

wire Compensated Circuit which improves the load regulation characteristic of

the LDO has been presented. The idea is to compensate the drop of VOUT by

adjusting the feedback voltage according to the load current.

The proposed circuit can actualize the excellent load regulation by maintain-

ing VOUT at roughly 1% fluctuation when the load changes from 0mA to 150mA.

Moreover, the load regulation after adapting the proposed Compensated Circuit

could maintain almost the same performance despite of temperature and thresh-

old voltage VTH variations.

6.1.5 Over Current Protection Circuit

The conventional method of current control of Over Current Protection Circuit

can usually be classified as either “constant-current” or “current-fold back” cur-

rent limiting. When overload occurred, the constant current circuit limits the

output current at a maximum rate which will cause large power dissipation. Al-

ternately, with another scheme the allowable current will fold back as VOUT falls

due to increasing overload, until it reaches as much lower value as possible. Thus

164

6.2 Future Works

the power dissipation is reduced. But this protection scheme is potentially subject

to latch up because of the nonlinear loads’ influence to VOUT during the start-up

of regulator.

Latch-up occurs when the static load line intersects the fold back current curve

because the load draws more current than the regulator can supply at the voltage

where the curves intersect. Generally, this problem can be solved by enlarging

the slope of the fold back curve to avoid the intersection. But this will sacrifice

the internal power dissipation and lower the fold back characteristic.

In the proposed technique, a new design of low power and high accuracy

Over Current Protection Circuit for LDO designed with 0.35µm CMOS process is

presented. The idea is to digitally cut off the closed-loop and fix power MOSFET

gate’s voltage to a limit value which is equally to a holding current. By creating

only two conditions of gate’s voltage, i.e., at normal regulation condition and

overload condition, the latch-up effect can be avoided.

The proposed circuit is composed of very simple basic analog and digital cir-

cuits. Adding to its wide range of VDD and VOUT , it does a precise current limiting

and stable operation. The chip size of our proposed circuit is only 0.0079mm2

and consumes very low power of only 0.82µA. The proposed circuit has no effects

on LDO regulation when the over current has not taken place. It starts up and

works to reduce output voltage and load current to a stable holding current when

load current has exceeded a maximum rated value in the way with which LDO

can be protected from latch-up effect. After it starts up, it cuts off the negative

feedback loop of the regulator, so that LDO is prevented from damage.

6.2 Future Works

6.2.1 Fabrication and Evaluation of Auto Inrush Current

Limiting Circuit

The future works is to complete the chip fabrication and evaluation of the pro-

posed Auto Inrush Current Limiting Circuit presented in Chapter 4.

The approach of the proposed Auto Inrush Current Limiting Circuit is focused

on producing small inrush current and quick start-up time while driving a large

165

6.2 Future Works

Figure 6.1: Layout of LDO with auto inrush current limiting circuit.

output capacitor. To validate the results of the proposed schemes, the circuit is

being fabricated by using 0.18µm CMOS process technology.

The layout has been finished and the chip layout photograph is shown in Fig-

ure 6.1. The whole active area is approximately 580µm × 635µm where reference

circuit, feedback network, ESD protection circuit are implemented.

6.2.2 Capacitor-Free LDO

“ System on a Chip”, or SOC, refers to the integration of all the necessary

electronic circuits of diverse functions onto a single chip, to come up with a

166

6.2 Future Works

complete electronic system that performs the more complex but more useful final

product function. Thus, instead of building an electronic product by assembling

various chips and components on a circuit board, SOC technology will allow all

of these parts to be fabricated together on a single chip, which can function as

the final product itself.

In recent year, with the rapid development of system-on-chip designs, there is

a growing trend toward power-management integration. Need less to say, the lo-

cal LDO which are utilized to power up sub-blocks of a system individually must

be the On-chip. However, for relatively high performance and stable operation,

LDO often employs external capacitors at both the input and output interfaces.

These external capacitors have the equivalent series resistance (ESR) and they

can adversely affect the stability of the regulator. Not only the stability of LDO,

the mentioned external capacitors will also significantly increase the cross talk,

deteriorates the voltage regulation, and creates the load-transient voltage spikes

from the bonding wire inductances. In addition, the externally connected capac-

itors can increase the surface area (space) and external pins required to mount a

regulator on a circuit board/PCB for an electronic device. These disadvantages

will result in the increasing of high cost for mass production.

Under these circumstances, a research on high performance LDO which can

be realized without the external capacitor (capacitor-free) is expected to play an

important role for the future of SOC.

So far, many researchers have proposed many advanced methods to improve

the performance of LDO. However, all of them reveal the fact that there are

limitations on the structure and frequency compensation scheme of classical LDO,

especially for the low-voltage LDO designs. Moreover, the external capacitor,

which is the key for stability and high LDO performance, can not be eliminated

[63]. In a word, the external capacitor is the main obstacle to fully integrating

LDO in system-on-chip designs.

Totally, the design of a low-voltage high-stability and fast-transient LDO with,

preferably, capacitor-free operation has become one of the main topic in our future

works.

167

6.3 Conclusion

6.2.3 Power MOSFET Scaling

In present LDO, the Power MOSFET occupies the majority of the chip area.

When thinking about reducing the chip area to improve the productive efficiency,

the decreasing the Power MOSFET to the smallest size has become an important

problem. Reducing the size of Power MOSFET will result in lower driving ability

of the load current. That is the reason why the size of Power MOSFET is still

occupying the majority of the chip area when it is designed for large load current.

However, with the advance CMOS technology scaling, the driving ability of

Power MOSFET at the same size will improve compared with the past. Hence,

it is necessary to think about the design of the LDO that can correspond to such

Power MOSFET.

Concretely, with the scaling of CMOS technology, the leak current will re-

markably flow in the circuit. A method to solve this leak problem is to shutdown

the power supply during standby mode. In this case, the research of highly ef-

fective regulator with large output current having stable start-up characteristic

is the one of the most necessary thing to be done.

6.3 Conclusion

The first some works had been oriented to proposed a high performance LDO

operated in very low power consumption. As a results, five circuit design tech-

niques have been proposed and verified, which permit the practical realizations

of low dropout regulators in a single, low voltage battery cell environment to

be feasible in current existing technologies. They are the techniques of Quick

Response Circuit for Load Transient Response, Bulk-Gate Control Circuit for

PSRR, Auto Inrush Current Limiting Circuit for Inrush Current, Bonding Wire

Compensated Circuit for Load Regulation and High accuracy structure for Over

Current Protection.

Firstly, a Quick Response Circuit has been proposed to achieve fast load

transient response when load current abruptly changes. The circuit has been

achieved through properly charging and discharging the gate capacitor of power

MOSFET. Secondly, a Bulk-Gate Control Circuit has been proposed to realize the

168

6.3 Conclusion

high power supply rejection ratio (PSRR). The circuit has been achieved through

controlling the bulk-gate of input transistor of error amplifier. Thirdly, in order to

keep the LDO output voltage drop due to bonding wire, the Compensated Circuit

has been proposed. It works to adjust the feedback voltage of feedback network.

Fourthly, an Auto Inrush Current Limiting Circuit has also been proposed to

restrain the inrush current of output capacitor to make sure that the malfunction

of the application system due to inrush current is avoided. Not only the small

inrush current but also the high speed start-up of LDO has been achieved. Fifthly,

an Over Current Protection Circuit which is necessary to protect LDO from the

damage happened by over load current or output shortening, is proposed. The

proposed protection circuit has high accurate limiting current and stable holding

current without getting effects from latchup.

The high performance LDO with proposed Quick Response Circuit, Bulk-

Gate Control Circuit, Compensated Circuit was fabricated with 0.18µm CMOS

technology while the LDO with proposed Over Current Protection Circuit was

fabricated with 0.35µm CMOS technology. For the proposed Auto Inrush Current

Limiting Circuit, the implemented chip is now being fabricated.

The experimental results of the fabricated chips show that the output un-

dershoot and overshoot of load transient response are only 116mV and 104mV

for 4.7µF output capacitor and ILOAD=0.1mA ⇐⇒ 150mA. Also, the PSRR

performance is up to 75dB for 10Hz and remaining high 61.8dB for 1KHz rip-

ple frequency for VOUT = 1.2V and ILOAD=50mA. The output voltage drop is

restrained to less than 1% even when the load current reaches 150mA. The quies-

cent current of the whole chip is 8.5µA for no load and 35µA for full load current.

Meanwhile, the LDO with proposed Over Current Protection Circuit has a high

accurate limiting current of 200mA and a stable holding current of 17.8mA. It

can digitally shut down the output of LDO, thus, the latchup effect is avoided.

From the simulation results, the LDO with Auto Inrush Current Limiting

Circuit can achieve a very small inrush current of 144.1mA and fast start-up

time of 127.7µs for 10µF output capacitor.

With the combination of the above five techniques, the power consumption of

the LDO with proposed circuits adopted have been dramatically reduced while

the performance has been much improved.

169

6.3 Conclusion

170

Appendix A

OTHER MEASUREMENT

RESULTS

A.1 Load Transient Response

In this appendix, the other measurement results of the load transient respond of

proposed LDO with QR circuit are attached. They are the results measured in

the following conditions.

1. Ta=25C (Room Temperature)

2. VOUT =1.2V

3. VDD=VOUT +1V

4. CIN=1µF

5. CCOUT =0.47µF , CCOUT =1.0µF, CCOUT =4.7µF

6. ILOAD=0.1-50mA , ILOAD=0.1-100mA , ILOAD=0.1-150mA ,

171


Figure A.1: ILOAD=0.1mA-50mA and COUT =0.47µF.

Figure A.2: ILOAD=50mA-0.1mA and COUT =0.47µF.

172




173



Figure A.6: ILOAD=150 mA-0.1mA and COUT =0.47µF.

174


Figure A.7: ILOAD=0.1mA-50mA and COUT =1µF.

Figure A.8: ILOAD=50mA-0.1mA and COUT =1µF.

175




176




177




178




179




180

A.2 Power Supply Rejection Ratio


In this appendix, the other measurement results of the Power Supply Rejection

Ratio (PSRR) of proposed LDO with Bulk-Gate Control Circuit are attached.

They are the results measured in the following conditions.

1. Ta=25 C (Room Temperature)

2. VOUT =0.9V, VOUT =1.2V, VOUT =1.5V,

3. VDD=VOUT +1V

4. Vrip=0.2V (Ripple Input Voltage)

5. CIN=1 µF

6. CCOUT =1.0µF

7. ILOAD=1mA , ILOAD=50mA , ILOAD=100mA ,

181


Figure A.19: VOUT =0.9V, ILOAD=1mA without proposed circuit.

Figure A.20: VOUT =0.9V, ILOAD=1mA with proposed circuit.

182




183




184




185




186




187




188




189




190

Appendix B

LAYOUT PHOTOGRAPH

In this appendix, the layout of fabricated chip presented in chapter 4 and chapter

5 of this dissertation are attached.

B.1 LDO with Developed Circuits

The LDO with proposed Quick Response Circuit to improve Load Transient Re-

sponse is fabricated with 0.18µm CMOS process provided by VLSI Design and

Education Center (VDEC) in collaboration with RHOM CO, LTD. At the same

chip, the LDO with proposed Bulk-Gate Control Circuit, Bonding Wire Compen-

sated Circuit to improve Power Supply Rejection Ration (PSRR) is also imple-

mented. Figure B.1 shows the whole layout photograph of fabricated chip with

the above three developed circuits and other peripheral circuits adopted.

B.2 LDO with Protection Circuit

Meanwhile, the LDO with proposed Over Current Protection to realize the accu-

rate limiting current and stable holding current is fabricated with 0.35µm CMOS

process provided by VLSI Design and Education Center (VDEC) in collaboration

with the same RHOM CO, LTD. Figure B.2 shows the whole layout photograph

of fabricated chip.

191


Figure B.1: Fabricated chip of LDO with developed circuits.

192


Figure B.2: Fabricated chip of LDO with over current protection.

193


194

Appendix C

CURRENT-MODE

OPERATIONAL AMPLIFIER

In the automotive industry, LDO is necessary during cold-crank conditions where

the battery voltage can drop below 6V. The increasing demand, however, is read-

ily apparent in mobile battery operated products, such as cellular phones, pagers,

camera recorders, and laptops. This portable electronics market requires low volt-

age and low quiescent current flow for increased battery efficiency and longevity.

As a result, high current efficiency is necessary to maximize battery life. Low

voltage operation is also a consequence of the direction of process technology

towards higher packing densities [23].

A current-mode CMOS circuit is a promising solution to low-voltage analog

CMOS circuit design , since it is theoretically operable with a supply voltage of

several hundred milli-volts greater than the threshold voltage of a MOSFET. A

reduction in power-supply voltage makes voltage signal swings much smaller. To

avoid this problem, recent analog circuit designers have preferably used current

signals instead of voltage signals because current-signal swings are not restricted

by power-supply voltages [65].

In this appendix a low-voltage and low-power-consumption of current-mode

operational amplifier designed by the level shifter technique is proposed and in-

troduced. Even though, the research in this appendix is not related directly to the

design of LDO but it discusses detail on the design technique of how to achieve a

195

C.1 Introduction

current-mode amplifier which is operable in low-voltage condition. The current-

mode circuit design technique mention here is expected to be applicable in many

low-power analog circuits design included the design of current-mode LDO in our

future works.

The proposed current-mode operational amplifier is a simple integrator which

is fabricated using only 12 typical MOSFETs and 2 bias current sources. To

minimize the effects of the common-mode signal and noise on signal processing,

a fully differential structure is applied. From the result of a simulation and mea-

surement, it was confirmed that the proposed circuit functions as an integrator

in the frequency range of 0 ∼ 2.95MHz at a 5V supply voltage and consumed a

maximum DC power 31.8µW.

C.1 Introduction

In recent years, an increasing number of high-performance electronic devices has

been required. Furthermore, world energy problems and environmental damage

have increased in severity. These trends have highlighted the advantages of low

power consumption circuits. On the other hand, most portable appliances such

as mobile phones, hearing aids and implantable cardiac pacemakers , require

low power dissipation to extend the battery life while maintaining a reasonable

battery weight.

Lowering the supply voltage is a way of reducing power consumption in ap-

plications [66]. Over the years, research on low-voltage analog circuit compati-

ble with CMOS technologies has been carried out and several approaches have

been tried. They include the use of level shifter MOSFETs , presented in this

paper, bulk-driven MOSFETS, self-cascode MOSFETs and floating-gate MOS-

FETs. Table C.1 shows a comparison of the above techniques [67]. The table

clearly shows that floating-gate MOSFETs and level-shifter MOSFETs seem to

be much more suitable for low-voltage and low-power analog circuit design be-

cause they can operate with supply voltage less than twice the threshold voltage

(<2V th).

However, the above-mentioned floating-gate devices have the following prob-

lems. First, they cannot be simulated with a conventional MOSFET model using

196

C.1 Introduction

Table C.1: Characteristics of various techniques [66].

Technique Available BW Voltage Power

Bulk-Driven Low ≈ 2V th High

Self-Cascade Medium > 2V th High

Floating-Gate Medium < 2V th Medium

Level-Shifter High < 2V th Medium

an analog simulator such as SPICE, because SPICE can not accept a floating

node that has no DC branch to ground. Therefore, it is necessary to add one

large resistor to each capacitor. Second, when the input voltages to the floating

gates are suddenly changed, or in the initial stages of the floating-gate devices,

it is necessary to discharge the excess electric charges that accumulated in the

floating gates. Thus, additional circuitry for discharge operations is required [68].

On the contrary, the level-shifter MOSFET has a superior performance and

advantages for analog circuit design compared with floating-gate MOSFETs.

First, it is formed using conventional MOSFETs. Thus, there is no need to

fabricate a complicated transistor model for SPICE simulation, nor a circuit for

discharging the excess charge at the floating gate. Also, using an existing guar-

anteed model such as BSIM, the reliability of the simulation result is expected

to be much closer to that of the real world than the model we fabricated. Sec-

ond, without the need for a large floating gate, the chip can be realized with a

small diced area suitable for VLSI design. Third, the circuit utilizing a level-

shifter technique is operable at a low supply voltage no higher than that of the

floating-gate MOSFET, as shown in Table C.1.

Originally, floating-gate MOSFETs were suitable for dynamic memory design

because of the benefit of the electrical charge at the floating gate. They are

also good for circuits that need to control the threshold voltage of the transistor.

However, they are not suitable for all analog circuits because of the problems

mentioned above. Here, we present a current-mode operational amplifier with

the level-shifter technique, which is the most suitable MOSFETs for low-voltage

and low-power-circuit design and comparable to floating-gate MOSFETs.

197

C.2 Level-Shifter MOSFETs

Figure C.1: MOSFET transresistance.


Figure C.1(a) shows the transresistance of an NMOS FET. The input current IIN

flowing through M1 is expressed by:

IIN =KW (VGS − V th)2

2L(C.1)

Where, W and L as well as K=µCox represent the channel width, channel length

and trans conductance, respectively. Thus, the minimum input voltage require-

ment is V in=V GS > V th. This means that the circuit is inoperable when the

supply voltage becomes less than V th. However, if this circuit is modified, as

showing in Figure C.1(b), the input voltage requirement of the circuit is ex-

pressed by V in=V GS1 − V GS2, where V GS1 and V GS2 are the gate-source

voltages of M1 and M2, respectively. We find that both circuits have the same

input resistance but the input voltage requirement for the circuit in Figure C.1(b)

is smaller. V GS1 depends on V DS1 and IB. For zero input current, V DS1 be-

comes zero and IB alone determines V GS1. Hence, V GS1 can be calculated

theoretically by :

• When IB is sufficiently low to make M2 at the sub-threshold region:

198


Figure C.2: IIN−VGS1 characteristics for various IB.

IB = −K[(VGS1 − V th)VGS1 − 1

2VGS1)](1− λVGS1) (C.2)

• When IB is sufficiently high to make M2 at the saturation region:

IB = −1

2K

W2

L2(VGS1 − V th)2(1− λVGS1) (C.3)

Figure C.2 shows the characteristics of IIN − V GS1. The simulation was

carried out under the condition that IB is sufficiently high to make M2 operate

in the saturation region. Here, we set the aspect ratio of M1 as W1/L1 =

2µm/10µm and that of M2 as W2/L2 = 30µm/2µm. From the results, we found

that V GS1 is already higher than V th at V in=0. Furthermore, the level of V GS1

at V in=0 can be modified by the bias current IB of M2.

FigureC.3 shows a wide range of transresistance gains that can be achieved by

varying the aspect ratio of transistor M1. The simulation is carried out under the

condition that IB = 5µA and the aspect ratio of M2 is W2/L2 = 30µm/2µm.

199

C.3 Proposed Current Mode Differential Amplifier

Figure C.3: IIN−VGS characteristics for various values of W1/L1 of M1.

C.3 Proposed Current Mode Differential Am-

plifier

The proposed circuit is shown in Figure C.4. The original feature of our method

is the application of level-shifter MOSFETs to the differential structure of an

integrated circuits. So far, there have been few papers published on current-mode

amplifiers. In these papers, the differential input structure was also described.

Thus, although the level-shifter technique is not the new one, the application of

the level-shifter technique to a differential current-mode amplifier has not yet been

considered. The proposed structure has novel features, in particular, differential

input from the input current equivalent to 0V and a small diced area.

The proposed circuit has the following mechanism. A pair of input currents

IIN+ and IIN− is applied to the drains of M5 and M6 respectively. M3 and M4

function as level-shifters, to shift the gate voltages of M5 and M6 and the M7 and

M8 to above V th at zero input current, enabling them to operate as depletion-

200

C.3 Proposed Current Mode Differential Amplifier

Figure C.4: Proposed current-mode differential operational amplifier.

mode MOSFETs. The drain currents of M7 and M8 are the same as that of the

current mirror. Thus, the sum of feedback currents IFED flows through M9, and

IIN− becomes equal to IIN+. The output stage is formed by M10 and M11 which

function as a current mirror circuit. The current flow through M10 is equal to the

feedback current IFED. M11 copies IFED and integrates IFED by the size ratio

of M10 to M11. M9 functions as the source follower. Thus, at the DC stage the

following relation is obtained.

IIN+ = (IFED) + (IIN−) (C.4)

Thus, we obtain the output current as:

IOUT = [(IIN+)− (IIN−)](W/L)M11

(W/L)M10

(C.5)

By adjusting the sizes of M10 and M11, we can achieve a high current gain

independent of the load. V B is the bias voltage applied to the error amplifier. It

is supplied by a bias current source circuit that we are not going to mention in

201

C.4 Experimental Results

this paper. Here, CP acts as a compensated condenser. The two current sources

IB provide a bias current for M3 and M4 and this current source can be simply

realized using a single p-channel MOSFET.

Figure C.5 shows the simulation result of AC characteristics of the proposed

amplifier. The frequency was swept from 1Hz to 10MHz and IIN+ and IIN− were

set to 10µA and 0µA, respectively.

Figure C.5: AC characteristics (gain and phase responses).


The circuit was designed in accordance with the Motorola CMOS 1.2µm double-

poly process. Figure C.6 shows the micrograph of fabricated chip of the proposed

circuit with a size of 0.11mm2. This area includes the bias circuit for providing

bias voltage.

Figure C.7 shows the DC characteristics of the proposed amplifier. The sim-

ulation was carried out varying IIN+ from 0µA to 10µA , while IIN− was varied

from 0µA to 10µA in 2µA steps.

Figure C.4 shows the characteristics of load dependence for load resistance of

1kΩ and 5kΩ.

202


Figure C.6: Micrograph of proposed circuit.

The measurement results indicate that the proposed circuit has the following

attractive performance attributes. First, the circuit is fabricated using only con-

ventional MOSFETs that can be easily simulated by a circuit simulator. Second,

it can be operated with a 5V supply voltage and consumes only 31.8µW. This

includes the current source circuitry for the bias current. Third, by adjusting the

sizes of M10 and M11, the proposed circuit provides a high current gain indepen-

dent of load, but without increasing power consumption. Fourth, the proposed

circuit can be realized with a small chip size because it does not need the gate

conductance required by conventional circuits using floating-gate devices.

Table C.2 shows the electrical performance of the proposed operational am-

plifier.

203


Figure C.7: DC characteristics.

Figure C.8: Load dependence of output current characteristic.

204

C.5 Conclusion

Table C.2: Electrical performances of proposed amplifier.

VDD 5V

VSS 0 V

Frequency Range 0∼2.95MHz

Power Consumption 31.8µw(Max)

THD < 3% up to 3MHz

DC Gain 20dB

Phase Margin 78 degree

Chip Size 0.11mm2

C.5 Conclusion

A 5V current-mode -differential operational amplifier has been proposed. A new

low-voltage input stage, for which the level-shifter technique is adopted to mod-

ulate the threshold voltage of an n-channel pair, has been described. A new

output stage of the circuit has also been applied that provides a high-output

current-drive capability and load independence but does not increase the power

consumption when the load changes. The proposed circuit functions as an in-

tegrator in the frequency range of 0 ∼ 2.95MHz. The total harmonic distortion

(THD) is less than 3% up to 3MHz for a 10µA peak-to-peak sine-wave input

current. The circuit dissipates less than 31.8µW for a 5V voltage supply. The

integrator has a 20dB DC gain at 5kΩ load. However, this does not mean that

such accurate values of the load resistance are necessary. This circuit is expected

to play an important role in the current signal-processing field for such portable

devices as mobile phones, PDAs and game machines .etc. Such a circuit is one

of many approaches to conserving the planet’s energy supply by reducing power

consumption.

205

C.5 Conclusion

206

Appendix D

LIST OF PUBLICATION

D.1 Journal Paper

[1] Socheat HENG and Cong-Kha PHAM, “Low Power Full Input Range Current-

Mode Operational Amplifier Using Level Shifter Technique,” Journal of

Signal Processing, Vol.10, no.6, pp.385-390, Nov. 2006.

[2] Socheat HENG , Marie SHIMIZU and Cong-Kha PHAM, “An Over Cur-

rent Protection Circuit for Low Power Low Dropout Regulator,” IEICE

Trans. Fundamentals of Electronic, Communications and Computer Sci-

ences, Vol.J90-A, no.07, pp.619-621, Jul. 2007. (In Japanese)

[3] Socheat HENG and Cong-Kha PHAM, “Compensated Circuit for Series Reg-

ulator having Stable Load after Consideration of Bonding Wire Resistance,”

IEICE Trans. Fundamentals of Electronic, Communications and Computer

Sciences, Vol.J91-A, no.1, pp.172-175, Jan. 2008. (In Japanese)

[4] Socheat HENG and Cong-Kha PHAM, “Improvement of Power Supply Re-

jection Ratio (PSRR) of LDO Deteriorated By Reducing Power Consump-

tion,” IEICE Trans. Fundamentals of Electronic, Communications and

Computer Sciences, Vol.J91-A, no.4, pp.535-537, Apr. 2008. (In Japanese)

207

D.2 International Conference and Workshop

[5] Socheat HENG and Cong-Kha PHAM, “A Quick Response Circuit for Low-

Power Series Regulator to improve Load Transient Response,” IEICE Trans.

Fundamentals of Electronic, Communications and Computer Sciences, Vol.J92-

A, no.7, pp.470-476, Jul. 2009. (In Japanese)

[6] Socheat HENG and Cong-Kha PHAM, “Inrush Current Limiting Circuit

With High Speed Start-Up Time For Low Dropout Regulator,” IEICE


ences, Vol.J92-A, no.7, pp.521-523, Jul. 2009. (In Japanese)

[7] Socheat HENG and Cong-Kha PHAM, “A Low-Power High Accuracy Over

Current Protection Circuit for Low Dropout Regulator,” IEICE Trans.

Electronic, Japan. Vol.E92-C, no.9, pp.-, Sep. 2009.

[8] Socheat HENG and Cong-Kha PHAM, “A Low Power High PSRR Low

Dropout Regulator with Bulk-Gate Controlled Circuit,” IEEE Trans. Cir-

cuit and Systems. (Under Review)

D.2 International Conference and Workshop

[1] Socheat HENG and Cong-Kha PHAM, “A 1.2V Current-Mode Operational

Amplifier Using Level Shifter Technique,” Proc. of 2006 International

Workshop on Nonlinear Circuits and Signal Processing (NCSP’06), pp.393-

396, Mar. 2006.

[2] Socheat HENG and Cong-Kha PHAM, “A 1.5V Current-Mode Operational

Amplifier Using Level Shifter Technique,” Proc. of IEEE 2006 International

Symposium on VLSI Design, Automation and Test (VLSI-DAT’06), pp.291-

294, Apr. 2006.

[3] Socheat HENG and Cong-Kha PHAM, “An Over Current Protection Circuit

For Low Power Load Dropout Regulator,” Proc. of IEEJ 2006 International

Analog VLSI Workshop (AVLSIWS’06) , Nov. 2006.

208

D.3 Local Conference and Workshop

[4] Socheat HENG and Cong-Kha PHAM, “Compensated Circuit for Low Dropout

Regulator having Stable Load Regulation after Consideration of Bonding

Wire Resistance,” Proc. of IEEE 2007 European Conference on Circuit

Theory and Design (ECCTD’07), pp.120-123, Aug. 2007.

[5] Socheat HENG and Cong-Kha PHAM, “Quick Response Circuit for Low-

Power LDO Voltage Regulators to improve Load Transient Response,” Proc.

of IEEE 2007 International Symposium on Communications and Informa-

tion Technologies (ISCIT’07), pp.28-33, Aug. 2007.　

[6] Socheat HENG and Cong-Kha PHAM, “Improvement of power supply rejec-

tion ratio of LDO deteriorated by reducing power consumption,” Proc. of

IEEE International Conference on IC Design and Technology (ICICDT’08),

pp.43-46, Jun. 2008.

[7] Socheat HENG and Cong-Kha PHAM, “A Low-Power High Accuracy Over

Current Protection Circuit for Low Dropout Regulator,” Proc. of IEEE

2006 International Symposium on VLSI Design, Automation and Test (VLSI-

DAT’09), pp.47-51, Apr. 2009.

[8] Socheat HENG and Cong-Kha PHAM, “Improvement of LDO’s PSRR De-

teriorated By Reducing Power Consumption : Implementation and Exper-

imental Results,” Proc. of IEEE International Conference on IC Design

and Technology (ICICDT’09), pp.11-15, May. 2009.

[9] Socheat HENG and Cong-Kha PHAM, “Low Power LDO with Fast Load

Transient Response Based on Quick Response Circuit,” Proc. of IEEE In-

ternational Symposium on Circuits and Systems(ISCAS’09), pp.2529-2532,

May. 2009.


[1] Socheat HENG and Cong-Kha PHAM, “Full Input Range Current-Mode

Operational Amplifier Using Level Shifter Technique,” Proc. of the 2nd

IEEE Tokyo Student Workshop, Tokyo Institute of Technology, Dec. 2005.

209


[2] Socheat HENG, Marie Shimizu and Cong-Kha PHAM, “Low Power Over

Current Protection Circuit for Low Dropout Regulator,” Proc. of 1st KMUTT-

UEC Workshop on Electronics, University of Electro-Communications, p47-

p52, Dec. 2006.

[3] Socheat HENG and Cong-Kha PHAM, “Inrush Current Limiting Circuit

For High Speed Start-Up Low Dropout Regulator,” Proc. of the 22nd

Karuizawa Workshop on Circuits and Systems, pp.355-360, Apr. 2009.

210

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218

Acknowledgements

First of all, the author would like to offer his sincerest gratitude to his

supervisor Cong Kha PHAM, the associate Professor of University of

Electro-Communications for his continuous encouragement through-

out the courses from undergraduate to graduate school with his pa-

tience and knowledge whilst providing the author a room to work

on his own way. While experiencing the research and preparing the

dissertation, the author received many invaluable guidance and mean-

ingful discussion which led to the successful accomplishment of his dis-

sertation writing. Also, the author would like to thank his supervisor

for offering the good learning environment which makes his student

life enjoyable and unforgettable. The author would like to dedicate

his Doctor Degree to his supervisor for his encouragement and efforts.

Without him, this thesis would not have been completed successfully.

Also, the author would like to express his sincere appreciation to Pro-

fessor Kazushi NAKANO of the University of Electro-Communications

for his advices, directions and recommendations throughout his grad-

uate program.

Moreover, the author would like to thank all his friends in PHAM

Lab for their tireless efforts to help him writing this thesis as well as

to brave the storm of the century to attend his defense.

In addition, the author would like to send his deep gratitude to his

parents and his brother and sisters for their endowment upon him and

the opportunity that they have presented to him.

Last but not least, the author would like to acknowledge VLSI Design

and Education Center, RHOM Ltd. and On-Semiconductors, Nippon

Motorola Ltd. for their technical supports.

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