pic familly

8/7/2019 pic familly

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1.0. TNG QUAN THIT BTi liu ny cha thng tin c th cho cc thit b sau y:

+PIC18F66J60 +PIC18F87J60+ PIC18F66J65 +PIC18F96J60+ PIC18F67J60 + PIC18F96J65+ PIC18F86J60 +PIC18F97J60+ PIC18F86J65

H ny gii thiu mt dng mi ca cc thit b in p thp vi li thtruyn thng hng u ca tt c cc vi iu khin PIC18 c th l, hiusut tnh ton cao v tnh nng phong ph mt mc gi rt cnh tranh.

Nhng tnh nng ny lm cho h PIC18F97J60 l mt s la chn hp lcho nhiu ng dng hiu sut cao m chi ph l mt xem xt chnh.

1,1 Cc tnh nng chnh1.1.1 La chn dao ng v cc tnh nngTt c cc thit b trong gia nh PIC18F97J60 nm la chn cung cpdao ng khc nhau, cho php ngi s dng mt lot cc la chn trongvic pht trin ng dng phn cng. Cc ty chn ny bao gm:- Hai Crystal ch , s dng tinh th hoc cng hng gm.- Hai ng h bn ngoi cc ch , cung cp cc ty chn ca mt ura 4 by ng h phn chia.- Mt giai on vng kha (PLL) tn s nhn, c sn cho cc ch daong bn ngoi, cho php tc xung nhp ln ti 41,667 MHz.+ mt RC ni b dao ng vi mt lng c nh 31 kHz m cung cpmt la chn nng lng rt thp cho cc ng dng thi gian phn bitdng ch. Cc khi b dao ng ni b cung cp mt ngun tham khotnh nng n nh cung cp cho gia nh b sung cho hot ng mnh m:

+ Fail-Safe Clock Monitor: Ty chn ny lin tc gim st ccngun ng h chnh chng li mt tn hiu tham kho c cung cp bi

cc b dao ng ni b. Nu l mt tht bi ng h xy ra, iu khinc chuyn sang cc b dao ng ni b, cho php tc vn tip tcthpng dng hot ng hoc tt my an ton.

+ Hai tc khi ng: Ty chn ny cho php cc b dao ngni b phc v nh ngun ng h t Power-on Reset, hay nh thct ch ng, cho n khi ng h chnh c sn ngun.

1.1.2 B nh m rngCc h PIC18F97J60 cung cp phong ph cho cc m ng dng, t

64 Kb n 128 Kb ca khng gian m. Cc t bo b nh Flash cho


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chng trnh c nh gi vo cui 100 xa / ghi chu k. Lu gi dliu m khng lm mi l c tnh d dt hn 20 nm.

Cc gia nh PIC18F97J60 cng cung cp rt nhiu phng cho dliu ng dng nng ng vi 3.808 byte d liu b nh RAM.

1.1.3 b nh ngoi BusTrong trng hp khng chc rng 128 Kb b nh khng chomt ng dng, cc thnh vin 100-pin ca h PIC18F97J60 cng thchin mt Bus b nh ngoi (EMB). iu ny cho php chng trnh iukhin ni b truy cp vo a ch mt khng gian b nh trong ln n 2MB, cho php mt mc truy cp d liu s 8-bit thit b c th yucu. iu ny cho php ty chn b nh b sung, bao gm:

:- S dng s kt hp ca chip v b nh ngoi ln n gii hn 2-Mbyt

- S dng b nh Flash bn ngoi m ti lp trnh ng dng hay dliu ln cc bng- S dng cc thit b b nh RAM bn ngoi lu tr lng d liu lnbin

1.1.4 Tp lnh m rng

H PIC18F97J60 thc hin phn m rng ty chn i vi cc tplnh PIC18, thm tm hng dn mi v mt ch biu c lp chmc. Ni bt nh l mt ty chn cu hnh thit b, m rng c thitk ti u ha li m cc ng dng ban u c pht trin bng ccngn ng cp cao, nh C.

1.1.5 D dng di chuyn

Bt k kch thc b nh, tt c cc thit b chia s cng mt tphp phong ph ca cc thit b ngoi vi, cho php cho mt con ngchuyn i trn tru nh cc ng dng pht trin v tin ha.

1,2 Tnh nng c bit khc+ Giao tip: H PIC18F97J60 kt hp mt lot cc thit b ngoi vi

giao tip ni tip, trong c ti hai USART c lp nng cao v ln tihai Master module SSP, c kh nng c hai ch SPI v I2 Ctm(Masterv Slave) hot ng. Ngoi ra, mt trong nhng mc ch chung cng I /O c th c cu hnh li nh mt Parallel Slave Port 8-bit trc tipx l thng tin lin lc n x l.

+CCP Modules: Tt c cc thit b trong h kt hp hai Capture /

Compare / PWM (CSTQ) m-un v ba Enhanced CSTQ (ECCP)module ti a ha tnh linh hot trong ng dng iu khin. Ln n


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bn thi gian c s khc nhau c th c s dng thc hin cc hotng khc nhau cng mt lc. Mi phng trong s ba m-un ECCPcung cp ti a bn kt qu u ra PWM, cho php vi tng s mi haiPWM. Cc m-un ECCP cng cung cp nhiu tnh nng mang li li

ch, bao gm la chn cc, thi gian cht c th lp trnh, t ng tt myv khi ng li v ch ra na cu v ton cu.+10- bit A / D chuyn i: module ny kt hp vi vic mua li

thi gian lp trnh, cho php mt knh c la chn v chuyn i c bt u m khng cn ch i trong mt thi gian ly mu v do, gim chi ph m.

+ M rng Watchdog Timer (WDT): y l phin bn nng caokt hp mt prescaler 16-bit, cho php mt phm vi thi gian-out mrng.

1,3 Chi tit v cc thnh vin gia nh c nhnCc thit b trong h PIC18F97J60 c sn trong pin-64, 80 v cc

gi pin-100-pin. S khi trong ba nhm c th hin trong hnh 1-1,hnh 1-2 v hnh 1-3.

Cc thit b c phn bit vi nhau trong bn cch:1. Chng trnh b nh Flash (ba kch c, t 64 Kb cho cc thit b

PIC18FX6J60 n 128 Kb cho cc thit b PIC18FX7J60).2. knh A / D (mi mt cho cc thit b 64-pin, mi lm cho cc

thit b pin 80-pin v mi su cho cc thit b 100-pin).3. Giao tip Serial module (mt EUSART module v mt module

MSSP trn cc thit b 64-pin, hai EUSART module v mt moduleMSSP trn 80-pin thit b v hai EUSART m-un v hai MSSP m-untrn cc thit b 100-pin).

4. I / O pins (39 ngy 64-pin thit b, 55 trn cc thit b 80-pin v70 trn cc thit b 100-pin).

Tt c cc tnh nng khc cho cc thit b trong gia nh ny l

ging nhau. y l nhng tm tt trong Bng 1-1, 1-2 v Bng Bng 1-3.Cc s chn cho tt c cc thit b c lit k trong Bng 1-4,

1-5 v Bng Bng 1-6.

2,0 Cu hnh B dao ng

2,1 Tng quanCc thit b trong gia nh PIC18F97J60 v kt hp mt b dao

ng ng h h thng vi iu khin khc vi tiu chun thit b

PIC18FXXJXX. Vic b sung cc module Ethernet, vi yu cu camnh cho mt ngun n nh ng h 25 MHz, lm cho n cn thit


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cung cp mt b dao ng chnh c th cung cp tn s ny l cng nhmt lot cc tc ng h khc nhau vi iu khin. Tng quan v ccu b dao ng c th hin trong hnh 2-1.

Tnh nng dao ng khc s dng trong PIC18FXXJXX vi iu

khin nng cao, chng hn nh cc b dao ng RC bn trong v chuyni ng h, vn nh c. H s c tho lun sau ny trong chng ny.Cc loi dao ng 2,2

Cc gia nh PIC18F97J60 ca cc thit b c th hot ng trongnm ch dao ng khc nhau:

1. HS tc cao Crystal / ting ku vang2. HSPLL tc cao Crystal / ting ku vang vi phn mm iu

khin PLL3. EC External Clock vi FOSC / 4 u ra

4. ECPLL ngoi ng h vi phn mm iu khin PLL5. INTRC ni b dao ng 31 kHz

2.2.1 iu khin dao ng

Cc ch dao ng c chn bng cch lp trnh cc FOSC2:FOSC0 cu hnh bit. FOSC1: FOSC0 bit chn cc ch mc nh cab dao ng chnh, trong khi FOSC2 chn khi INTRC c th c vindn. Vic ng k OSCCON (ng k 2-2) chn ch hot ng ngh. N ch yu c s dng trong kim sotng h chuyn i trongcc ch quyn qun l. S dng ca n c tho lun ti mc 2.7.1"Oscillator Control ng k". Vic ng k OSCTUNE (ng k 2-1)c s dng chn tn s ng h h thng t ngun dao ng chnhbng cch chn kt hp ci t prescaler postscaler / v cho php ccPLL. S dng ca n c m t trong Phn 2.6.1 "PLL Block".

2,3 Crystal Oscillator / Gch cng hng (Cc ch HS)Trong ch HS hoc HSPLL Oscillator, tinh th c kt ni vi ccchn OSC1 v OSC2 thit lp dao ng. Hnh 2-2 cho thy cc kt ni

pin.Vic thit k b dao ng yu cu s dng ca mt tinh th no c xpcho cc hot ng cng hng song song.

2.4 u vo ng h bn ngai (EC Modes)

EC v ECPLL ch dao ng yu cu mt ngun ng h bnngoi c kt ni vi cc pin OSC1. Khng c dao ng thi gian khing yu cu sau khi mt Power on Reset hoc sau khi thot khi ch

Sleep. Trong ch EC Oscillator, tn s dao ng chia cho 4 l c sntrn cc pin OSC2. Tn hiu ny c th c s dng cho mc ch th


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nghim hoc ng b ha logic khc. Hnh 2-3 cho thy cc kt nipin cho ch EC Oscillator.

Mt ngun ng h bn ngoi cng c th c kt ni vi pinOSC1 ch HS, nh trong Hnh 2-4. Trong cu hnh ny, cc pin

OSC2 c m. Dng tiu th trong cu hnh ny s c phn cao hn sovi EC ch , nh l oscillators ni mch phn hi s c kch hot(trong ch EC, cc mch phn hi b v hiu ha).

2,5.Dao ng ni khi

Cc gia nh PIC18F97J60 ca cc thit b bao gm mt ngun daong ni b (INTRC) m cung cp mt u ra 31 kHz trn danh ngha.Cc INTRC c kch hot trn thit b in v ng h cc thit b trongchu k cu hnh ca n cho n khi n i vo hot ng ch . INTRCcng c kch hot nu n c chn l ngun ng h thit b hocnuc nhng iu sau y c kch hot:

+Fail-Safe Clock Monitor+Watchdog Timer+ Hai tc khi ng

Nhng tnh nng ny c tho lun chi tit hn trong phn 24,0 "cim chnh ca CPU. "Cc INTRC cng c th ty chn cu hnh nh ngun ng h mc nhtrn thit b khi ng bng cch thit lp cu hnh FOSC2 bit. iu nyc tho lun trong Mc 2.7.1 "Oscillator Control ng k".

2.6 Hot ngEthernetvng hccvi iu khin

Mc d cc thit b ca h PIC18F97J60 c th chp nhn mt lotcc tinh th v cc u vo b dao ng bn ngoi, h lun lun phi cmt ngun 25 MHz ng h khi c s dng cho cc ng dngEthernet. Khng cung cp c thc hin cho ni b to ng hEthernet yu cu t mt ngun chnh ca mt b dao ng tn s khcnhau. Mt sai tn s c xc nh, c th khng bao gm vic s dngcc b cng hng gm.

Xem Phn 27,0 "ElectricalCharacteristics", Bng 27-6, thng s 5,cho bit thm chi tit.


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2.6.1 PLL BLOCK

p ng mt lot cc ng dng v tc ng h vi iu khin,

mt khi PLL ring bit c kt hp vo h thng ng h. N bao gmba thnh phn:

+ Mt prescaler cu hnh (1:02 hoc 1:3)+ Mt s nhn tn s 5x PLL

+ Mt postscaler cu hnh (1:1, 1:02, hoc 1:3)

Cc hot ng ca cc thnh phn blocks PLL c kim sot biOSCTUNE ng k (ng k 2-1). Vic s dng cc prescaler blockis

PLL v postscaler, c hoc khng c cc PLL chnh n, cung cp mtlot cc tn s ng h h thng la chn, bao gm c khng thay i25 MHz ca b dao ng chnh. y cc cu hnh b dao ng c thtng thch vi cc hot ng Ethernet c th hin trong Bng 2-2.

2.7 Ngun ng h v dao ng chuyn mchCc cc thit b ca h PIC18F97J60 bao gm mt tnh nng cho php

cc thit b ngun ng h c chuyn t cc b dao ng chnh lmt ngun thay th ng h. Cc thit b ny cng cung cp hai ngunng h thay th. Khi mt ngun ng h thay th c kch hot, scmnh khc nhau qun l ch hot ng c sn. V c bn, c ba ngunng h cho cc thit b ny:

+ Tiu dao ng+ Trung dao ng+ B dao ng ni khi

Cc dao ng chnh bao gm ch External Crystaland Resonator

and External Clock modes. Cc ch c th c xc nh bi ccFOSC2: bit cu hnh FOSC0. Cc chi tit ca cc ch ny c bohim trc trong chng ny.

Cc dao ng trung l nhng ngun bn ngoi khng kt ni vicc chn OSC1 hoc OSC2. Nhng ngun ny c th tip tc hot ngngay c sau khi iu khin c t trong mt ch quyn lc qun l.Cc gia nh PIC18F97J60 ca cc thit b cung cp cc b dao ng nhmt b dao ng timer1 th cp. Trong tt c cc ch qun l innng, b dao ng ny thng l c s thi gian cho cc chc nng nh

mt ng h thi gian thc (RTC).


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Thng thng, mt 32,768 kHz tinh th xem c kt ni gia ccchn RC0/T1OSO/T13CKI v RC1/T1OSI. Loading t cng c kt ni

t mi chn xung t. Cc b dao ng timer1 c tho lun chi tithn trong mc 12.3 timer1 dao ng.Ngoi vic l mt ngun ng h chnh, cc b dao ng ni b c

sn nh l mt ngun nng lng ng h ch qun l. Cc ngunINTRC cng c s dng nh ngun ng h cho mt s tnh nng cbit, nh cc WDT v Fail-Safe Clock Monitor.Cc ngun ng h cho cc thit b gia nh PIC18F97J60 c th hintrong hnh 2-1. Xem Phn 24,0 "c im chnh ca CPU" bit chi titcu hnh ng k.

2.7.1. Kim sot dao ng ng k

Vic him sot dao ng ng k ng k 2-2) iu khin mt s khacnh hot ng ca thit b ng h, c trong hot ng sc mnh vquyn lc trong cc ch qun l.

H thng ng h Chn bit, SCS1: SCS0, chn ngun ng h. Ccngun ng h c sn l cc ng h chnh (c xc nh bi FOSC2s: FOSC0 bit cu hnh), ng h th cp (timer1 b dao ng) v b dao

ng ni b. Nhng thay i ng h sau khi mt ngun hoc nhiu hncc bit c thay i, sau mt khong thi gian chuyn i ngn ng h.Cc OSTS (OSCCON ) v T1RUN (T1CON ) bit ch ra ng hhin ang cung cp ngun ng h in. Cc bit T1RUN cho thy khi ccdao ng timer1 ang cung cp cc ng h in thoi ch ng hth cp. Trong ch qun l in nng, ch c mt trong cc bit ny sc thit lp bt c lc no. Nu bit khng c thit lp, cc ngunINTRC ang cung cp ng h, hoc cc b dao ng ni b ch mibt u v vn cha n nh

Cc bit IDLEN xc nh nu thit b i vo ch Sleep hoc mttrong cc ch Idle khi lnh SLEEP c thc thi. Vic s dng cc bitc v kim sot bit dao ng ng k c tho lun chi tit hn trongphn 3.0 "Power-manager mode".

2.7.2 Dao ng chuyn tip

Cc thit b trong h PIC18F97J60 c cc mch in ngn chnng h glitches khi chuyn i gia cc ngun ng h. Mt tm dng

ngn trong thit b ng h xy ra trong qu trnh chuyn i ng h.Chiu di tm dng ny l tng hp ca hai chu k ca ngun ng h c


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v 3-4 chu k ca ngun ng h mi. Cng thc ny gi nh rng ccngun ng h mi c n nh. Chuyn ng h c tho lun chitit hn trong mc 3.1.2 " Entering Power-Managed Modes ".

2.8 nh hngcach qun l ngun lnngunng hkhcnhau

Khi ch PRI_IDLE c chn, cc b dao ng chnh c chnh tip tc chy m khng b gin on. i vi tt c quyn lc qunl ch khc, cc b dao ng bng cch s dng pin OSC1 b v hiuha. Cc pin OSC1 (v pin OSC2 nu c s dng bi b dao ng) sngng dao ng.

Trong ch th cp ng h (SEC_RUN v SEC_IDLE), cc bdao ng timer1 ang hot ng v cung cp cc thit b ng h. Cc bdao ng timer1 cng c th chy trong tt c cc ch qun l innng khi cn phi ng h timer1 hoc Timer3.

Trong ch RC_RUN v RC_IDLE, cc b dao ng ni b cungcp ngun ng h in. 31 kHz ra INTRC c th c s dng trc tip cung cp ng h v c th c kch hot h tr cc tnh nngkhc nhau c bit, bt k ch qun l nng lng (xem phn 24,2

"Watchdog Timer (WDT)" thng qua cc mc 24,5 "Fail-Safe ClockMonitor " bit thm thng tin v WDT, Fail-Safe Clock Monitor v HaiSpeed-Start-up).

Nu ch Sleep c chn, tt c cc ngun ng h l ngng li.V tt c cc bng bn dn chuyn i dng in c dng li, ch ng t c mc tiu th thp nht hin ti ca thit b (dng in r rch).

Vic kch hot bt k tnh nng trn chip ny s hot ng trong gicng s lm tng tiu th trong hin ti Sleep.The INTRC l cn thit h tr hot ng WDT. Cc b dao ng timer1 c th c iu hnh h tr mt ng h thi gian thc. Cc tnh nng khc c th c iuhnh m khng cn mt ng h thit b ngun (ngha l n l MSSP,PSP, INTx chn v nhng ngi khc). Thit b ngoi vi c th thmng k mc tiu th hin hnh c lit k ti Mc 27,2 " DCCharacteristics: Power-Down and Supply Current ".


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2.9 Power-up DelaysPower-up Delays c iu khin bi hai timers, khng c mch

Reset bn ngoi l cn thit cho hu ht cc ng dng. Vic tr hon mbo rng thit b ny c gi trong Thit lp li cho n khi vic cung

cp in ca thit b c n nh trong nhng hon cnh bnh thng vng h chnh l iu hnh v n nh. i vi thng tin b sung vPower-up Delays, xem Phn 4.6 "Power-up Timer (PWRT)".Nhng gi u tin l Timer Power-up (PWRT), cung cp mt s chmtr c nh trn (thng s 33, Bng 27-12) m in, n lun c kchhot.

Cc b m thi gian th hai l dao ng Start-up Timer (OST), dnh gi cho cc chip trong Thit lp li cho n khi cc b dao ngtinh th l n nh (HS ch ). OST lm iu ny bng cch tnh chu k

dao ng 1024 trc khi cho php dao ng n ng h in thoi.C mt s chm tr ca TCSD khong (s 38, Bng 27-12), sau POR,trong khi iu khin tr nn sn sng thc hin hng dn.

3.0 .POWER-PHNG THC QUN L

Cc thit b gia nh PIC18F97J60 cung cp kh nng qun l in

nng tiu th bng cch qun l xung nhp cho CPU v cc thit b ngoivi. Ni chung, mt tn s ng h thp hn v gim s lng cc mchc tc tiu th in nng thp to nn. V li ch ca quyn lcqun l trong mt ng dng, c ba phng thc chnh ca hot ng:

+ Ch khi ng+ Ch Idle+ Ch ngh

Cc ch ny xc nh m cc phn ca thit b c tc v tc g. Cc ch Idle Run v c th s dng bt k ca ba ngun c snng h (tiu hc, trung hc hoc ni b dao ng khi); cc ch Sleep khng s dng mt ngun ng h.

Cc ch qun l in nng bao gm mt s tnh nng tit kimin c cung cp trn cc thit b MCU trc PIC. Mt l chuyni ng h tnh nng, c cung cp trong cc thit b PIC18 khc, chophp b iu khin s dng b dao ng timer1 thay cho b dao ngchnh. Cng bao gm l ch Sleep, c cung cp bi tt c cc MCU

PIC thit b, ni tt c cc ng h in c ngng li


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3,1 Chn ch qun l Power

Chn mt ch qun l in nng yu cu hai quyt nh: nu CPUl c tc hay khng v c ngun ng h l c s dng.

Cc bit IDLEN (OSCCON ) Chm Cng iu khin CPU, trong khiSCS1: bit SCS0 (OSCCON ) chn ngun ng h. Cc ch cnhn, thit lp bit, cc ngun ng h v m-un b nh hng c tmTt trong bng 3-1.

3.1.1 NGUN NG HCc bit SCS1: SCS0 cho php la chn mt trong ba ngun ng h chocc ch quyn qun l. l:+ Cc h s, theo quy nh ca FOSC2: bit FOSC0 cu hnh

+ Cc ng h th cp (timer1 oscillator)+ Cc b dao ng ni b

3.1.2 ENTERING POWER-MANAGED MODES

Chuyn i t ch qun l in nng vi nhau bt u bng cchti cc OSCCON ng k. Cc SCS1: bit SCS0 chn ngun ng h vxc nh ch Run hoc Idle l c s dng. Thay i nhng th nygy ra mt chuyn i trc tip vi ngun ng h mi, gi s rng nang chy. Vic chuyn i cng c th b tr hon qu trnh chuyn ing h. y l nhng tho lun trong Phn 3.1.3 "Clock Transitions andStatus Indicators" v phn tip theo.

3.1.3 CLOCK TRANSITIONS AND STATUS INDICATORSChiu di ca vic chuyn i gia cc ngun ng h l tng ca

hai chu k ca ngun ng h c v 3-4 chu k ca ngun ng h mi.Cng thc ny gi nh rng cc ngun ng h mi c n nh. Haibit ch ra ngun ng h hin ti v ca tnh trng : OSTS(OSCCON) v T1RUN(T1CON ).

Nhn chung, ch c mt trong cc bit ny s c thit lp trong khi mt ch qun l in nng nht nh. Khi bit OSTS c thit lp, ccng h chnh l cung cp cc thit b ng h. Khi bit T1RUN cthit lp, cc b dao ng timer1 ang cung cp ng h. Nu khng ccc bit ny c thit lp, INTRC l clocking thit b.

3.1.4 NHIU LNH SLEEP

Cc ch qun l in nng c gi vi cc ch dn SLEEP c

xc nh bi cc thit lp ca cc bit IDLEN ti thi im hng dnc thc hin. Nu mt hng dn SLEEP c thc thi, thit b s vo


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ch qun l in nng theo quy nh ca IDLEN ti thi im . NuIDLEN thay i, thit b s vo ch qun l nng lng mi cch nh bi cc thit lp mi.

3,2Ch Run

Trong ch Run, ng h cho c hai li v cc thit b ngoi viang hot ng. S khc bit gia cc ch ny l ngun ng h.

3.2.1 PRI_RUN MODE

Cc ch PRI_RUN l bnh thng, y sc mnh thc hinch ca b vi iu khin. y cng l ch mc nh khi mt thit bReset, tr khi hai tc khi ng c kch hot (xem Phn 24,4 "Hai-Speed Start-up" bit chi tit). Trong ch ny, cc bit OSTS cthit lp. (xem Phn 2.7.1 "Oscillator Control ng k").

3.2.2 SEC_RUN MODE

Cc ch SEC_RUN l ch tng thch vi tnh nng "ng hchuyn i" c cung cp trong cc thit b PIC18 khc. Trong ch ny, CPU v thit b ngoi vi c tc t b dao ng timer1. iu

ny cho php ngi dng ty chn tiu th in nng thp hn trong khivn s dng mt ngun ng h chnh xc cao.Ch SEC_RUN c nhp bng cch thit lp SCS1: bit SCS0 01. Cc ngun thit b ng h l chuyn sang cc b dao ng timer1(xem Hnh 3-1), cc b dao ng chnh l ng ca, cc bit T1RUN(T1CON ) c thit lp v cc bit OSTS l xa.Khi chuyn tip t ch SEC_RUN PRI_RUN, cc thit b ngoi vi vCPU tip tc c tc t b dao ng timer1 trong khi ng h chnhl bt u. Khi ng h chnh tr nn sn sng, mt chic ng h

chuyn v ng h ch yu xy ra (xem Hnh 3-2). Khi cng tc ng hhon tt, cc bit T1RUN c xa b, OSTS bit c thit lp v ccng h chnh l cung cp ng h. Cc bit IDLEN v SCS khng b nhhng bi thc tnh; cc b dao ng timer1 tip tc chy.

3.2.3 RC_RUN MODE

Trong ch RC_RUN, CPU v thit b ngoi vi c tc t bdao ng ni b; cc ng h chnh l ng ca. Ch ny cung cp

vic bo tn nng lng tt nht ca tt c cc ch Run trong khi vnthc thi m. N hot ng tt cho cc ng dng ngi dng khng phi l


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thi im rt nhy cm hoc khng yu cu tc cao ng h ti tt ccc ln. Ch ny c nhp vo bng cch thit lp SCS ti"11 ". Khi cc ngun ng h l chuyn sang cc INTRC (xem Hnh 3-3),cc b dao ng chnh l ng ca v cc bit OSTS l xa.

Ngy chuyn tip t ch RC_RUN PRI_RUN ch , thit b ny tiptc c tc t INTRC trong khi cc ng h chnh l bt u. Khing h chnh tr nn sn sng, mt cng tc ng h cc ng hchnh xy ra (xem Hnh 3-4). Khi cng tc ng h hon tt, cc bitOSTS c thit lp v cc ng h chnh l cung cp cc thit b ngh. Cc bit IDLEN v SCS khng b nh hng bi switch. Cc ngunINTRC s tip tc chy nu mt trong hai WDT hoc Fail-Safe ClockMonitor c kch hot.

3,3SleepMode

Ch Sleep qun l in nng ging ht vi c ch ca ch Sleep cung cp ti tt c cc thit b PIC MCU khc. N c nhp bngcch xa bit IDLEN (cc trng thi mc nh trn thit b Reset) v thchin cc ch dn SLEEP. iu ny s tt cc dao ng c la chn(Hnh 3-5). Tt c cc bit trng thi ngun ng h s b xa.Bc vo ch Sleep t bt k ch khc khng yu cu chuyn ing h. iu ny l bi v khng c ng h l cn thit khi iu khin

bc vo gic ng. Nu WDT c chn, cc ngun INTRC s tiptc hot ng. Nu cc dao ng timer1 c kch hot, n cng s tiptc chy.

Khi mt s kin nh thc xy ra trong ch ng (do gin on,Thit lp li hoc thi gian WDT ngoi), thit b s khng c tc cho n khi cc ngun ng h la chn bi cc SCS1: SCS0 bit tr nnsn sng (xem Hnh 3-6), hoc n s c tc t b dao ng ni bnu c hai tc Start-up hoc Fail-Safe Clock Monitor c kch hot

(xem Phn 24,0 "Tnh nng c bit ca cc CPU"). Trong c hai trnghp, cc bit OSTS c thit lp khi cc ng h chnh l cung cp ccthit b ng h. Cc IDLEN v SCS bit l khng b nh hng bi ccnh thc.

3,4 Idle Modes

Cc ch Idle cho php iu khin ca CPU c la chn ng

ca trong khi cc thit b ngoi vi tip tc hot ng. Chn mt ch Idle c bit cho php ngi dng tip tc qun l tiu th in nng.


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Nu bit IDLEN c thit lp 1 khi mt ch dn SLEEP cthc thi, cc thit b ngoi vi s c tc t ngun ng h la chnbng cch s dng SCS1: SCS0 bit, tuy nhin, CPU s khng c tc. Cc bit m ngun ng h tnh trng khng b nh hng. Thit

IDLEN v thc hin mt ch dn SLEEP cung cp mt phng phpnhanh chng chuyn t mt ch chy cho ch Idle ca n tngng. Nu WDT c chn, cc ngun INTRC s tip tc hot ng. Nucc dao ng timer1 c kch hot, n s cngtip tc chy.

K t khi CPU khng thc hin hng dn, ch li thot him t btk ch Idle l do gin on, trong thi gian WDT hoc mt Reset. Khimt s kin nh thc xy ra, thc hin CPU b tr hon bi mt khong

TCSD (s 38, Bng 27-12) trong khi n tr nn sn sng thc thi m.Khi CPU bt u thc thi m, n s yu l lch bng ngun cng mtng h cho cc ch Idle hin hnh. V d, khi thc dy t ch RC_IDLE, khi dao ng ni s ng h CPU v thit b ngoi vi (nicch khc, RC_RUN ch ). Cc IDLEN v SCS bit l khng b nhhng bi cc nh thc. Trong khi bt k ch Idle hoc ch Sleep, mt thi gian WDT-ra s dn n mt WDT thc tnh v ch Run hin theo quy nh ca SCS1: bit SCS0.

3,5Thot khich Idlev Sleep

Mt li ra t ch ng, hoc bt k cc ch Idle, c kch hotbi mt ngt, mt Thit lp li hoc mt thi gian ra WDT-. Phn nybn v nhng kch t c li thot him gy ra t cc ch quyn qunl.

Nhng hnh ng c h thng con clocking c tho lun trong mich qun l in phn ( xem Phn 3.2 " Run Modes ", mc 3.3 "SleepMode v phn 3.4 Idle Modes).

3.5.1 "EXIT DO INTERRUT"

Bt k ngun ngt c sn c th gy ra thit b thot khi ch Idle, hoc ch Sleep, vi mt ch Run. kch hot chc nng ny,mt ngun gin on phi c kch hot bng cch thit lp cho phpca n bit ti mt trong nhng ghi INTCON hoc PIE. Cc trnh t thotra c bt u khi cc bit c ngt tng ng c thit lp.Trn tt c cc li thot him t Idle hoc cc ch bng cch lm gin

on gic ng, ngnh thc thi m cc vector ngt nu Gi / GIEH bit(INTCON ) c thit lp. Nu khng, m thc thi tip tc hoc h


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s xin vic m khng phn nhnh (xem Phn 9,0 "ngt").Mt s chm tr c nh ca TCSD khong sau s kin nh thc cyu cu khi ri khi ch Sleep v Idle. S chm tr ny l cn thitcho CPU chun b cho thc hin. Hng dn thc hin h s v cc

chu k ng h u tin sau s chm tr ny.

3.5.2 "EXIT DO WDT OUT-TIME"

Mt thi gian WDT-ra s gy ra hnh ng khc nhau ty thuc voch qun l in nng thit b ny trong khi trong thi gian xy ra.Nu thit b khng thc thi m (tt c cc ch Idle v ch Sleep),trong ra thi gian s cho kt qu xut cnh mt t ch qun l nnglng (xem Phn 3.2 "Khi ng ch " v Phn 3.3 "Sleep Mode").

Nu thit b c thc thi m (tt c cc ch Run), trong ra thi gians cho kt qu trong mt Reset WDT (xem Phn 24,2 "Watchdog Timer(WDT)"). Cc b m thi gian WDT v postscaler c thng theo mttrong cc s kin sau y:

+ Thc hin mt gic ng hoc hng dn CLRWDT+ S mt mt ca mt ngun ng h hin ang c chn (nu thtbi Safe Clock Monitor c kch hot).

3.5.3 "EXIT DO RESET"

Thot khi mt Idle hoc ch Sleep bi Reset t ng lc lngcc thit b chy t cc INTRC.

3.5.4 " EXIT WITHOUT AN OSCILLATOR START-UP TIMERDELAY "

Mt s li ra t cc ch quyn qun l khng gi cc OST tt c.C hai trng hp:

+ PRI_IDLE ch , ni m cc ngun ng h chnh l khng ngng+ Cc ngun ng h chnh l mt trong hai ch EC hoc ECPLL

Trong trng hp ny, cc ngun ng h chnh hoc l khng yucu mt b dao ng khi s chm tr k t khi n vn ang chy(PRI_IDLE), hoc bnh thng khng i hi mt b dao ng khi ngchm (EC). Tuy nhin, s chm tr c nh ca TCSD khong sau skin nh thc vn cn cn thit khi ri khi ch Sleep v Idle cho

php cc CPU chun b cho thc hin. Hng dn thc hin h s vcc chu k ng h u tin sau s chm tr ny.


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4.0. ResetCc thit b trong h PIC18F97J60 c s khc bit gia cc loi Thit

lp li:

a) Thit lp li MCLR trong khi hot ng bnh thngb) Thit lp li MCLR trong ch qun l nng lngc)Power-on POR (Reset)d)Brown-out Reset (BOR)e)Configuration Mismatch (CM)f)Hng dn RESETg)Thit lp li ton Stackh)Thit lp li trn di Stacki) Thit lp li Watchdog Timer (WDT) trong khi thc hin

Phn ny bn v Reset c to ra bi s kin cng (MCLR), s kinin (POR v BOR) v cu hnh bt xng (CM). N cng bao gm cchot ng ca cc thi gian bt u khc nhau. Thit lp li ngn xp ccs kin c cp trong mc 5.1.6.4 "Stack Full andUnderflow Resets".t li WDT c cp trong mc 24,2 "Watchdog (WDT) Timer".

4,1Thanh ghi RCON

Thit lp li cc s kin thit b c theo di qua thanh ghi RCON(Thanh ghi 4-1). Cc Thanh ghi thp hn su bit ch ra rng mt Thit lpli c th s kin xy ra. Trong hu ht trng hp, cc bit ny ch cth c thit lp bi s kin ny v phi c xa bi cc ng dng saukhi s kin ny. Tnh trng ca cc bit c, cng nhau, c th c c ch cc loi Thit lp li rng ch cn xy ra. iu ny c m t chi tithn trong phn 4.7 "Thit lp li Nh nc ng k".Vic Thanh ghi RCON cng c mt cht iu khin thit lp u tinngt (IPEN). u tin ngt c tho lun ti mc 9,0 "ngt".

4,2MasterClear(MCLR)

Cc chn MCLR cung cp mt phng php kch hot mt Resetcng bn ngoi ca thit b. Mt Thit lp li c to ra bng cch gichn thp. PIC18 m rng cc thit b vi iu khin c mt b lc tingn(nhiu) trong ng dn MCLR Thit lp li m pht hin v b quacc xung nh. Cc chn MCLR khng li xung mc thp bi bt k

Reset ni b, bao gm c WDT.


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4,3Power-on (POR) Reset

Mt iu kin Power-on Reset c to ra trn chip bt c khi noVDD tng trn mt ngng nht nh. iu ny cho php cc thit b bt u trong trng thi khi to khi VDD l cho hot ng. tndng li th ca cc mch POR, buc cc chn MCLR thng qua in tr(1 k n 10 k) n VDD. iu ny s loi b cc thnh phn bnngoi RC thng l cn thit to ra mt Power-on Reset chm tr. Mtt l tng ti thiu cho VDD c quy nh (tham s D004). Trong mtthi gian tng chm, xem hnh 4-2. Khi thit b bt u hot ng bnhthng (tc l ra khi tnh trng Thit lp li), cc thng s vn hnhthit b (in p, tn s, nhit , vv) phi c p ng m bo hotng. Nu nhng iu kin ny khng c p ng, thit b cn phic t chc vo Thit lp li cho n khi cc iu kin hot ng cp ng. S kin POR b bt do bit POR (RCON ). Cc trng thi cabit c thit lp l "0" bt c khi no mt Power-on (POR) Reset xy ra,n khng thay i cho bt k s kin Thit lp li khc. POR l khngt li '1 'bi bt k s kin phn cng. nm bt nhiu s kin,ngi s dng t thit lp li cc bit '1 'trong phn mm sau y bt kPower-on Reset.

4,4Brown-out Reset(BOR)

Cc thit b trong h PIC18F97J60 kt hp chc nng BOR n ginkhi cc iu chnh ni b c kch hot (pin ENVREG gn lin viVDD). Bt c thay i ca VDD di VBOR (D005 tham s), cho lnhn TBOR thi gian (s 35), s thit lp li cc thit b. Mt Reset c thhoc khng th xy ra nu VDD gim xung di VBOR t hn TBOR.Cc chip s vn trong Brown-out Reset cho n khi VDD ln trn

VBOR.Mt khi mt BOR xy ra, cc Timer Power-up s gi cho chiptrong Thit lp li cho TPWRT (s 33). Nu VDD gim xung diVBOR trong khi Timer Power-up ang chy, cc chip s quay tr lithnh mt Brown-out Reset v Power-up Timer s c khi to. Mtkhi VDD ln trn VBOR, cc Timer Power-up s thc hin chm trthm thi gian


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4,5 Configuration Mismatch (CM)

Cc Configuration Mismatch (CM) Reset c thit k pht hinv c gng phc hi t b nh, lm h hng cc s kin ngu nhin.

Chng bao gm Electrostatic Discharge (ESD) cc s kin c th gy raph bin duy nht-bit thay i trong sut cc thit b v kt qu tht bithm khc. Trong PIC18FXXJ thit b Flash, cc thit b ghi cu hnh(nm trong khng gian b nh cu hnh) ang tip tc theo di trong qutrnh hot ng bng cch so snh gi tr ca mnh ng k min ph .Nu khng ph hp c pht hin gia hai b ng k, mt Thit lp liCM t ng xy ra. Nhng s kin ny c chp bi cc bit CM(RCON ). Cc trng thi ca bit c thit lp l "0" bt c khi nomt s kin CM xy ra, n khng thay i cho bt k s kin Thit lp li

khc.

4,6 Power-up Timer (PWRT)

H thng PIC18F97J60 ca cc thit b kt hp mt on-chip Power-up Timer (PWRT) gip iu chnh qu trnh Power-on Reset. PWRTlun lun c kch hot. Chc nng chnh l m bo rng cc thitb in p n nh trc khi m c thc thi.

Cc Timer Power-up (PWRT) ca cc thit b h thngPIC18F97J60 l mt truy cp 11-bit s dng ngun INTRC nh l uvo ng h. iu ny mang li mt khong thi gian gn ng bng2048 x 32 s = 66 ms. Trong khi PWRT ang tnh ton, thit b c tchc vo Reset.

4.6.1 TRNH T THI GIAN CH

Thi gian ch PWRT c thit lp sau khi cc xung POR xa.Tng thi gian ch s thay i da trn tnh trng ca PWRT ny. Hnh4-3, hnh 4-4, hnh 4-5 v hnh 4-6 tt c cc m t trnh t thi gian chv power-up.

K t thi gian ch xy ra t xung POR, nu MCLR c gi mc thp di, cc PWRT s ht hn. a MCLR cao s bt u thchin ngay lp tc (Hnh 4-5). iu ny rt hu dng cho mc ch thnghim hoc ng b ha nhiu hn mt thit b hot ng song songPIC18FXXJ6X


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5,0 T CHC B NH

C hai loi b nh trong cc thit b vi iu khin PIC18 Flash:

-B nh chng trnh- RAM d liu

Ging nh cc thit b kin trc Harvard, nhng b nh chng trnhv d liu s dng cc bus ring bit. iu ny cho php truy cp ngthi vo 2 khng gian b nh .

Thng tin chi tit v hot ng ca b nh chng trnh Flash ccung cp ti mc 6.0 Flash Program Memory

5,1T CHC CHNG TRNH B NH

Cc vi iu khin PIC18 thc hin truy cp chng trnh 21-bit ckh nng nh a ch 2-Mbyte mt chng trnh khng gian b nh.Vic truy cp vo mt v tr gia cc ranh gii trn ca b nh vt l thchin v a ch 2-Mbyte s tr li tt c gi tr l "0" (mt lnh NOP).Cc h thng PIC18F97J60 cung cp ba kch c ca b nh chng trnh

on-chip Flash, t 64 Kb (32.764 n t hng dn) n 128 Kb (65.532n t hng dn). Cc bn chng trnh b nh dnh cho cc n vthnh phn trong h thng c th hin trong hnh 5-1. (BN BNH CA CC THIT B H THNG PIC18F97J60)

5.1.1CC VC-T B NH CNG

Tt c cc thit b PIC18 c tng cng ba hard-coded tr v ccvect trong khng gian chng trnh b nh ca chng. a ch vectorReset l gi tr mc nh chng trnh truy cp tr li trn tt c cc

thit b Reset, n c v tr 0000h.

Thit b PIC18 cng c hai a ch vector ngt dnh cho vic x lcc ngt u tin cao v ngt u tin thp. Cc vector ngt u tin caoc t ti a ch 0008h v cc vector ngt u tin thp 0018h. V trca chng lin quan n bn chng trnh b nh c hin th tronghnh 5-2.

Hnh 5-2: VECTOR CNG V V TR CU HNH CHO CC

THIT B H THNG PIC18F97J605.1.2 CC N V CU HNH FLASH


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V cc thit b h thng PIC18F97J60 khng lu tr b nh cuhnh, bn n v u ca b nh chng trnh on-chip c dnh ringcho thng tin cu hnh. Trong Reset, cc thng tin cu hnh c sao

chp vo s ng k Cu hnh.

n v Cu hnh c lu trong v tr chng trnh b nh cachng theo s th t, bt u vi byte thp ca CONFIG1 ti a ch thpnht v kt thc vi byte trn ca CONFIG4. i vi nhng thit b ny,ch c n v cu hnh, CONFIG1 n CONFIG3, c s dng;CONFIG4 c dnh ring. Cc a ch thc t ca cc n v cu hnhFlash dnh cho cc thit b trong h thng PIC18F97J60 c th hintrong bng 5-1. V tr ca chng trong bn b nh c hin th vi

cc vect b nh khc trong hnh 5-2.Chi tit v thit b n v cu hnh c cung cp trong mc 24,1'Configuration Bits. Bng 5-1: N V CU HNH FLASH CHO HTHNG PIC18F97J60

5.1.3 CC CH CHNG TRNH B NH PIC18F9XJ60/9XJ65

Cc thit b 100-pin trong h thng ny c th c di a ch ln ntng s l 2 MB chng trnh b nh. iu ny t c thng qua busb nh bn ngoi. C hai ch hot ng khc bit c sn cho cc b

iu khin:

- Vi iu khin (MC)- M rng Vi iu khin (EMC)

Cc ch chng trnh b nh c xc nh bng cch thit lpcc bit cu hnh EMB (CONFIG3L ), nh trong mc ng k 5-1.(Xem thm Phn 24,1 'Configuration Bits bit chi tit thm v ccbc cu hnh thit b.)

Cc ch chng trnh b nh hot ng nh sau:- Cc ch vi iu khin ch truy cp vo b nh on-chip Flash. N

lc c phn u ca b nh on-chip dn n c tt c cc gi tr 0(mt lnh NOP).

Cc ch vi iu khin cng ch hot ng cc thit b 64-pin v80-pin.

- Ch vi iu khin m rng cho php truy cp vo c hai chngtrnh b nh ni b v bn ngoi nh mt khi. Cc thit b c th

truy cp vo b nh chng trnh on-chip ca n. Trong phn ny,cc thit b truy cp vo chng trnh b nh bn ngoi ln n ti


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a 2-Mbyte khng gian chng trnh.T ng thc hin chuyn giahai b nh theo yu cu.

5.1.4 CH VI IU KHIN M RNG V THAY I A CHTheo mc nh, cc thit b trong ch vi iu khin m rng

trc tip trnh by cc gi tr chng trnh truy cp vo a ch busngoi cho cc a ch trong khong khng gian b nh bn ngoi. Trnthc t, c ngha l a ch ny trong thit b b nh ngoi nm dihng u ca b nh on-chip l khng c.

trnh iu ny, cc ch vi iu khin m rng thc hinmt thay i a ch ty chn cho php a ch dch thut t ng.Trong ch ny, a ch trnh by trn bus bn ngoi c chuynxung bi kch thc ca chng trnh b nh on-chip v c nh x

li bt u t 0000h. iu ny cho php s dng y khng gianb nh ca cc thit b b nh ngoi

pic familly

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