Paper Review Presentation

Paper Title:

Hardware Assisted Two Dimensional Ultra Fast Placement

Presented by: Mahdi ElghazaliCourse: Reconfigurable Computing Systems

April 5, 2007 Winter 2007

Resource

Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS’04)

Authors: Manish Handa and Ranga Vemuri. Department of ECECS, University of

Cincinnati.

OUTLINE

Introduction Model of a Partially Reconfigurable Dynamic

System. Serial Architecture. Parallel Architecture. Serial-Parallel Architecture. Results. Conclusion. Paper Evaluation.

Introduction

Placement is one of the most time consuming steps in an computer aided design (CAD) environment.

In ROS more than one application may execute on the same FPGA.

The application is divided into tasks that are placed on FPGA using partial reconfiguration.

In a dynamically reconfigurable systems, the sequence of tasks is known at run time.

a placement engine is required to place each subsequent task while the application is running (at run-time). Such a placement paradigm is called online placement.

Model of a Partially Reconfigurable Dynamic System

Model of a Partially Reconfigurable Dynamic System The host:

Online placement. Controls the execution of the tasks on the

FPGA. Maintains the clock and other global signal.

FPGA: Application area.. Operating system (OS) area.

Serial Architecture

1. FPGA modeling:• The FPGA surface was modeled as a two

dimensional array called area matrix.• Each cell in the array represents a CLB in

the FPGA.• A weight of 0 for every occupied cell.• Figure 2 shows an example of the area

matrix of a FPGA with three tasks placed on it.

FPGA modeling

Serial Architecture

2. Deign Details:

Deign Details

The area matrix is stored in a memory on a row-by-row basis.

The height and the width of the task are stored in macro height and macro width registers.

An up-counter is used to address the memory.

Run-time Performance and Overhead

The worst case run time =

Total memory requirement=

Main overhead of this architecture is the time taken for host to write the area matrix in the shared memory.

Parallel Architecture

1. FPGA modeling:• A weight of 0 for occupied cells and a weight

of 1 for empty cells.

Deign Details

Consist of three main component: Area matrix. Reconfigurable adder. Parallel comparator.

Deign Details

1. Area matrix: One data word of the area matrix memory holds one full

column of the area matrix. The area matrix memory can easily be implemented using

look-up tables (LUTs) in the FPGA. The area matrix memory has height of 64 and width of 2

CLBs.

Deign Details

2. Reconfigurable adder: Height of the reconfigurable adder is equal to height of the

FPGA Rf and its width is equal to width of the task Wt. Consume Rf * (Wf+1) FF and Rf * (Wf-1) LUTs.

Deign Details

Deign Details

3. Parallel comparator: Consists of two stages.

Run-time Performance and Overhead

The worst case run time =

Total memory requirement=

Partial reconfiguration is the main overhead of the parallel architecture.

Serial-Parallel Architecture

1. Design details:• Accumulator

Run-time Performance and Overhead

The worst case run time =

Total memory requirement=

the execution time of the serial-parallel architecture is higher than the other two architectures.

Results

The circuit was tested on Xilinx Virtex XCV1000 FPGA. The Placement engine was implemented for an 64 CLB high and 96

CLB wide FPGA. 25 X 25 takes was used.

Conclusion

Three hardware architectures for chip-based two dimensional online placement were presented.

Table 2 shows a comparison between the three architectures.

Paper Evaluation

Pros Some examples was to explain the

functionality of some parts of the circuit. Good description about the first two

architecture was given. Cons:

They did not give enough information about the last architecture.

Some information was not clear.

Q & A

Thank you