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Reconfigurable Computing
Reconfigurable Architectures
Chapter 3.1
Prof. Dr.Ing. Jrgen Teich
Lehrstuhl fr HardwareSoftwareCoDesign
Reconfigurable Computing
Early Work
Reconfigurable Computing
Gerald Estrin FixPlus Machine
Vision of a restructurable computer system
Pragmatic problem studies predict gains in computation
speeds in a variety of computational tasks when executed
on appropriate problemoriented configurations of the
variable structure computer. The economic feasibility of
the system is based on utilization of essentially the same
hardware in a variety of special purpose structures. This
capability is achieved by programmed or physical
restructuring of a part of the hardware.
G. Estrin, B. Bussel, R. Turn, J Bibb (UCLA 1963)
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Gerald Estrin FixPlus Machine
Fixed plus Variable
structure computer Proposed by G. Estrin in 1959
Consist of three parts A high speed general purpose
computer (the fix part F).
A variable part (V) consisting of various size high speed digital substructureswhich can be reorganized in problemoriented special purpose configurations.
The supervisory control (SC) coordinates operations between the fix module and the variable module.
Speed gain over IBM7090 (2.5 to 1000)
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Source: G. Estrin et al., Parallel Processing in a
Restructurable Computer System, IEEE
Transactions on Electronic Computers,
vol 12, no 5, pp. 747755, 1963.
Gerald Estrin FixPlus Machine
The Fixed Part (F) Was initially an IBM 7090, but could be any general purpose computer
The Variable Part (V) Made upon a set of problemspecific optimized functional units in the
basic configuration (trigonometric functions, logarithm, exponentials, nth
power, roots, complex arithmetic, hyperbolic, matrix operation)
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Two types of basic building blocks The first basic element contains four
amplifiers and associated input logic for signal inversion, amplification, or highspeed storage
The second basic block consists of ten diodes and four output drivers and is for combinatoric application
The basic blocks
Source: G. Estrin et al., Parallel Processing in a
Restructurable Computer System, IEEE Transactions
on Electronic Computers, vol 12, no 5, pp. 747755, 1963.
Gerald Estrin FixPlus Machine
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*The mother board
*The wiring harness
The basic modules can be inserted into any of 36 positions on a mother board.
The connection between the modules is
established through a wiring harness
Function Reconfiguration means changing
some modules
Routing Reconfiguration means changing
parts of the wiring harness
*Source: G. Estrin et al., Parallel Processing in a
Restructurable Computer System, IEEE Transactions
on Electronic Computers, vol 12, no 5, pp. 747755, 1963.
Gerald Estrin FixPlus Machine
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Estrin at work.
Substantial effort on
manual reconfiguration
Source: C. Bobda, Introduction to Reconfigurable Computing, Springer, 2007.
The Rammig Machine
Goal
Investigation of a system, which, with no manual or
mechanical interference, permits the building, changing,
processing and destruction of real (not simulated) digital
hardware
Franz J. Rammig (University of Dortmund 1977)
The concept resulted in the construction of a
hardware editor
Useful to observe a circuit under test
(Hardware Emulation)
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The Rammig Machine
Implementation Outputs of modules connected to
selectors and selector outputs connected to module inputs.
Softwarecontrolled module interconnection
Two main problems to solve: Because the circuit is not hardwired, a
distortion of the behaviour is possible during reconfiguration
The timing is controlled by the circuit instead of being dictated by an observation mechanism
A timecontrol must therefore be provided by delay circuits and inertialdelay circuits
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9
Source: F.J. Rammig, A concept for the editing of
hardware resulting in an automatic hardwareeditor,
Design Automation Conference, pp. 187193, 1977.
Programmable Logic
Reconfigurable Computing
PALs and PLAs
Prefabricated building block of many AND/OR gates (or NOR, NAND)
"Personalized" by making or breaking connections between the gates
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Programmable Array Block Diagram for Sum of Products Form
Inputs
Dense array of AND gates Product
terms
Dense array of OR gates
Outputs
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Example:
Equations
Personality Matrix
Key to Success: Shared Product Terms
1 = asserted in term0 = negated in term = does not participate
1 = term connected to output0 = no connection to output
Input Side:
Output Side:
Reuse of
terms
F 1 1
0
1
0
0
Outputs Inputs Product t erm A
1

1

1
B
1
0

0

C

1
0
0

F 0 0
0
0
1
1
F 2 1
0
0
1
0
F 3 0
1
0
0
1
A B
B C
A C
B C
A
F0 = A + B CF1 = A C + A BF2 = B C + A BF3 = B C + A
PALs and PLAs
PALs and PLAs
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Example Continued  Unprogrammed device
All possible connections are availablebefore programming
A B C
F0 F1 F2 F3
PALs and PLAs
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Example Continued Programmed part Unwanted connections are "blown"
Note: some array structureswork by making connectionsrather than breaking them
A B C
F0 F1 F2 F3
AB
BC
AC
BC
A
PALs and PLAs
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Alternative representation for high fanin structures
Shorthand notationso we don't have todraw all the wires!
x at junction indicatesa connection
Notation for implementation
F0 = A B + A B
F1 = C D + C D
A B C D
AB+AB CD+CD
AB
CD
CD
AB
Unprogrammed device
Programmed device
PALs and PLAs
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Design Example
F1 = A B C
F2 = A + B + C
F3 = A B C
F4 = A + B + C
F5 = A B C
F6 = A B C
Multiple functions of A, B, C
F1 F2 F3 F4 F5 F6
ABC
A
B
C
A
B
C
ABC
ABC
ABC
ABC
ABC
ABC
ABC
A B C
PALs and PLAs
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What is difference between Programmable Array Logic (PAL) andProgrammable Logic Array (PLA)?
PAL concept implemented by Monolithic MemoriesAND array is programmable, OR array is fixed at fabrication
A given column of the OR arrayhas access to only a subset ofthe possible product terms
PLA concept Both AND and OR arrays are programmable
PALs and PLAs
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Design Example: BCD to Gray Code Converter
Truth Table
Kmaps
Minimized Functions:
A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
W 0 0 0 0 0 1 1 1 1 1 X X X X X X
X 0 0 0 0 1 1 0 0 0 0 X X X X X X
Y 0 0 1 1 1 1 1 1 0 0 X X X X X X
Z 0 1 1 0 0 0 0 1 1 0 X X X X X X
AB
CD 00 01 11 10
00
01
11
10
D
B
C
A
0 0 X 1
0 1 X 1
0 1 X X
0 1 X X
Kmap for W
AB
CD 00 01 11 10
00
01
11
10
D
B
C
A
0 1 X 0
0 1 X 0
0 0 X X
0 0 X X
Kmap for X
AB
CD 00 01 11 10
00
01
11
10
D
B
C
A
0 1 X 0
0 1 X 0
1 1 X X
1 1 X X
Kmap for Y
AB
CD 00 01 11 10
00
01
11
10
D
B
C
A
0 0 X 1
1 0 X 0
0 1 X X
1 0 X X
Kmap for Z
W = A + B D + B CX = B CY = B + CZ = A B C D + B C D + A D + B C D
PALs and PLAs
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Programmed PAL:
4 product terms per each OR gate
Minimized Functions:
W = A + B D + B CX = B CY = B + CZ = A B C D + B C D + A D + B C D
A B C D
A B C D
A
BD
BC
0
0
0
0
B
C
0
0
BC
BCD
AD
BCD
W X Y Z
W = A + B D + B CX = B CY = B + CZ = A B C D + B C D + A D + B C D
Complex Programmable Logic Devices
Complex PLDs (CPLD) typically combine PAL combinational logic with Flip Flops
Organized into logic blocks connected in an interconnect
matrix
Combinational or registered output
Usually enough logic for simple counters, state