1 - cpre 583 (reconfigurable computing): reconfigurable computing architectures iowa state...

1 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames)

Reconfigurable Architectures• Forces that drive a Reconfigurable Architecture

– Price• Mass production 100K to millions• Experimental 1 to 10’s

– Granularity of reconfiguration• Fine grain• Course Grain

– Degree of system integration/coupling• Tightly• Loosely

All are a function of the application that will run on the Architecture


Example Points in (Price,Granularity,Coupling) Space

Price

$100’s

$1M’s

Granularity

Coarse

Fine

CouplingLoose Tight

Intel /AMD

Int

float

RFU

Processor

PC

ML507

Ethernet

Decode

Exec

Store


What’s the point of a Reconfigurable Architecture

• Performance metrics– Computational

• Throughput• Latency

– Power• Total power dissipation• Thermal

– Reliability• Recovery from faults

Increase application performance!


Typical Approach for Increasing Performance

• Application/algorithm implemented in software– Often easier to write an application in software

• Profile application (e.g. gprof)– Determine where the application is spending its time

• Identify kernels of interest– e.g. application spends 90% of its time in function

matrix_multiply()• Design custom hardware/instruction to accelerate kernel(s)

– Analysis to kernel to determine how to extract fine/coarse grain parallelism (does any parallelism even exist?)

Amdahl’s Law!


Granularity


Granularity: Coarse Grain

• rDPA: reconfigurable Data Path Array• Function Units with programmable interconnects

ALU ALU ALU

ALU ALU ALU

ALU ALU ALU

Example




ALU ALU ALU

ALU ALU ALU

ALU ALU ALU

Example


Granularity: Fine Grain

• FPGA: Field Programmable Gate Array• Sea of general purpose logic gates

CLB CLB CLB CLB

CLB CLB CLB CLB

CLB CLB CLB CLB

CLB CLB CLB CLB

Configurable Logic Block




CLB CLB CLB

CLB CLB CLB CLB

CLB CLB CLB CLB

CLB CLB CLB CLB





CLB CLB

CLB

CLB

CLB CLB CLB CLB



Granularity: Trade-offsTrade-offs associated with LUT size

Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits)1024-bits

1024-bits

2-LUT

10-LUTMicroprocessor




1024-bits

2-LUT


4

3

3

AB

op3




1024-bits

2-LUT


4

3

3

AB

op3

4

3

3AB

op3

4

3

3

AB

op3




1024-bits

2-LUT


4

3

3

AB

op

3

4

3

3AB

op

3

3

3

3

AB

op




1024-bits

2-LUT


4

3

3

AB

op

3

4

3

3AB

op

3

4

3

3

AB

op

3




1024-bits

2-LUT

10-LUT

Bit logic and constants




1024-bits

2-LUT

10-LUT


(A and “1100”) or (B or “1000”)




1024-bits

2-LUT

10-LUT


(A and “1100”) or (B or “1000”)

A

B




1024-bits

2-LUT

10-LUT


(A and “1100”) or (B or “1000”)

A AND

OR

OR

1

0

B

4

4

It’s much worse, each 10-LUT only has one output

Area that wasrequired using

2-LUTS


Granularity: Example Architectures

• Fine grain: GARP

• Course grain: PipeRench


Granularity: GARP

CPU RFU

Garp chip

Memory

I-cache D-cache

Configcache


Granularity: GARP

CPU RFU

Garp chip

Memory

I-cache D-cache

Configcache

RFUcontrol

(1)Execution(16, 2-bit)

N

PE (Processing Element)


Granularity: GARP

CPU RFU

Garp chip

Memory

I-cache D-cache

Configcache

RFUcontrol


N

PE (Processing Element)Example computations in one cycleA<<10 | (b&c)(A-2*b+c)


Granularity: GARP

CPU RFU

Garp chip

Memory

I-cache D-cache

Configcache

Impact of configuration size• 1 GHz bus frequency•128-bit memory bus• 512Kbits of configuration size

On a RFU context switch how longto load a new full configuration?

4 microseconds

An estimate of amount of time for theCPU perform a context switch is ~5 microseconds

~2x increase context switch latency!!


Granularity: GARP

CPU RFU

Garp chip

Memory

I-cache D-cache

Configcache

RFUcontrol


N

PE (Processing Element)

“The Garp Architecture and C Compiler”http://www.cs.cmu.edu/~tcal/IEEE-Computer-Garp.pdf


Granularity: PipeRench • Coarse granularity

• Higher (higher) level programming

• Reference papers• PipeRench: A Coprocessor for Streaming Multimedia Acceleration

(ISCA 1999): http://www.cs.cmu.edu/~mihaib/research/isca99.pdf• PipeRench Implementation of the Instruction Path Coprocessor

(Micro 2000): http://class.ee.iastate.edu/cpre583/papers/piperench_Micro_2000.pdf


Granularity: PipeRench

Interconnect

8-bit ALU

Reg file

PE8-bit ALU

Reg file

PE8-bit ALU

Reg file

PE

Interconnect

8-bit ALU

Reg file

PE8-bit ALU

Reg file

PE8-bit ALU

Reg file

PE

8-bit ALU

Reg file

PE8-bit ALU

Reg file

PE8-bit ALU

Reg file

PE

Glo

bal b

us



PE PE PEPE

PE PE PEPE

PE PE PEPE

Cycle

Pipelinestage

1 2 3 4 5 6

0

1

2

3

4



PE PE PEPE

PE PE PEPE

PE PE PEPE

0

Cycle

Pipelinestage

1 2 3 4 5 6

0

1

2

3

4



PE PE PEPE

PE PE PEPE

PE PE PEPE

0

Cycle

Pipelinestage

1 2 3 4 5 6

0

1

2

3

4

0

1



PE PE PEPE

PE PE PEPE

PE PE PEPE

0

Cycle

Pipelinestage

1 2 3 4 5 6

0

1

2

3

4

0

1

0

1

2



PE PE PEPE

PE PE PEPE

PE PE PEPE

0

Cycle

Pipelinestage

1 2 3 4 5 6

0

1

2

3

4

0

1

0

1

2

1

2

3



PE PE PEPE

PE PE PEPE

PE PE PEPE

0

Cycle

Pipelinestage

1 2 3 4 5 6

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1

2

3

4

0

1

0

1

2

1

2

3

2

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4



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Degree of Integration/Coupling • Independent Reconfigurable Coprocessor

– Reconfigurable Fabric does not have direct communication with the CPU

• Processor + Reconfigurable Processing Fabric– Loosely coupled on the same chip– Tightly coupled on the same chip


Degree of Integration/Coupling M

ain M

emory

CPU

Fe

tch

De

code

Execute Me

mory

Write

Back

L1 Cache

L2 Cache

MemoryController

DMAController

I/OController

USB PCI PCI-Express SATA

Hard DriveNIC

ALU

FPU



ain M

emory

CPU

Fe

tch

De

code

Execute Me

mory

Write

Back

L1 Cache

L2 Cache

MemoryController

DMAController

I/OController


Hard DriveNIC

ALU

FPU

RPF



ain M

emory

CPU

Fe

tch

De

code

Execute Me

mory

Write

Back

L1 Cache

L2 Cache

MemoryController

DMAController

I/OController


Hard DriveNIC

ALU

FPURPF



ain M

emory

CPU

Fe

tch

De

code

Execute Me

mory

Write

Back

L1 Cache

L2 Cache

MemoryController

DMAController

I/OController


Hard DriveNIC

ALU

FPU

RPF

ConfigI/F



ain M

emory

CPU

Fe

tch

De

code

Execute Me

mory

Write

Back

L1 Cache

L2 Cache

MemoryController

DMAController

I/OController


Hard DriveNIC

ALU

FPU

RPFI/O

ConfigI/F



ain M

emory

CPU

Fe

tch

De

code

Execute Me

mory

Write

Back

L1 Cache

L2 Cache

MemoryController

DMAController

I/OController


Hard DriveNIC

ALU

FPURFU


Next Class

• Reconfiguration Management– Chapter 4


Questions/Comments/Concerns

• Write down– Main point of lecture

– One thing that’s still not quite clear

– If everything is clear, then give an example of how to apply something from lecture

OR


Lecture notes



• Scheduling virtual stage on to physical• Partial/Dynamically reconfig (each cycle)


Granularity: GARP

• Impact of configuration size on performance• Context switching

• Garp feature• Dynamic reconfigurable• Store multiple configurations in an on chip

cache (4)• One configuration at a time

• Example app mapping to GARP (loop)• Amdahl's Law

The Garp Architecture and C Compiler• http://www.cs.cmu.edu/~tcal/IEEE-Computer-Garp.pdf


Overview• Dimensions

– Price– Granularity– Coupling– To optimize App Performance (compute (throughput, latency),

Power, reliability)• RPF to efficiently implement VICs

– Main picture authors' wants to convey• What’s the point or having a Reconfigure arch

– Example (Increase App performance)• App -> SW/CPU• Profile• ID kernels of intense compute• Design custom hardware/instruction (Amdels law)

– Intel FPL paper, great example for reading by Friday


Reconfigurable Architectures• RPF -> VIC (short slide)

1 - cpre 583 (reconfigurable computing): reconfigurable computing architectures iowa state...

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