overview slides before midterm exam

EE 534 Summer 2004 University of South Alabama

Overview slides beforemidterm exam


64

256

1,000

4,000

16,000

64,000

256,000

1,000,000

4,000,000

16,000,000

64,000,000

10

100

1000

10000

100000

1000000

10000000

100000000

1980 1983 1986 1989 1992 1995 1998 2001 2004 2007 2010

Year

Kbit

capa

city

/chi

p

Evolution in DRAM Chip Capacity

1.6-2.4 m

1.0-1.2 m

0.7-0.8 m

0.5-0.6 m

0.35-0.4 m

0.18-0.25 m

0.13 m

0.1 m

0.07 m

human memoryhuman DNA

encyclopedia2 hrs CD audio30 sec HDTV

book

page

4X growth every 3 years!


Die Size Growth

40048008

80808085

8086286

386486 Pentium ® proc

P6

1

10

100

1970 1980 1990 2000 2010Year

Die

siz

e (m

m)

~7% growth per year~2X growth in 10 years

Die size grows by 14% to satisfy Moore’s Law

Courtesy, Intel


Clock Frequency

Lead microprocessors frequency doubles every 2 years

P6Pentium ® proc

48638628680868085

8080800840040.1

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Freq

uenc

y (M

hz)

2X every 2 years

Courtesy, Intel


Power Dissipation

P6Pentium ® proc

486386

2868086

808580808008

4004

0.1

1

10

100

1971 1974 1978 1985 1992 2000Year

Pow

er (W

atts

)Lead Microprocessors power continues to increase

Courtesy, Intel

Power delivery and dissipation will be prohibitive


Power Density

400480088080

8085

8086

286 386486

Pentium® procP6

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Pow

er D

ensi

ty (W

/cm

2)

Hot Plate

NuclearReactor

RocketNozzle

Courtesy, Intel


Why Scaling?

Technology shrinks by ~0.7 per generation

With every generation can integrate 2x more functions on a chip; chip cost does not increase significantly

Cost of a function decreases by 2x

But … How to design chips with more and more functions? Design engineering population does not double every two years…

Hence, a need for more efficient design methods Exploit different levels of abstraction


Design Abstraction Levels

n+n+S

GD

+

DEVICE

CIRCUIT

GATE

MODULE

SYSTEMBehavior description(Verilog, HDL, etc.)Silicon compilation

Physical description(layout, circuit, etc.)

Simulation for system specification


Major Design Challenges Microscopic issues

ultra-high speeds power dissipation and

supply rail drop growing importance of

interconnect noise, crosstalk reliability,

manufacturability clock distribution

Macroscopic issues time-to-market design complexity

(millions of gates) high levels of

abstractions reuse and IP, portability systems on a chip (SoC) tool interoperability

Year Tech. Complexity Frequency 3 Yr. Design Staff Size

Staff Costs

1997 0.35 13 M Tr. 400 MHz 210 $90 M1998 0.25 20 M Tr. 500 MHz 270 $120 M1999 0.18 32 M Tr. 600 MHz 360 $160 M2002 0.13 130 M Tr. 800 MHz 800 $360 M


Why learn full hierarchy? somebody has to do it at each level

good design of cell or modules requires in-depth knowledge

stringent constraints

vertical knowledge in horizontally integrated companies

global factors (interconnect for power, ground, clock, bus, etc.)

new issues previously considered not critical: dynamic power dissipation interconnect delay and coupling many other “surprises” waiting ahead!!!

Murphy’s law (when things can go wrong, they do) comes again and again.


Course overview: VLSI design

Job of VLSI designer: design a circuit block to meet one or more objectives:

Maximize speed, performance Minimize power consumption Minimize area Noise immunity (robustness)

How? Choice of circuit style (static, dynamic, etc) Circuit design, transistor sizing Interconnect design, efficient layout


VLSI Design Stages Logic Design/Simulation

Partition architecture into cycles / latches Verify against architecture specification

Circuit Design/Simulation Transistor sizing Performance verification

Static Timing Analysis Verify margin requirements

Physical Design Draw masks for layout, following design rules Placement and routing Parasitic extraction


VLSI Design Approaches

Gate Arrays Prefabricated chips containing transistors/gates and

local interconnects Upper level wires added to implement design Quick, but sub-optimal

Standard Cells Cells in a library with fixed height, width Cells characterized for delay, power Design is fast – layout mostly automatic

Custom Design Variable sizes Extensive checking / verification required Dense design, best performance Performance

Ease of Design


Design Rules

Interface between the circuit designer and process engineer

Guidelines for constructing process masks

Unit dimension: minimum line width scalable design rules: lambda parameter absolute dimensions: micron rules

Rules constructed to ensure that design works even when small fab errors (within some tolerance) occur

A complete set includes set of layers intra-layer: relations between objects in the same layer inter-layer: relations between objects on different layers

is half of the minimum feature size in a given process (e.g., min. gate length).


The Threshold Voltage

VT = VT0 + (|-2F + VSB| - |-2F|)

where

VT0 is the threshold voltage at VSB = 0 and is mostly a function of the manufacturing process

Difference in work-function between gate and substrate material, oxide thickness, Fermi voltage, charge of impurities trapped at the surface, dosage of implanted ions, etc.

VSB is the substrate-bias voltage

F = -Tln(NA/ni) is the Fermi potential (T = kT/q = 26mV at 300K is the thermal voltage; NA is the acceptor ion concentration; ni 1.5x1010 cm-3 at 300K is the intrinsic carrier concentration in pure silicon)

= (2qsiNA)/Cox is the body-effect coefficient (impact of changes in VSB) (si=1.053x10-10F/m is the permittivity of silicon; Cox = ox/tox is the gate oxide capacitance with ox=3.5x10-11F/m)


MOSFET Current –Voltage Relationships (Non saturation Region)

The region for which VDS< VDS(sat) is known as the nonsaturation region. The ideal current voltage characteristics in this region are describe by the equation

iD= Kn[(VGS-VTN)VDS-VDS2/2]

Where the parameter Kn is called the conduction parameter or gain factor for the n-channel device and is given by

Kn= nCoxW/L

Where Cox is the oxide capacitance per unit area. The capacitance is given by

Cox= ox/tox

Where tox is the oxide thickness and ox is the oxide permittivity. The parameter n is the mobility of the electron in the inversion layer.


MOSFET Current –Voltage Relationships (Saturation Mode)

In saturation mode VDS ≥ VGS-Vt . The expression for saturation mode

can be obtained by substituting VDS = VGS-Vt resulting in

iD (Sat)= Kn/2(VGS-VTN)2

This expression indicates that the saturation drain current has no dependence on VDS.


Process Tranconductance parameter

It is to be noted that in the above expressions the parameter nCox is a constant determined by the processing technology used to fabricate the MOS technology. It is known as the process transconductance parameter, and is denoted by

K'n= nCox

We can rewrite the conduction parameter in the form,

Kn= K'nW/L

Transistor design variable.


Current Determinates

For a fixed VDS and VGS (> VT), IDS is a function of the distance between the source and drain – L the channel width – W the threshold voltage – VT

the thickness of the SiO2 – tox

the dielectric of the gate insulator (SiO2) – ox

the carrier mobility- for n: n = 500 cm2/ V-sec- for p: p = 180 cm2/ V-sec

iD= Kn[(VGS-VTN)VDS-VDS2/2]


Short-channel effects Short-channel device: channel length is

comparable to depth of drain and source junctions and depletion width In general, visible when L ~ 1m and

below

Short-channel effects: Carrier velocity saturation Mobility degradation Threshold voltage variation


Carrier velocity saturation

Electric field Ey exists along channel As channel length is reduced, electric field increases (if voltage is

constant)

Electron drift velocity vd is proportional to electric field only for small field values for large electric field, velocity saturates

source drain

Vds0 Vgs

N+N+

P

L


Effects of High fields Vertical field

The vertical field occurs in the y-direction from the gate to the channel (EY=VDD/tox

1980 1995 2001EY=5V/1000Ao =50 x 104V/cm EY=3.3.V/75Ao=4.4 x 106V/cm Ey=1.2V/22AO=5.5 x 106 V/cm

Horizontal field

The horizontal field occurs in the x-direction from the drain to the source (EY=VDS/L

1980 1995 2001Ex=5V/5m =104V/cm Ex=3.3.V/0.35m=9.4 x 104V/cm Ex=1.2V/0.1m=1.2 x 105 V/cm


Carrier velocity saturation Effect of velocity saturation:

Current saturates before “saturation region” VDSAT = voltage at which saturation occurs Drain current is reduced:

)()()( 21

DSATTGSoxdD VVVCsatWvsatI

(no longer quadratic function of VGS)

Saturation region is extended: VDSAT < VGS-VT


Velocity Saturation Effects

0

10

Long channel devices

Short channel devices

VDSAT VGS-VT

VDSAT < VGS – VT so the device enters saturation before VDS reaches VGS – VT and operates more often in saturation

For short channel devices and large enough VGS – VT

IDSAT has a linear dependence wrt VGS so a reduced amount of current is delivered for a given control voltage

VGS = VDD


MOS ID-VGS Characteristics

0123456

0 0.5 1 1.5 2 2.5VGS (V)

I D ( A

)

long-channel quadratic

short-channel linear

Linear (short-channel) versus quadratic (long-channel) dependence of ID on VGS in saturation

Velocity-saturation causes the short-channel device to saturate at substantially smaller values of VDS resulting in a substantial drop in current drive

(for VDS = 2.5V, W/L = 1.5)

X 10-4


Short-channel and long channel comparison

Both devices have same effective W/L ratio I/V curves should be similar

Short-channel device has ~ 40% less current at high VDS

Note linear dependence on VGS in short-channel device

Long-channel Short-channel


Threshold voltage variation

Until now, threshold voltage assumed constant VT changed only by substrate bias VSB

In threshold voltage equations, channel depletion region assumed to be created by gate voltage only

Depletion regions around source and drain neglected: valid if channel length is much larger than depletion region depths

In short-channel devices, depletion regions from drain and source extend into channel


Threshold voltage variationShort-channel effects cause threshold voltage

variation:

VT roll off As channel length L decreases, threshold

voltage decreases

Drain-induced barrier lowering As drain voltage VDS increases, threshold

voltage decreases

Hot-carrier effect Threshold voltages drift over time


Source depletion region

Drain depletion region

Gate-induced depletion region


Even with VGS=0, part of channel is already depleted

Bulk depletion charge is smaller in short-channel device → VT is smaller

N+ source

N+ drain


Threshold voltage variation Change in VT0:

xdS, xdD: depth of depletion regions at S, D xj: junction depth

121121

2221

0j

dD

j

dSjFASi

oxT x

xxx

Lx

NqC

V

VT0 is proportional to (xj/L)– For short channel lengths, VT0 is large– For large channel lengths, term approaches 0


Threshold voltage variationsGraphically: VT0 versus channel

length L

VTVT

Low VDS threshold

VDS

VT Roll-off:VT decreases rapidly with channel length

VT0

L

Long-channel VT

Lnom

Threshold as a function ofAs a function of length (for low VDS)

Drain-induced barrier lowering(for low L)



Hot-carrier effect increased electric fields causes

increased electron velocity high-energy electrons can tunnel into

gate oxide This changes the threshold voltage

(increases VT for NMOS) Can lead to long-term reliability

problems


Threshold voltage variation Hot electrons

High-velocity electrons can also impact the drain, dislodging holes

Holes are swept towards negatively-charged substrate → cause substrate current-

Called impact ionization This is another factor which limits the

process scaling → voltage must scale down as length scales


Sources of Capacitance

Cw

CDB2

CDB1

CGD12

CG4

CG3

wiring (interconnect) capacitance

intrinsic MOS transistor capacitances

Vout2Vin

extrinsic MOS transistor (fanout) capacitances

Vout

VoutVin

M2

M1

M4

M3

Vout2

CL


MOS Intrinsic Capacitances

Structure capacitances (oxide capacitance)

Channel capacitances

Depletion regions of the reverse-biased pn-junctions of the drain and source


MOS Structure Capacitances (oxide)

Overlap capacitances gate electrode overlaps source and drain regions XD is overlap length on each side of channel Leff = Ldrawn – 2LD

Total overlap capacitance:

Ld

Sourcen+

Drainn+W

Ldrawn

Ld

Poly Gate

n+n+tox

Leff

Top view

lateral diffusion

DoxGDOGSOO WLCCCC 2


Channel capacitances Gate-to-source: Ggs

Gate-to-drain: Ggd

Gate-to-bulk: Ggb

Cutoff: No channel connecting source and drain Cgs = Cgd = 0 Cgb = CoxWLeff Total channel capacitance CC = CoxWLeff

source drainCgb

CgdCgs

MOS Channel Capacitances


Gate capaciatnce- an example CC = CoxWLeff=WCg

Cg=CoxLeff

Cg=Eox/tox(L)=(4)(8.85 x 10-14)/(1100Ao)(5m)=1.6fF/m)

Cg=Eox/tox(L)=(4)(8.85 x 10-14)/(75Ao)(0.35m)=1.6fF/m)

Cg=Eox/tox(L)=(4)(8.85 x 10-14)/(22Ao)(0.1m)=1.6fF/m)

This factor has reminded constant for over 25 years!


MOS Channel Capacitances Linear mode

Channel spans from source to drain

Capacitance split equally between S and D

effoxGS WLCC21

effoxGD WLCC21

– Total channel capacitance CC = CoxWLeff

0GBCThe body electrode is shielded from the gate by the channel


MOS Channel Capacitances Saturation mode

Channel is pinched off:

effoxGS WLCC320GDC 0GBC

–Total channel capacitance CC = 2/3 CoxWLeff


Simulated Wire Delays

0

0.5

1

1.5

2

2.5

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

vol ta

ge (V

0)

time (nsec)

Vin Vout

L

L/10 L/4 L/2 L


Overcoming Interconnect Resistance Selective technology scaling

scale W while holding H constant

Use better interconnect materials lower resistivity materials like copper

- As processes shrink, wires get shorter (reducing C) but they get closer together (increasing C) and narrower (increasing R). So RC wire delay increases and capacitive coupling gets worse.

- Copper has about 40% lower resistivity than aluminum, so copper wires can be thinner (reducing C) without increasing R

use silicides (WSi2, TiSi2, PtSi2 and TaSi)- Conductivity is 8-10 times better than poly

alone

n+n+

SiO2

polysilicon

silicide

p Use more interconnect layers

reduces the average wire length L (but beware of extra contacts)


CMOS Inverter VTC

0

0.5

1

1.5

2

2.5

0 0.5 1 1.5 2 2.5

Vin (V)

Vou

t (V

)

NMOS offPMOS res

NMOS satPMOS res

NMOS satPMOS sat

NMOS resPMOS sat NMOS res

PMOS off

VDD

Vout

CL


CMOS inverter design consideration

The CMOS inverter usually design to have, (i) VTN =|VTP|(ii) K´n(W/L)=K´p(W/L)

But K´n> K´p (because n>p)How equation (ii) can be satisfied?This can be achieved if width of the PMOS is made

two or three times than that of the NMOS device. This is very important in order to provide a symmetrical VTC, results in wide noise margin.


VCC

VCC

Vin

Vout

kp=kn

kp=5kn

kp=0.2kn

• Increase W of PMOS kp increases VTC moves to right

• Increase W of NMOS kn increases VTC moves to left

• For VTH = Vcc/2 kn = kp

Wn 2Wp

CMOS inverter design consideration (cont.)


Effects of Vth adjustment Result from changing kp/kn ratio:

Inverter threshold VTH Vcc/2 Rise and fall delays unequal Noise margins not equal

Reasons for changing inverter threshold Want a faster delay for one type of

transition (rise/fall) Remove noise from input signal:

increase one noise margin at expense of the other


Example:


Calculation of Delay times: Average current method

HLavg

OHload

HLavg

HLloadPHL I

VVCI

VC,

)(,

. %50

LHavg

OLload

LHavg

LHloadPLH I

VVCI

VC,

)(,

. %50

The average current during high to low transition can be calculated by using the current values at the beginning and the end of the transition.

),(),(21, %50VVVVIVVVVinII outOHinCOHoutOHCHLavg

),(),(21, %50 OLoutOLinCoutOLinCLHavg VVVVIVVVVII

The average current during low to high transition can be calculated by using the current values at the beginning and the end of the transition.


Inverter delay, falling Total fall delay =

(t1-t0) + (t2-t1)

1)(4

ln2

)(,0

,0

,0

,0 OLOH

nTOH

nTOH

nT

nTOHn

LPHL VV

VVVV

VVVk

Ct


Inverter delay, rising Similar calculation as for falling delay

Separate into regions where PMOS is in linear, saturation

1

)(4ln

2)(

,0

,0

,0

,0 OLOH

pTOLOH

pTOLOH

pT

pTOLOHp

LPLH VV

VVVVVV

VVVVk

Ct


Example 6.2


Propagation delay of simple lumped RC network

For fall delay tphl, V0=Vcc, V1=Vcc/2

Lpplh

Lnphl

p

CC

CCp

CRt

CRt

RCt

VV

RCVVRCt

69.0

69.0

)5.0ln(

lnln 21

0

1

Standard RC-delay equations


Review: Designing Inverters for Performance Reduce CL

internal diffusion capacitance of the gate itself interconnect capacitance fanout

Increase W/L ratio of the transistor the most powerful and effective performance optimization tool

in the hands of the designer

Increase VDD only minimal improvement in performance at the cost of

increased energy dissipation

Slope engineering - keeping signal rise and fall times smaller than or equal to the gate propagation delays and of approximately equal values

good for performance good for power consumption

overview slides before midterm exam

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