onfi 3.0 nand flash controller
DESCRIPTION
The Arasan ONFI 3.0 compliant NAND Flash Controller IP Core is a full featured, easy to use, synthesizable design that is easily integrated into any SoC or FPGA development. Designed to support both SLC and MLC flash memories, it is flexible to use and implementTRANSCRIPT
Introducing the ONFI 3.0 NAND Flash Controller
By Dennis McCarty
©Arasan Chip Systems Inc. 2011
Arasan Chip Systems Total IP SolutionsONFI 3.0 FeaturesCore ArchitectureDeliverablesArasan Advantages
Arasan Total IP Solutions
©Arasan Chip Systems Inc. 2011
ONFI Background
ONFI Open NAND Flash Interface• NAND Flash Industry Consortium
Version 3.0• Latest specification for NAND Flash control• Faster data transfers and new features• Backwards compatible with previous versions
©Arasan Chip Systems Inc. 2011
Operates memory devices at any frequency up to 200 MHz
• 200 MT/S Differential signaling on clock and data lines
DDR-2 Transfers• True and Complement Data Strobes• SDR, NV-DDR and NV-DDR2
ONFI 3.0 Features
©Arasan Chip Systems Inc. 2011
ONFI 3.0 Features
Single and Dual data bus discoveryEight chip enablesPage sizes up to 8KECC up to 64 bits
• Dynamically configurable ECC widthWarm-up cycles for high-speed operationSupports all new commands
©Arasan Chip Systems Inc. 2011
Patented BCH Coding
BCH Coded ECC supports dynamically scalable correction bitsParallel bit processing on the BCH encoderParallel syndrome generationInversion-less Berlekamp-Massey algorithm for key equation solverParallel computation for the key equation solverParallel Chien search algorithm
©Arasan Chip Systems Inc. 2011
NAND Flash Architecture
©Arasan Chip Systems Inc. 2011
ONFI Compliance
Compliant to the 3.0 ONFI (rev. 2011)
Only announced product in the market
©Arasan Chip Systems Inc. 2011
Deliverables
RMM (Reuse Methodology Manual) compliant Verilog
Configurable Behavioral models
Verification Suite & Test Cases
Documentation and Design Support
©Arasan Chip Systems Inc. 2011
Features
• Analog and Digital cores, with no gaskets or wrappers for efficient, low-gate design
• Software, Synthesis scripts and Test Environments
• Verification IP, ESL models
• HW Development Kits & Verification Platforms
• Design Services
©Arasan Chip Systems Inc. 2011
Total IP Solutions
©Arasan Chip Systems Inc. 2011
Benefits• Compliance across the standard• Single supplier – Single support• Guaranteed compatibility• Lowest overall cost and risk• Seamless integration from PHY to SW layers• Fastest cycle: MRD to SoC
Total IP Solutions