lec6 memory flash nand

7/30/2019 Lec6 Memory Flash NAND

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NAND Flash Technology

[email protected]

Adapted from:Adapted from:11 Nonvolatile Memor Technolo ies with Em hasis on Flash edited b JoeNonvolatile Memor Technolo ies with Em hasis on Flash edited b Joe

E. Brewer, WileyE. Brewer, Wiley 20082008

[[22]] M.SanvidoM.Sanvido and et al., NAND Flash Memory and Its Role on Storageand et al., NAND Flash Memory and Its Role on StorageArcthitecturesArcthitectures,, Proceeding of IEEEProceeding of IEEE Vol.Vol.9696, No., No.1111, Nov, Nov 20082008


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NAND Flash

TopicTopic

Examples

-

NAND Application with HDD and SSD


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NAND Flash

OverviewOverview

of Tohoku University in 1987

Uses uniform FN tunnelin for both erasin andprogramming

Block-oriented memory

Easily programmed in a long page (order of 16kb) so theprogramming time per byte can be short

resistance of cells and select transistor

Suitable for applications that requires reading andprogramming blocks of data


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NAND Flash-Recap

NAND Structured CellNAND Structured Cell

connected between two

select transistor

Cell pitch defined by thepolysilicon wiring litho-

graphy thus easier forscaling


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NAND Flash

ArchitectureArchitecture


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NAND Flash

Ex:Ex: 6464 MbitMbit


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NAND Flash-Recap

EraseErase

allow inhibit

Over-erasure is of no concern


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NAND Flash

ProgramProgram

0-programchange to positive VT

1-programkeep negative VT0V 0V

Page operation

are programmed simultaneously

A l 20 V to a selected cell and 10 V to non-selected cells(which share the same BL and must operate as a pass gate)

Apply 0 V to BL for 0-programing ( change to positive VT)

ppy o or -programng eep nega ve


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NAND Flash

Ex: Program SchemeEx: Program Scheme


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NAND Flash

ReadRead

o er ce s excep e se ec e ce serve as passdevices


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NAND Flash

Array Structure and OperationsArray Structure and Operations

Use staggered-row decoder instead of sub row

pitch


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NAND Flash

Conventional StructureConventional Structure

Each row decoder occupies length of a NAND strings


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NAND Flash

Staggered Row DecoderStaggered Row Decoder

Each row decoder occupies length of two NANDstrin s


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NAND Flash

SelfSelf--booted Erase Inhibit Schemebooted Erase Inhibit Scheme

By floating CG andas ng -we , e

capacitive coupling

same amount as P-well.


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NAND Flash

Block EraseBlock Erase


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NAND Flash

SelfSelf--boosted Program Inhibit Schemeboosted Program Inhibit Scheme


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NAND Flash

Capacitive Model for SelfCapacitive Model for Self--boostedboosted


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NAND Flash

Program Page OperationProgram Page Operation


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NAND Flash

Read OperationRead Operation


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NAND Flash

Program DisturbProgram Disturb

VM should be set between 6 and 11 V.


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NAND Flash

Read/Write and Verify CircuitsRead/Write and Verify Circuits

(Write CG4 and operate at Supply = 3V)


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NAND Flash

Read/Write and Verify CircuitsRead/Write and Verify Circuits

(Read CG4 and operate at Supply = 3V)


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NAND Flash

VerifyVerify--readread010

001

111

101


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NAND Flash

Page Programming AlgorithmPage Programming Algorithm


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Flash-MLC

MultiMulti--Level CellLevel Cell

Improve memory density without increasing the

Lower cost per bit

ConCon

ompex program a gor ms an c rcu s

Increase access time


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Flash-MLC

Key RequirementsKey Requirements

Accurate control of the amount of charge stored, or placed,

on the floating gatePrecise control and timing of the voltages applied to the

cells

Accurate measurement of the transistor characteristics todetermine which charge level, or data bit, is stored

Advanced analog to digital conversion

Retention: Accurate charge storage, such that the charge level, or data

bit, remains intact over time


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NOR Flash MLC

Ex: IntelsEx: Intels StrataFlashStrataFlash (ETOX NOR)(ETOX NOR)

Charge difference between states in 1 b/c is roughly

30 000 electrons Distribution of 0.3 V corresponds to 3,000 electrons


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NOR Flash MLC

PlacementPlacement

Program timing control voltage and placement

O


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NOR Flash MLC

SensingSensing

fast decoding

Use flash cell togenerate referencefor better tracking

of process variationand operating

NAND Fl h MLC


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NAND Flash MLC

44--Level NANDLevel NAND

arge res o vo age s r u on

NAND Fl h MLC


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NAND Flash MLC

44--Level NAND : Page ReadLevel NAND : Page Read

The WSR scheme identifiesone o our eren ce s a esby sequentially changing the

NAND Fl h MLC


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NAND Flash MLC

44--Level NAND : Page ProgramLevel NAND : Page Program

NAND Fl h MLC


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NAND Flash MLC

33--Level NANDLevel NAND

NAND Flash MLC


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NAND Flash MLC

44--bit per Cellbit per Cell

Spansion (AMD) announced MirrorBit Quad

Using silicon nitride instead of conductive floating gate

Claimed as first industry 4-bit per cell Flash. Actually it is nota FG Flash, it is a NROM

20092009

SanDisk initiated shipments of X4

Made by Toshiba

43 nm process technology

Density 64Gb

NAND Flash


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NAND Flash

Architecture and PerformanceArchitecture and Performance

NAND Flash


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NAND Flash

Typical Raw ThroughputsTypical Raw Throughputs

Type Page Block Page/blc Erase(mS/blc)

Program

(S/p)

Write(MB/S)

Read(S/p)

- - -(64B)

. . .

2LC 4KB 512KB 128 3 600-900 3.8-5.4 50(218B)

[2]

Higher parallelism

Setup standard interfaces :ONFI (Open Nand Flash, ,

Applications with HDD


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Disk Caching ArchitectureDisk Caching Architecture

Add NAND flash as a disk cache to HDD

Looks as if there is firmware on HDD Data are not split into two separate physical units

Driver is needed on host side to manage NAND



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Use part of flash to permanently store some data such as

portion of boot data, initial portion of the hibernation file,requency use ran om a a or app ca ons

Use part of flash to temporary store incoming write datadurin the time that HDD does not s in to save owe

Advantages provide a faster boot up and improve resume time from

standby or hibernation

reduce power consumption by rotating media, thus

improve launch time for frequently used applications

improve the hard disk drive reliability, since the media canbe spun down most of the time



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Place NAND flash outside

of HDD (on MTB or as acard)

Split data into two physical

oca ons

Require software and driver

to mana e NAND and HDD

Advantages

Fast boot, fast resume Lower overall power consumption

Improve HDD reliability

HDD System Diagram


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HDD System Diagram

Source: Debasis BaralSource: Debasis BaralSamsung USASamsung USA

Solid-State Drive


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Solid State Drive

Inside SSDInside SSD

Source: Debasis BaralSource: Debasis BaralSamsung USASamsung USA

Solid-State Drive


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Solid State Drive

SSDSSD

Currently use SLC NAND Flash

-

Sequential read slower than HDD which achieves100MB s

Four to ten times slower than HDD on write access

Still some issues on endurance, data retention

design (average for 32/64 GB ~1-2 W)

NAND Flash


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NAND Flash

NANDNAND vsvs HDDHDD

Ref. J.Unsworth, Gartnet, Dataquest Insight: Solid-State Drive Emergein Select Consumer and Enterprise Markets, Jan 7, 2008

Limitations of Flash


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Limitations of Flash

Programming VoltageProgramming Voltage

Programming SpeedProgramming Speed

EnduranceEndurance

Little improvement, so far ~10

ScalingScaling

Limitation of Flash


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Fundamental Scaling LimitFundamental Scaling Limit

on retention time

Attem t to reduce ro rammin volta e has not etsuccessful

Good news: it can be scaled for more technology

generations before anticipated fundamental scalingissues become critical.

Limitation of Flash


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Ideal MemoryIdeal Memory

lec6 memory flash nand

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