microelectronics lab elct605 spring 2013 digital lab session #4 · 2013. 4. 7. · dr m. abd el...
TRANSCRIPT
Microelectronics LabELCT605
Spring 2013
Digital Lab Session #4
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IETELCT605 Lab Session #4 Spring 2013
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IETELCT605 Lab Session #4 Spring 2013
Outline
FPGA Complete Flow – Decoder Example
Task:
1. Download 4-bit Up-Counter with Enable on FPGA using
Switches for the inputs and LEDs for the outputs.
2. Show the name of one of your team members on the
Spartan 3E FPGA LCD Display.
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IETELCT605 Lab Session #4 Spring 2013
FPGA Complete Flow
entity Decoder2x4 is
port(E: in std_logic;
A0,A1: in std_logic;
D0,D1,D2,D3: out std_logic);
end Decoder2x4;
architecture Behavioral of Decoder2x4 is
begin
D3 <= E and A1 and A0;
D2 <= E and A1 and (not A0);
D1 <= E and (not A1) and A0;
D0 <= E and (not A1) and (not A0);
end Behavioral;
1. Write VHDL Code
2.Test and Simulation
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IETELCT605 Lab Session #4 Spring 2013
FPGA Complete Flow
3. Synthesize Design
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IETELCT605 Lab Session #4 Spring 2013
FPGA Complete Flow
4. Assign Inputs and Outputs Locations on Board
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IETELCT605 Lab Session #4 Spring 2013
FPGA Complete Flow
4. Assign Inputs and Outputs Locations on Board
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IETELCT605 Lab Session #4 Spring 2013
FPGA Complete Flow
4. Assign Inputs and Outputs Locations on Board
Enter the locations of the
inputs and outputs on the
FPGA Board
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IETELCT605 Lab Session #4 Spring 2013
FPGA Complete Flow
4. Assign Inputs and Outputs Locations on Board
Enter the locations of the
inputs and outputs on the
FPGA Board
Save
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IETELCT605 Lab Session #4 Spring 2013
FPGA Complete Flow
5. Implement Design
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IETELCT605 Lab Session #4 Spring 2013
FPGA Complete Flow
5. Configure FPGA Device
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IETELCT605 Lab Session #4 Spring 2013
FPGA Complete Flow
5. Configure FPGA Device
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IETELCT605 Lab Session #4 Spring 2013
FPGA Complete Flow
5. Configure FPGA Device
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IETELCT605 Lab Session #4 Spring 2013
FPGA Complete Flow
5. Configure FPGA Device
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IETELCT605 Lab Session #4 Spring 2013
FPGA Complete Flow
5. Configure FPGA Device
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IETELCT605 Lab Session #4 Spring 2013
FPGA Complete Flow
5. Configure FPGA Device
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IETELCT605 Lab Session #4 Spring 2013
FPGA Complete Flow
5. Configure FPGA Device
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IETELCT605 Lab Session #4 Spring 2013
FPGA Complete Flow
5. Configure FPGA Device
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IETELCT605 Lab Session #4 Spring 2013
Lab Task 1
Download 4-bit Up-Counter with Enable on the
Spartan3E FPGA using switches for the inputs and
LEDs for the outputs.
Hints: How to use the FPGA internal clock?
What is the frequency of the FPGA internal clock?
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IETELCT605 Lab Session #4 Spring 2013
FPGA Spartan3E LCD Display
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IETELCT605 Lab Session #4 Spring 2013
LCD Display Character Set
LCD Display = 2 rows of characters 16 character per each row
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IETELCT605 Lab Session #4 Spring 2013
LCD Display Character Set
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IETELCT605 Lab Session #4 Spring 2013
LCD Character Display Interface
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IETELCT605 Lab Session #4 Spring 2013
LCD Display Command Set
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IETELCT605 Lab Session #4 Spring 2013
LCD Display Command Set
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IETELCT605 Lab Session #4 Spring 2013
LCD Display Operation – Interface Timing
Each 8-bit command to the LCD controller occurs over a 4 bit interfaceEach command is
decomposed into two 4-bit transmissions spaced by 1us. Subsequent commands (each
sequential 4-bit transmission) must be spaced from the next by at least 40us.
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IETELCT605 Lab Session #4 Spring 2013
LCD Display Operation – Interface Timing
FPGA Clk_frequency = 50MHz
Clk_period = 20ns
timeclk
cyclesDescription
1us 50Between corresponding
nibbles
40us 2000Between successive
commands
1.64ms 82000After a “Clear Display”
command
40ns 2 Set up time
230ns 12 Hold time
10ns 1 Fall time
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IETELCT605 Lab Session #4 Spring 2013
LCD Display Operation - Initialization
1. Initialization establishes that the FPGA application wishes to use
the 4-bit data interface to the LCD as follows:
Wait 15 ms or longer. 15ms = 750,000 cycles.
Write SF_D<11:8> = 0x3, pulse LCD_E High for 12 clock cycles.
Wait 4.1 ms = 205,000 cycles.
Write SF_D<11:8> = 0x3, pulse LCD_E High for 12 clock cycles.
Wait 100 μs = 5,000 cycles.
Write SF_D<11:8> = 0x3, pulse LCD_E High for 12 clock cycles.
Wait 40 μs = 2,000 cycles.
Write SF_D<11:8> = 0x2, pulse LCD_E High for 12 clock cycles.
Wait 40 μs = 2,000 cycles.
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IETELCT605 Lab Session #4 Spring 2013
LCD Display Operation–Configuration & Display
2. Configuration
Issue a Function Set command, 0x28, to configure the display for operation
on the Spartan-3E Starter Kit board.
Issue an Entry Mode Set command, 0x06, to set the display to
automatically increment the address pointer.
Issue a Display On/Off command, 0x0C, to turn the display on and
disables the cursor and blinking.
Issue a Clear Display command then delay 1.64 ms=82,000 cycles.
3. Display
Issue a Set DDRAM Address command to specify the starting address in
the Display
Write data to the display using a Write Data to CG RAM or DD RAM
command.
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IETELCT605 Lab Session #4 Spring 2013
Spartan3E LCD Display: Initialization FSM
IDLE
init=0init=1 15ms
750000
cycles
SFD=3
E=1, 12
cycles
E=0
205000
cycles
SFD=3
E=1, 12
cycles
E=0
5000
cycles
SFD=3
E=1, 12
cycles
E=1
2000
cycles
SFD=2
E=1, 12
cycles
Done
E=0
2000
cycles
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IETELCT605 Lab Session #4 Spring 2013
Spartan3E LCD Display: Main FSM
Init
finish
initialize
Entry
Set
CMD=x06
RS=0
Set
Address
CMD=x80
RS=0
Function
Set
CMD=x28
RS=0
Set
Display
CMD=x0C
RS=0
Clear
Display
CMD=x01
RS=0
Pause
82,000
cycles
Char_F
CMD=x46
RS=1
Char_A
CMD=x41
RS=1
Done
Char_P
CMD=x50
RS=1
Char_G
CMD=x42
RS=1
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IETELCT605 Lab Session #4 Spring 2013
Spartan3E LCD Display: Command Timing FSM
Setup 1
E=0
DB=1st nibble
2 cycles
Hold 1
E=1
DB=1st nibble
12 cycles
Hold 2
E=1
DB=2nd nibble
12 cyclesSetup 2
E=0
DB=2nd nibble
2 cycles
wait 1us
50 cycles
wait 40 us
2000 cycles
Done
tx=1tx=0
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IETELCT605 Lab Session #4 Spring 2013
Lab Task 2
Download 4-bit Up-Counter with Enable on the
Spartan3E FPGA using switches for the inputs and
LEDs for the outputs. Hints: How to use the FPGA internal clock?
What is the frequency of the FPGA internal clock?
2. Display the name of one of the team members in
the middle of the Spartan3E LCD.
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IETELCT605 Lab Session #4 Spring 2013
Lab Assignment 4
Download 4-bit Up-Counter with Enable on the
Spartan3E FPGA using switches for the inputs and
the LCD display to show the counter output in
the form of “counter = #number” in the middle of
the LCD Display.