ltc1065 5th order bessel lp filter[18]

8/6/2019 LTC1065 5th Order Bessel LP Filter[18]

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LTC1065

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Clock-Tunable Cutoff Frequency 1mV DC Offset (Typical) 80dB CMR (Typical) Internal or External Clock 50VRMS Clock Feedthrough 100:1 Clock-to-Cutoff Frequency Ratio 80VRMS Total Wideband Noise 0.004% Noise + THD at 2VRMS Output Level 50kHz Maximum Cutoff Frequency Cascadable for Faster Roll-Off Operates from 2.375 to 8V Power Supplies Self-Clocking with 1 RC Available in 8-Pin DIP and 16-Pin SW Packages

The LTC1065 is the first monolithic filter providing bothclock-tunability with low DC output offset and over 12-bitDC accuracy. The frequency response of the LTC1065closely approximates a 5th order Bessel polynomial. Withappropriate PCB layout techniques the output DC offset istypically 1mV and is constant over a wide range of clockfrequencies. With 5V supplies and 4V input voltagerange, the CMR of the device is typically 80dB.

The filter cutoff frequency is controlled either by an inter-nal or external clock. The clock-to-cutoff frequency ratio is100 : 1. The on-board clock is nearly power supply inde-pendent and it is programmed via an external RC. The50VRMS clock feedthrough of the device is considerablylower than other existing monolithic filters.

The LTC1065 wideband noise is 80VRMS and it canprocess large AC input signals with low distortion. With7.5V supplies, for instance, the filter handles up to4VRMS (94dB S/N ratio) while the standard 1kHz THD isbelow 0.005%; 87dB dynamic range (S/N + THD) is ob-

tained with input levels between 2VRMS and 2.5VRMS.

The LTC1065 is available in 8-pin miniDIP and 16-pin SWpackages. For a Butterworth response, see LTC1063 datasheet. The LTC1065 is pin compatible with the LTC1063.

APPLICATIO SU

TYPICAL APPLICATIOU

DESCRIPTIOU

FEATURES

DC Accurate, Clock-TunableLinear Phase 5th Order Bessel

Lowpass Filter

3.4kHz Single 5V Supply Bessel Lowpass Filter

Audio Strain Gauge Amplifiers Anti-Aliasing Filters Low Level Filtering

Digital Voltmeters Smoothing Filters Reconstruction Filters

VIN

4.53k

13k*

5V

0.1F

VOUT

1065 TA01SELF-CLOCKING SCHEME*

200pF*

1

2

3

4

8

7

6

5

LTC10650.1F

5V

4.99k

+ 1FTANT

Frequency Response

FREQUENCY (kHz)

1

GAIN(dB)

10

0

10

20

30

40

50

60

70

80

9010 100

1065 TA01b

, LTC and LT are registered trademarks of Linear Technology Corporation.All other trademarks are the property of their respective owners. Protected by U.S. Patentsincluding 4857860.


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PARAMETER CONDITIONS MIN TYP MAX UNITS

Clock-to-Cutoff Frequency Ratio (fCLK/ fC) 2.375V VS7.5V 1000.5

Maximum Clock Frequency (Note 2) VS = 7.5V 5 MHzVS = 5V 4 MHzVS = 2.5V 3 MHz

Minimum Clock Frequency (Note 3) 2.5V VS7.5V, TA < 85C 30 Hz

Input Frequency Range 0 0.9fCLKFilter Gain VS = 5V, fCLK = 25kHz, fC = 250Hz

fIN = 250Hz 3.5 3.1 2.7 dBfIN = 1kHz 43.0 41.0 39.0 dB

VS = 5V, fCLK = 500kHz, fC = 5kHzfIN = 100Hz 0 dB

fIN = 1kHz = 0.2fC 0.215 0.175 0.135 dB

fIN = 2.5kHz = 0.5fC 1.1 0.972 0.84 dB

fIN = 4kHz = 0.8fC 2.35 2.13 1.9 dB

fIN = 5kHz = fC 3.35 3.1 2.7 dB

fIN = 10kHz = 2fC 14.5 14.15 13.0 dB

fIN = 20kHz = 4fC 43.0 41.15 39.0 dB

ELECTRICAL CHARACTERISTICS

Consult LTC Marketing for parts specified with wider operating temperature ranges.

PACKAGE/ORDER I FOR ATIOU UW

Total Supply Voltage (V + to V ) .......................... 16.5VPower Dissipation ............................................. 400mW

Voltage at Any Input .... (V 0.3V) VIN (V+ + 0.3V)Burn-In Voltage ...................................................... 16VStorage Temperature Range ................ 65C to 150C

Operating Temperature Range (Note 7)LTC1065C .............................................. 0C to 70C

LTC1065I ........................................... 40C to 85CLTC1065M (OBSOLETE) .................. 55C to 125C

Lead Temperature (Soldering, 10 sec) ................. 300C

ORDER PARTNUMBER

ORDER PARTNUMBER

LTC1065CN8LTC1065IN8

LTC1065MJ8

LTC1065CSWLTC1065ISW

TJMAX = 100C, JA = 85C/W

TOP VIEW

SW PACKAGE16-LEAD PLASTIC SO WIDE

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

NC

VIN

GND

NC

V

NC

NC

CLK OUT

VOS ADJ

NC

VOUT

NC

V+

NC

NC

CLK IN

ABSOLUTE AXI U RATI GSW W W U

(Note 1)

The denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at VS = 5V, fCLK = 500kHz, fC = 5kHz, RL = 10k, TA = 25C unless otherwise specified.

1

2

3

4

8

7

6

5

TOP VIEW

VIN

GND

V

CLK OUT

VOS ADJ

VOUT

V+

CLK IN

N8 PACKAGE8-LEAD PLASTIC DIP

TJMAX = 100C, JA = 110C/W (N)

J8 PACKAGE8-LEAD CERAMIC DIP

TJMAX = 150C, JA = 100C/W (J)

OBSOLETE PACKAGEConsider the N Package for an Alernate Source

Order Options Tape and Reel: Add #TRLead Free: Add #PBF, Lead Free Tape and Reel: Add #TRPBF, Lead Free Part Marking:http://www.linear.com/leadfree/
http://www.linear.com/leadfree/http://www.linear.com/leadfree/http://www.linear.com/leadfree/


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PARAMETER CONDITIONS MIN TYP MAX UNITS

Filter Gain VS = 2.375V, fCLK = 500kHz, fC = 5kHz

fIN = 1kHz 0.225 0.185 0.145 dBfIN = 2.5kHz 1.1 1.0 0.83 dB

fIN = 4kHz 2.35 2.15 1.9 dB

fIN = 5kHz 3.35 3.1 2.7 dB

fIN = 10kHz 14.5 14.1 13.0 dB

Clock Feedthrough 2.375V VS7.5V 50 VRMSWideband Noise (Note 4) 2.375V VS7.5V, 1Hz < f < fCLK 80 VRMSTHD + Wideband Noise (Note 5) VS = 7.5V, fC = 20kHz, fIN = 1kHz, 87 dB

2VRMS VIN 2.5VRMSFilter Output DC Swing VS = 2.375V 1.5/ 2.0 1.7/2.2 V

1.3/ 1.8 V

VS = 5V 4.0/ 4.5 4.3/ 4.8 V 3.8/ 4.3 V

VS = 7.5V 6.5/ 7.0 6.8/ 7.3 V 6.3/ 6.8 V

Input Bias Current 10 nA

Dynamic Input Impedance 800 M

Output DC Offset (Note 6) VS = 2.375V 2 mVVS = 5V 0 5 mVVS = 7.5V 4 mV

Output DC Offset Drift VS = 2.375V 10 V/CVS = 5V 20 V/CVS = 7.5V 25 V/C

Self-Clocking Frequency (fOSC) R (Pin 4 to 5) = 20k, C (Pin 5 to GND) = 470pFVS = 2.375V 99 103 112 kHz

LTC1065C

95 103 112 kHzLTC1065M 92 100 112 kHz

VS = 5V 100 106 112 kHzLTC1065C 98 106 114 kHzLTC1065M 97 105 114 khz

VS = 7.5V 102 106 114 kHzLTC1065C 101 109 116 kHzLTC1065M 100 108 116 kHz

External CLK Pin Logic Thresholds VS = 2.375V Min Logical 1 1.43 VMax Logical 0 0.47 V

VS = 5V Min Logical 1 3 VMax Logical 0 1 V

VS = 7.5V Min Logical 1 4.5 V

Max Logical 0 1.5 VPower Supply Current VS = 2.375V, fCLK = 500kHz 2.5 4.0 mA

LTC1065C 5.5 mALTC1065M 6.0 mA

VS = 5V, fCLK = 500kHz 5.5 9 mALTC1065C 11 mALTC1065M 12 mA

VS = 7.5V, fCLK = 500kHz 7.0 12.0 mALTC1065C 14.5 mALTC1065M 16.0 mA

ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at VS = 5V, fCLK = 500kHz, fC = 5kHz, RL = 10k, TA = 25C unless otherwise specified.


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INPUT FREQUENCY (kHz)

1

GAIN

(dB)

10 100

1065 G06

10

0

10

20

30

4050

60

70

80

90200

A B C

A. fCLK = 1MHzB. fCLK = 2MHzC. fCLK = 3MHzD. fCLK = 4MHzE. fCLK = 5MHz

VIN = 1.4VRMSTA = 25C

E

D


1

GAIN

(dB)

10 100

1065 G05

10

0

10

20

30

4050

60

70

80

90200

A B C D

A. fCLK = 1MHzB. fCLK = 2MHzC. fCLK = 3MHzD. fCLK = 4MHz

VIN = 1.4VRMSTA = 25C


1

GAIN

(dB)

10 100

1065 G04

B C

VIN = 750mVRMSTA = 25C

10

0

10

20

30

40

50

60

70

80

90200

A

A. fCLK = 0.5MHzB. fCLK = 1MHzC. fCLK = 2MHz

ELECTRICAL C CHARA TERISTICS

Output Offset vs Clock,Medium Clock RatesSelf-Clocking Frequency vs R

Output Offset vs Clock,Low Clock Rates

EXTERNAL CLOCK FREQUENCY (kHz)

OUTPUTOFFSET(mV)

5

4

3

2

1

0

1

2

3

4

5

1065 G03

500 10000

VS = 7.5V

VS = 5V

VS = 2.5V

FREQUENCY (kHz)

RPINS4TO5(k)

110

100

90

80

70

60

50

40

30

20

10

1065 G01

100 300 500

LTC1065

R C

4 5

C = 200pFfOSC 1/RC

Gain vs Frequency; VS = 7.5VGain vs Frequency; VS = 2.5V Gain vs Frequency; VS = 5V

C CHARA TERISTICSUW

ATYPICAL PERFOR CE

Note 1: Absolute Maximum Ratings are those values beyond which the lifeof a device may be impaired.

Note 2: The maximum clock frequency is arbitrarily defined as the

frequency at which the filter AC response exhibits

1dB of gain peaking.Note 3: At limited temperature ranges (i.e., TA 50C) the minimum clockfrequency can be as low as 10Hz. The typical minimum clock frequency isarbitrarily defined as the clock frequency at which the output DC offsetchanges by more than 1mV.

Note 4: The wideband noise specification does not include the clockfeedthrough.

Note 5: To properly evaluate the filters harmonic distortion an invertingoutput buffer is recommended. An output buffer (although recommended)is not necessarily needed when measuring output DC offset or wideband

noise (see Figure 3).Note 6: The output DC offset is optimized for 5V supply. The output DCoffset shifts when the power supplies change; however, this phenomenonis repeatable and predictable.

Note 7: The LTC1065C is guaranteed to meet the specified performancefrom 0C to 70C and is designed, characterized and expected to meetspecified performance from 40C to 85C but is not tested or QAsampled at these temperatures. The LTC1065I is guaranteed to meetspecified performance from 40C to 85C.

EXTERNAL CLOCK FREQUENCY (Hz)

OUTPUTOFFSET(mV)

50

45

40

35

30

25

20

15

10

5

0

1065 G02

10 110 210

AB

A. TA = 25CB. TA = 85C

VS = 5V


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LTC1065

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0

GROUPDELAY(s)

45

40

35

30

25

20

15

10

5

06 213 9 181512

VS = 5VfC = 10kHz

1065 G17

C CHARA TERISTICSUW

ATYPICAL PERFOR CE

HORIZONTAL: 0.1ms/DIV, VERTICAL: 2V/DIV

VS = 5V, fC = 10kHz, VIN = 1kHz 3VPSQUARE WAVE

1065 G16

Transient Response Group Delay

PI FU CTIO SU UU

Power Supply Pins (Pins 6, 3, N Package)

The positive and negative supply pin should be bypassedwith a high quality 0.1F ceramic capacitor. In applicationswhere the clock pin (5) is externally swept to provideseveral cutoff frequencies, the output DC offset variationis minimized by connecting an additional 1F solid tanta-

lum capacitor in parallel with the 0.1F disc ceramic. Thistechnique was used to generate the graphs of the outputDC offset variation versus clock; they are illustrated in theTypical Performance Characteristics section.

When the power supply voltage exceeds 7V, and whenV is applied before V+ (if V+ is allowed to go belowground) connect a signal diode between the positivesupply pin and ground to prevent latch-up (see TypicalApplications).

Ground Pin (Pin 2, N Package)

The ground pin merges the internal analog and digitalground paths. The potential of the ground pin is thereference for the internal switched-capacitor resistors,and the reference for the external clock. The positive inputof the internal op amp is also tied to the ground pin.

For dual supply operation, the ground pin should beconnected to a high quality AC and DC ground. A groundplane, if possible, should be used. A poor ground will

degrade DC offset and it will increase clock feedthrough,noise and distortion.

A small amount of AC current flows out of the ground pinwhether or not the internal oscillator is used. The fre-quency of the ground current equals the frequency of theclock. The average value of this current is approximately

55A, 110A, 170A for 2.5V, 5V and 7.5V suppliesrespectively.

For single supply operation, the ground pin should bepreferably biased at half supply (see Typical Applications).

VOS Adjust Pin (Pin 8, N Package)

The VOS adjust pin can be used to trim any small amountof output DC offset voltage or to introduce a desired outputDC level. The DC gain from the VOS adjust pin to the filteroutput pin equals two.

Any DC voltage applied to this pin will reflect at the outputpin of the filter multiplied by two.

If the VOS adjust pin is not used, it should be shorted to theground pin. The DC bias current flowing into the VOSadjustpin is typically 10pA.

The VOS adjust pin should always be connected to an ACground; AC signals applied to this pin will degrade the filterresponse.


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LTC1065

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INTERNAL CLOCK FREQUENCY (kHz)

K

1.25

1.20

1.15

1.10

1.051.00

0.95

0.90

0.85

0.80

0.75

1065 F04b

100 300 500

VS = 7.5V

VS = 2.5V

fCLK = K/RCC = 200pFTA = 25C

VS = 5V

200 400

VIN

R

VOUT

1065 F04a

C

V V+

1

2

3

4

8

7

6

5

LTC1065

V

50k

V+

0.1F

VOUT

1065 F03

0.1FCLOCK IN

+

LT1022

20pF

VIN

50k

8

7

6

5

1

2

3

4

LTC1065

TEST CIRCUIT

Figure 3. Test Circuit for THD

Self-Clocking Operation

The LTC1065 features an internal oscillator which can betuned via an external RC. The LTC1065s internal oscillatoris primarily intended for generation of clock frequenciesbelow 500kHz. The first curve of the Typical PerformanceCharacteristics section shows how to quickly choose thevalue of the RC for a given frequency. More precisely, thefrequency of the internal oscillator is equal to:

fCLK = K/RCFor clock frequencies (fCLK) below 100kHz, K equals 1.07.Figure 4b shows the variation of the parameter K versusclock frequency and power supply. First choose the de-sired clock frequency (fCLK< 500kHz), then through Figure4b pick the right value of K, set C = 200pF and solve for R.

Example 1: fCUTOFF = 2kHz, fCLK = 200kHz, VS = 5V,TA = 25C, K = 1.0, C = 200pF

then, R = (1.0)/(200kHz 204pF) = 24.5k.

USA

OPPLICATI

WU UI FOR ATIO

Figure 4a. Figure 4b. fCLK vs K

Note a 4pF parasitic capacitance is assumed in parallelwith the external 200pF timing capacitor. Figure 5 showsthe clock frequency variation from 40C to 85C. The200kHz clock of Example 1 will change by 1.75% at 85C.

For a limited temperature range, the internal oscillator ofthe LTC1065 can be used to generate clock frequenciesabove 500kHz (Figures 6 and 7). The data of Figure 6 isderived from several devices. For a given external (RC)value, the observed device-to-device clock frequency varia-

tion was 1% (VS = 5V), and 1.25% for VS = 2.5V.

Example 2: fCUTOFF = 20kHz, fCLK = 2MHz, VS = 7.5V,TA = 25C, C = 10pF

from Figure 6, K = 0.575,and, R = (0.575)/(2MHz 14pF) = 20.5k.


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CLOCK FREQUENCY (MHz)

0.5

K

0.80

0.75

0.70

0.65

0.60

0.55

0.50

0.45

0.402.5

1065 F07

1.0 1.5 2.0 3.0


VS = 7.5V

VS = 2.5V

VS = 5V

CLOCK FREQUENCY (MHz)

0.5

K

0.80

0.75

0.70

0.65

0.60

0.55

0.50

0.45

0.40 2.5

1065 F06

1.0 1.5 2.0 3.0


VS = 7.5V

VS = 2.5V

VS = 5V

CLOCK FREQUENCY (kHz)

0

fCLKCHANGENORMALIZED

TOITS25CVALUE

(%)

4

3

2

1

0

1

2

3

4400

1065 F05

100 200 300 500

C = 200pFTA = 40C

TA = 85C

VS = 2.5VVS = 5V

VS = 7.5V

VS = 7.5V

VS = 5VVS = 2.5V

USA

OPPLICATI

WU UI FOR ATIO

Figure 5. fCLK vs Temperature

Figure 6. fCLK vs K

Figure 7. fCLK vs K

A 4pF parasitic capacitance is assumed in parallel with theexternal 10pF capacitor. A 1% clock frequency variationfrom device to device can be expected. The 2MHz clockfrequency designed above will typically drift to 1.74MHz at70C (Figure 7).

The internal clock of the LTC1065 can be overridden by anexternal clock provided that the external clock source candrive the timing capacitor C, which is connected from theclock input pin to ground.

Output Offset

The DC output offset of the LTC1065 is trimmed totypically less than 1mV. The trimming is done at VS =

5V. To obtain optimum DC offset performance, appropri-ate PC layout techniques should be used and the filter ICshould be soldered to the PC board. A socket will degradethe output DC offset by typically 1mV. The output DC offsetis sensitive to the coupling of the clock output pin 4 (Npackage) to the negative power supply pin 3 (N package).The negative supply pin should be well decoupled. Whenthe surface mount package is used, all NC pins should begrounded. When the output DC voltage is measured witha voltmeter, the filter output pin should be buffered. Longtest leads should be avoided.

With fixed power supplies, the output DC offset should notchange by more than 100V over 10Hz to 1MHz clockfrequency variation. When the filter clock frequency isfixed, the output DC offset will typically change by 4mV(2mV) when the power supply varies from 5V to 7.5V(2.5V). See Typical Performance Characteristics.

Common Mode Rejection

The common mode rejection is defined as the change ofthe output DC offset with respect to the DC change of the

input voltage applied to the filter.

CMR = 20log (VOS OUT/VIN)(dB)

Table 3 illustrates the common mode rejection for threepower supplies and three temperatures. The commonmode rejection improves if the output offset is adjusted toapproximately 0V. The output offset can be adjusted viapin 8 (N package). See Typical Applications.


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USA

OPPLICATI

WU UI FOR ATIO

Table 3. CMR Data, fCLK = 100kHz

25C

POWER SUPPLY VIN 40C 25C 85C (VOS Nulled)

2.5V 1.8V 84dB 83dB 80dB 83dB

5V 4V 82dB 78dB 77dB 78dB

7.5V 6V 80dB 77dB 76dB 80dB 5m

V/DIV

2s/DIV1065F08

fCLK = 100kHz, fC = 1kHz, VS = 5V, 1MHz SCOPE BW

Figure 8. LTC1065 Output Clock Feedthrough + Noise

0.5

mV/DIV

2s/DIV1063 F09

fCLK = 100kHz, fC = 1kHz, VS = 5V, 1MHz SCOPE BW

Figure 9. LTC1065 Output Clock Feedthrough + Noise

The above data is valid for clock frequencies up to 800kHz, 900kHz, 1MHz, forVS = 2.5V, 5V, 7.5V respectively.

Clock Feedthrough

Clock feedthrough is defined as the RMS value of the clockfrequency and its harmonics which are present at thefilters output pin. The clock feedthrough is tested with the

filter input grounded and it depends on the quality of thePC board layout and power supply decoupling. Any para-sitic switching transients during the rise and fall of theincoming clock, are not part of the clock feedthroughspecifications; their amplitude strongly depends on scopeprobing techniques as well as ground quality and powersupply bypassing. For a power supply VS = 5V, the clockfeedthrough of the LTC1065 is 50VRMS; for VS = 7.5V,the clock feedthrough approaches 75VRMS. Figures 8and 9 show a typical scope photo of the LTC1065 outputpin when the input pin is grounded. The filter cutoff

frequency was 1kHz, while scope bandwidth was chosento be 1MHz so that switching transients above the 100kHzclock frequency would show.

Wideband Noise

The wideband noise data is used to determine the operat-ing signal-to-noise ratio at a given distortion level. Thewideband noise (VRMS) is nearly independent of the valueof the clock frequency and excludes the clock feedthrough.The LTC1065s typical wideband noise is 80VRMS. Figure9 shows the same scope photo as Figure 8 but with a moresensitive vertical scale. The clock feedthrough is imbed-ded in the filters wideband noise. The peak-to-peak wide-band noise of the filter can be clearly seen; it is approxi-mately 420VP-P. Note that 420VP-P equals the 80VRMSwideband noise of the part multiplied by a crest factorof 5.25.

Aliasing

Aliasing is an inherent phenomenon of sampled datafilters. It primarily occurs when the frequency of an inputsignal approaches the sampling frequency. For theLTC1065, an input signal whose frequency is in the rangeof fCLK6% will generate an alias signal into the filterspassband and stopband. Table 4 shows details.

Example: LTC1065, fCLK = 20kHz, fC = 200kHz,fIN = (19.6kHz, 100mVRMS)fALIAS = (400Hz, 3.16mVRMS)


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OPPLICATI

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An input RC can be used to attenuate incoming signalsclose to the filter clock frequency (Figure 10). A Besselpassband response will be maintained if the value of the

input resistor follows Table 1.

Table 4. Aliasing Data

INPUT FREQUENCY OUTPUT FREQUENCY0.9995 fCLK 0.0005 fCLK 0.01 dB

0.995 fCLK 0.005 fCLK 0.98 dB

0.99 fCLK 0.01 fCLK 3.13 dB

0.9875 fCLK 0.0125 fCLK 4.79 dB

0.985 fCLK 0.015 fCLK 7.21 dB

0.9825 fCLK 0.0175 fCLK 10.43 dB

0.98 fCLK 0.02 fCLK 14.14 dB

0.975 fCLK 0.025 fCLK 21.84 dB

0.97 fCLK 0.03 fCLK 28.98 dB

0.965 fCLK 0.035 fCLK 35.31 dB

0.96 fCLK 0.04 fCLK 40.94 dB0.955 fCLK 0.045 fCLK 45.96 dB

0.95 fCLK 0.05 fCLK 50.46 dB

0.94 fCLK 0.06 fCLK 58.29 dB

0.93 fCLK 0.07 fCLK 64.90 dB

0.9 fCLK 0.1 fCLK 80.20 dB

OUTPUT AMPLITUDEREFERENCED TO

INPUT SIGNAL

VIN

VOUT

1065 F10

C

V V+

R

0.1F

1

2

3

4

8

7

6

5

LTC1065

0.1F

fCLK20 102RC

1 fCLK

fCLK

Figure 10. Adding an Input Anti-Aliasing RC


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LTC1065

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VIN

5V

R

5V

0.1F

VOUT

1065 TA03

1

2

3

4

8

7

6

5

LTC1065

C

1

2

3

4

8

7

6

5

LTC1065

5V 5V

0.1F0.1F

0.1F

VIN

VOUT

VIN

5V

R

5V

0.1F

VOUT

1065 TA02

1

2

3

4

8

7

6

5

LTC1065

C

1

2

3

4

8

7

6

5

LTC1065

5V 5V

0.1F0.1F

0.1F

fC (1/RC)(1/100)WIDEBAND NOISE = 110VRMSATTENUATION AT f = 2fC = 60dB

Cascading Two LTC1065s for Steeper Roll-Off Sharing Clock for Multichannel Applications

TYPICAL APPLICATIO SU


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LTC1065

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J8 0801

.014 .026

(0.360 0.660)

.200

(5.080)

MAX

.015 .060

(0.381 1.524)

.125

3.175MIN

.100(2.54)BSC

.300 BSC

(7.62 BSC)

.008 .018

(0.203 0.457)0 15

.005

(0.127)MIN

.405

(10.287)MAX

.220 .310

(5.588 7.874)

1 2 3 4

8 7 6 5

.025

(0.635)RAD TYP

.045 .068

(1.143 1.650)FULL LEAD

OPTION

.023 .045

(0.584 1.143)HALF LEAD

OPTION

CORNER LEADS OPTION(4 PLCS)

.045 .065

(1.143 1.651)NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATEOR TIN PLATE LEADS

PACKAGE DESCRIPTIOU

J8 Package8-Lead CERDIP (Narrow .300 Inch, Hermetic)

(Reference LTC DWG # 05-08-1110)

OBSOLETE PACKAGE


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LTC1065

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SW Package16-Lead Plastic Small Outline (Wide .300 Inch)

(Reference LTC DWG # 05-08-1620)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

PACKAGE DESCRIPTIOU

S16 (WIDE) 0502

NOTE 3

.398 .413(10.109 10.490)

NOTE 4

16 15 14 13 12 11 10 9

1

N

2 3 4 5 6 7 8

N/2

.394 .419(10.007 10.643)

.037 .045(0.940 1.143)

.004 .012(0.102 0.305)

.093 .104(2.362 2.642)

.050(1.270)

BSC

.014 .019(0.356 0.482)

TYP

0 8 TYP

NOTE 3.009 .013

(0.229 0.330)

.005(0.127)

RAD MIN

.016 .050(0.406 1.270)

.291 .299(7.391 7.595)

NOTE 4

45.010 .029(0.254 0.737)

INCHES(MILLIMETERS)

NOTE:1. DIMENSIONS IN

2. DRAWING NOT TO SCALE3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.

THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)

.420MIN

.325 .005

RECOMMENDED SOLDER PAD LAYOUT

.045 .005

N

1 2 3 N/2

.050 BSC.030 .005TYP


16/16

LTC1065

1065fb

TYPICAL APPLICATIO SU

VIN

5V

13k

5V

0.1F

VOUT

1065 TA04

0.1F

200pF

1

2

3

4

8

7

6

5

LTC10654.53k

+

4.99k

1FTANT

VIN

V

7.5VV+

7.5V

0.1F

1

2

3

4

8

7

6

5

LTC1065

fCLK0.1F

7.5V

1FTANT

+

1065 TA05

VOUT

10k

2.5mV

LT1009

10k

*

* OPTIONAL, 1N4148

Adjusting VOS(OUT) for7.5 Supply Operation

Single 5V Supply Operation (fC = 3.4kHz)

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