implementation of multicarrier based control schemes for

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Volume-5, Issue-6, December-2015

International Journal of Engineering and Management Research

Page Number: 484-493

Implementation of Multicarrier Based Control Schemes for Cascaded 9-Levels Multilevel Inverter

Pratigya Sharma1, Prof. Pawan Pandey2

1M.Tech Student, Department of Electrical and Electronics Engineering, Malwa Institute of Technology, Indore, INDIA 2

Sr. Assistant Professor, Malwa Institute of Technology, Indore, INDIA

ABSTRACT

In this proposed work upon the various Multi Carrier Based Pulse width (MCBPW) modulation techniques implemented by single phase multilevel inverter and their comparisons. The main focus in this paper is reducing of total harmonic distortion (THD). The multilevel inverter is used to improve the voltage quality by reducing the harmonics, as the number of voltage levels of multilevel inverter (MLI) is increased the harmonics are reduced and hence losses are minimized significantly, increasing the efficiency of the system. In proposed paper generation of carrier based PWM scheme using IPD, POD and APOD. This control signal used in multilevel inverter (MLI), and 9-level inverter system modeled and simulated using MATLAB simulator. The test results verify the effectiveness of the proposed strategy in terms of low distorted voltage with low-switching losses and total harmonic reduces in output voltage with increasing the number of voltage level. Keywords— MLI, THD, IPD, POD and APOD

I. INTRODUCTION

The Inverter is a device that converts electrical power from DC to AC form using electronic circuits. Generally simple inverter gives 2 or 3 level output voltage. Multilevel inverter gives 3 or more output voltage levels. It produces a stepped output voltage with reduced harmonic distortion when compared to a 2 level inverter. Numerous industrial applications have begun to require higher power apparatus in recent years. Some medium voltage motor drives and utility applications require medium voltage and megawatt power level. For a medium voltage grid, it is troublesome to connect only one power semiconductor switch directly. As a result, a multilevel power converter structure has been introduced as an alternative in high

power and medium voltage situations subsequently; several multilevel converter topologies have been developed. Multilevel Inverter (MLI) offers a number of advantages when compared to the conventional two level inverter in terms of improved DC link utilization and harmonic spectrum. The stepped approximation of the sinusoidal output waveform with higher levels reduces the harmonic distortion of the output waveform and the stresses across the semiconductor devices and also allows higher voltage/current and power ratings. The reduced switching frequency of each individual switch of the inverter also reduces the switching losses and improves the efficiency of the inverter. In recent years, multilevel inverters have gained popularity with medium and high power ratings. Renewable energy sources such as photovoltaic, wind, and fuel cells can be interfaced to a multilevel converter system. Many multilevel converter topologies have been proposed during the last two decades. Research has engaged novel converter topologies and unique modulation schemes. In recent era there is huge power requirement in industries and other areas. Multilevel inverter has become popular to fulfill power requirement due to advantage of high power quality waveforms, low electromagnetic compatibility.

II. DIFFERENT MODULATION

METHODS CONTROLLING OF MLI

Mainly the power electronic converters are operated in the switched mode, means the switches among the converter are invariably in either one of the 2 states, turned off (no current flows), or turned on (saturated with solely a tiny voltage drop across the switch). The operation within the linear region other than for the unavoidable transition from conducting to non



conducting incurs an undesirable loss of efficiency and an intolerable rise in power switch power dissipation. A. Pulse Width Modulation (PWM)

This happens rapidly enough that the inductors and capacitors at the input and output nodes of the converter average or filter the switched signal. Switched element is attenuated and the desired DC or low frequency AC component is retained. This method is known as Pulse Width Modulation (PWM), since the required average worth is controlled by modulating the width of the pulses. PWM Techniques The fundamental methodology of pulse width modulation (PWM) are divided into the Traditional voltage source and current regulated strategies. Voltage-source strategies more easily lend themselves to digital signal processor (DSP) or programmable logic device (PLD) implementation[39].

Fig 1.1. Pulse-width modulation

However, current controls usually rely on event scheduling and are thus analog implementations that will solely be reliably operated up to a certain power level. In distinct current -regulated strategies the harmonic performance is not as good as that of voltage-source strategies. A sample PWM methodology is delineated below. There are many modulation techniques are used for multilevel inverter to synthesize the output voltage as close as possible to the sinusoidal wave form. Its main use is to allow the control of the ability provided to electrical devices. The control techniques developed for harmonic reduction and switching loss minimization [39]. B. Multi Carrier Pulse Width Modulation Techniques

The carrier-based modulation schemes for multilevel inverters can be generally classified into two categories: 1. Phase -shifted 2. Level –shifted 1. Phase shifted multi carrier modulation using the formula is: 360’/(m-1)

This type of modulation is pattern that encodes information as variations in the instantaneous phase of a carrier wave. 2. Level shifted multi carrier modulation

In level shifted multi carrier modulation (m-1) carrier waves are used for m- level.These triangular carrier also having same frequency and amplitude. The (m-1) triangular carriers are vertically disposed such that the bands they occupy are contiguous. There are three alternative PWM strategies with different phase relationships for the level-shifted multicarrier modulation. C. In Phase Disposition (IPD)

This technique involves a number of carriers (m-l) which are all in phase accordingly. The phase disposition PWM technique is illustrated in - The rules for the in phase disposition methodology, once the number of level N = 3, are • The N –1 = 3-1=2 carrier waveforms are organized so that each carrier is in phase. • The converter is switched to +Vdc/ 2 once the reference is greater than both carrier waveforms. • The convertor is switched to zero when the reference is greater than the lower carrier waveform however less than the upper carrier waveform. • The converter is switched to - Vdc/ 2 once the reference is less than both carrier waveforms. In the carrier -based implementation, at every instant of time the modulation signals are compared with the carrier and depending on which is greater, the switching pulses are generated.

Fig. 1.2 : Switching pattern produced using the IPD

carrier-based PWM scheme

D. Phase Opposition Disposition (POD) For phase opposition disposition (POD)

modulation all carrier waveforms above zero reference are in phase and are 180 out of phase with those below zero axis. The rules for the phase opposition disposition method, when the number of level N = 3 are



1.The N –1 = 2 carrier waveforms are organized so all carrier waveforms above zero are in phase and are 180 out of phase with those below zero. 2.The converter is switched to + Vdc/ 2 once the reference is greater than both carrier waveforms. 3.The converter is switched to zero once the reference is greater than the lower carrier waveform but less than the upper carrier waveform. 4.The converter is switched to - Vdc / 2 once the reference is less than each carrier waveforms.

As seen from Figure 3.10 the figure illustrates the switching functions produced by POD carrier based PWM scheme. In PWM scheme there are two triangles, upper triangle magnitude from 1 to 0 and the lower triangle from 0 to –1 and these 2 triangle waveforms are in out of phase. Once the modulation signal is greater than both the carrier waveforms, S1ap and S2ap are turned on and the converter switches to positive node voltage and once the reference is less than the upper carrier waveform however greater than the lower carrier, S2ap and S1an are turned on and the converter power switches to neutral purpose. when the reference is lower than each carrier waveforms, S1an and S2an are turned on and the converter switches to negative node voltage. E. Alternate Phase Opposition Disposition (APOD)

In case of alternate phase disposition (APOD) modulation, every carrier waveform is in out of phase with its neighbor carrier by 180. Since APOD and POD schemes in case of 3 level inverter are an equivalent, 5 level inverter is considered to discuss about the APOD methodology. The foundations for APOD methodology, once the number of level N = 5, are

Fig.1.3. Switching pattern produced using the POD carrier

-based PWM scheme:

1. The N – 1 = four carrier waveforms are organized so that each carrier waveform is in out of phase with its neighbor carrier by 180. The converter switches to + Vdc/ 2 when the reference is greater than all the carrier waveforms. 2. The converter switches to Vdc/ four once the reference is less than the uppermost carrier waveform and greater than all other carriers. 3. The converter switches to 0 when the reference is less than 2|the 2 uppermost carrier waveform and greater than two lowermost carriers. 4. The converter switches to - Vdc/ four when the reference is greater than the lowermost carrier waveform and lesser than all other carriers. 5. The converter switches to -Vdc/ 2 when the reference is lesser than all the carrier waveforms.

Fig. 1.4: Switching pattern produced using the APOD

carrier -based PWM scheme.

III. PROPOSED 9-LEVEL DESIGN

In case of 9 level Asymmetric Cascaded MLI three DC sources are used having 2 same and third different and 12 power switches are used. The Asymmetric Multilevel Inverter increases the number of levels in the output and reduces the number of input DC sources required [3]. IGBT is used as semiconductor switch for designing the inverter circuit. It has the high power rating, less conduction loss and less switching loss. These topology uses level-shifted multi carrier based new PWM method, used to produced a nine- level output voltage.



Fig. 1.5: Simulink model of 7-level inverter

The simulink model of 9- level multilevel inverter implemented in Matlab-Simulink is shown in Figure 1.5 and 1.6.It is basically a Cascaded H-bridge type of Multilevel Inverter. Here the used DC source is Asymmetrical type, Asymmetrical source defines that it has different value of DC sources used in an Inverter. For 9 level inverter the DC sources are 100V, 200v, and 100 V respectively. The simulink model for 9- level multilevel inverter shown in figure 1.5 and 1.6

Fig. 1.6: Simulink model of 9 level with IM

Working of this inverter is nothing but how we make power switches (IGBTs) ON and OFF as per voltage level desired. We have generated switching pulses to obtain staircase output voltage which resembles nearly equal to sine wave. For different switching angles the power circuit behaves differently producing different waveforms. In this topology, we have generated 9 voltage levels as 0, 100V, 200V, 300V and 400V .The circuit working for each level is described below: For 0 voltage level Since S1and S3 are ON or all power switches are OFF, the current will cancelled out in the bridge and hence it gives 0 V voltage level. For 100V voltage level Since S1, S10, S12, S6, S8 and S2 are ON and remaining switches are OFF, the voltage across load will gives 100V level. For 200V voltage level Since S1, S4, S5, S6, S10 &



S12 are ON and remaining switches are OFF, the voltage across load will gives 200V level. For 300V voltage level Since S1, S2, S5, S6, S10 & S12 are ON and remaining switches are OFF, the voltage across load will gives 300V level For 400Vvoltage level Since S1, S2, S5, S6, S9 & S10 are ON and remaining switches are OFF, the voltage across load will gives 400V level For 0V voltage level Since S1and S3 are ON or all power switches are OFF, the current will cancelled out in the bridge and hence it gives 0 V voltage level For- 100V voltage level Since S3, S4, S6, S8, S10, and S12 are ON and remaining switches are OFF, the voltages across load will gives -100V level. For -200V voltage level Since S2, S4, S7, S8 S10, and S12are ON and remaining switches are OFF, the voltage across load will gives -200V level. For- 300V voltage level Since S3, S4, S7, S8, S10, & S12 are ON and remaining switches are OFF, the voltages across load will gives -300V level. I. For- 300V voltage level For -400V voltage level Since S3, S4, S7, S8, S11, & S12 are ON and remaining switches are OFF, the voltages across load will gives -400V level For detail operation of new topology can also be understand by analyzing table no. 1.1 which is given below. Here 0 means switches are OFF and 1 means switches are ON

Table no. 5.1 Switching pattern for asymmetrical cascaded nine level inverter

Table 1.2: System parameters for nine level Inverter System Parameters Value

Reference frequency 50 Hz

Carrier frequency 1.2K Hz

Load resistance 1Ω Load inductance 1 mH

DC Sources 100V, 200V,300V

IV. RESULT SWITCHING SCHEME

In this section, a switching procedure is developed so the topology may be modulated with the extent shifted pulse width modulation (PWM). This modulation schemes can be applied to the cascaded H-bridge (CHB) inverters. An m-level CHB inverter using level-shifted multicarrier modulation scheme needs (m-1) triangular carriers, all having an equivalent frequency and amplitude. The (m-1) triangular carriers are vertically disposed specified the bands they occupy are contiguous. There are 3 different PWM methods with different phase relationships for the level-shifted multicarrier modulations are developed shown in figure 1.7, 1.8 and 1.9. (i) In-phase disposition (IPD), where all carrier waveforms are in phase. (ii) Phase opposition disposition (POD), where all carrier waveforms higher than zero reference are in phase but in opposition with those below the zero reference. (iii) Alternative phase opposite disposition (APOD), where all carriers are alternatively in opposite disposition. B. Generation of Reference and Carrier Waveform for 9- CLSPWM Inverter

Fig.1.7: Reference and carrier waveform for IPD

CLSPWM



Figure 1.8: Reference and carrier waveform for POD

CLSPWM

Figure 1.9: Reference and carrier waveform for APOD CLSPWM

Also shows the output voltage of nine-level

asymmetrical cascaded multilevel inverters cascaded is compared for the PD, POD, APOD techniques ,and it also shows the THD profile and performance of the circuit with IM for three pwm techniques, and also the compare all result with seven-level MLI.

Cascaded multi level inverter shows the lowest THD profile without any type of filter and also any type of dependency of inductor and capacitor used for smooth the current wave form and due to less number of switching devices gate firing circuit also reduced that’s why total cost and performance has been increased .

Simulation Result of (9-Level) ACMLI with IM Using IPD- CLSPWM

Figure 1.10: Output phase voltage waveform for asymmetric (9-level) MLI using IPD-CLSPWM

Figure1.11: FFT analysis of voltage waveform of asymmetric (9-level) cascaded MLI using IPD-CLSPWM



Figure 1.12: Motor output of (9-level) cascaded MLI using IPD-CLSPWM

Simulation Result of (9-Level) ACMLI with IM Using

POD-CLSPWM

Figure 1.13: Output phase voltage waveform for asymmetric (9-level) MLI using POD-CLSPWM

Figure 1.14: FFT analysis of voltage waveform of asymmetric (9-level) cascaded MLI using POD-CLSPWM



Figure 1.15: Motor output of (9-level) cascaded MLI using

POD-CLSPWM

Simulation Result of (9-Level) ACMLI with IM Using APOD- CLSPWM

Figure 1.16: Output phase voltage waveform for

asymmetric (9-level) MLI using APOD-CLSPWM

Figure 1.17: FFT analysis of voltage waveform of asymmetric (9-level) cascaded MLI using APOD-

CLSPWM

Figure 1.18: Motor output of (9-level) cascaded MLI using APOD-CLSPWM

V. CONCLUSION

In this paper, the multicarrier pulse width

modulation (PWM) techniques for 7-level & 9-level have



been presented. Performance factor like total harmonic distortion (THD) of the output voltage of asymmetric cascade multi level inverter (CMLI) have been evaluated, presented and analyzed. The total harmonic distortion (THD) of the output voltage of unbalanced cascade multi level inverter (CMLI) is studied under different techniques such as IPD, POD & APOD, compare for seven and nine level multi level inverter (MLI) and less total harmonic distortion (THD) is observed for APOD techniques for 7- level and IPD techniques best for 9-level multi level inverter (MLI). Therefore, it concluded that It that the 9-level cascade multi level inverter (CMLI) provide a lower percentage total harmonic distortion (THD) as compared to 7-level multi level inverter (MLI). The harmonic distortions present in the output voltage waveforms were experiential and calculate from side to side Fast Fourier Transform (FFT) analysis tool in Matlab and simulink. In this work is it shown that the reducing the total harmonic distortion (THD) in multilevel inverter (MLI) with increasing the no voltage level and using multicarrier pulse width modulation (PWM) techniques ,the work can be expanded in following area . The proposed inverter has been operated by only three control schemes, namely IPD, POD and APOD PWM schemes. Applying the improved switching techniques can still improve the output quality. So potential of proposed version could be explored by adopting different switching techniques. The proposed version of CMI is only adopted for harmonic reduction applications. In fact the merits of CMI can be used to build for photovoltaic/grid connected systems. So it can extend to multiple applications like STATCOM, SSSC and UPQC etc.

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implementation of multicarrier based control schemes for

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