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CHAPTER 4

HARDWARE IMPLEMENTATION FOR MULTICARRIER

PWM BASED THREE PHASE MULTILEVEL INVERTER

4.1 INTRODUCTION

Availability of input and output pins in larger numbers, synthesis of

processes in series and parallel circuits, flexibility in programming make FPGA a

better choice than DSP. Therefore implementation of multicarrier PWM algorithm in

FPGA is more attractive, more user friendly and more cost effective.

From chapter 2 and chapter 3 it is understood that the single and dual

references based MCPWM achieve similar performances. Therefore hardware is

implemented for single reference based MCPWM methods.

The objective of this chapter is to develop and implement single

reference based multicarrier PWM algorithm for a three phase cascaded H-bridge

five level inverter using Xilinix software in FPGA. The multicarrier PWM algorithm

is developed using VHDL and is implemented in VPE Spartan 3A DSP board.

4.2 HARDWARE DESCRIPTION

In order to illustrate the efficiency of the designed FPGA based

multicarrier PWM algorithm, experimental work is carried out on a prototyping

platform of three phase CHB five level inverter. The test rig shown in Figure 4.1

consists of a FPGA processor, a three phase cascaded H-bridge five level inverter, a

driver circuit and an isolation circuit. Figure 4.2 displays the main circuit of the

three phase cascaded H-bridge five level inverter. The inverter topology is based on

the series connection of single phase inverters with separate DC sources. A five

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level inverter consists of two serial connected H-bridges in a phase. A single H-

bridge shown in Figure 4.3 consists of opto isolators A4506, driver IC IR2110,

bridge rectifier, DC link capacitor, RC snubber circuit and four power switches

realized by a power metal oxide semiconductor field effect transistor (MOSFET)

IRF540N. The details of IRF540N, IR2110 and A4506 are given in Appendix 2,

Appendix 3 and Appendix 4 respectively.

Figure 4.1 Test rig of three phase cascaded H-bridge five level inverter using FPGA

Figure 4.2 Main circuit of three phase CHB five level inverter

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The resulting phase voltage is synthesized by the addition of the voltages

generated by the individual single phase inverters. The rated output power of the

experimental prototype circuit is 400 VA.

Figure 4.3 Electronic circuit of a H-bridge in one leg of the cascaded H-bridge five level inverter

4.3 FEATURES OF FPGA

A Field-Programmable Gate Array (FPGA) is an integrated circuit

designed to be configured by a customer or a designer after manufacturing. The

heart of the FPGA kit is the Spartan-3A DSP-XS3D1800A-FG676 board, the details

of which are given in Appendix 1. It is processed with a maximum operating

sampling frequency of 10 KHz and a clock frequency of 20 MHz is used.

4.3.1 Architectural Overview

The XA Spartan-3A DSP family architecture shown in Figure 4.4

consists of the following fundamental programmable functional elements:

� Xtreme DSP48A Slice provides an 18-bit x 18-bit multiplier, 18-

bit pre-adder, 48-bit post-adder/accumulator and cascade

capabilities for various DSP applications.

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� Configurable Logic Blocks (CLBs) contain flexible Look-Up

Tables (LUTs) that implement logic plus storage elements used as

flip-flops or latches. CLBs perform a wide variety of logical

functions as well as store data.

� Input/output Blocks (IOBs) control the flow of data between the

I/O pins and the internal logic of the device. IOBs support

bidirectional data flow plus 3-state operation. They support a

variety of signal standards including several high performance

differential standards and Double Data Rate (DDR) registers.

� Block RAM provides data storage in the form of 18-Kb dual-port

blocks.

� Digital Clock Manager (DCM) Blocks provide self calibrating,

fully digital solutions for distributing, delaying, multiplying,

dividing and phase shifting clock signals.

� A Rich Routing network that interconnects all five functional

elements, transmitting signals among them. Each functional

element has an associated switch matrix that permits multiple

connections to the routing.

Figure 4.4 SPARTAN- 3A DSP family architecture

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A dual ring of staggered IOBs surrounds a regular array of CLBs. The

XC3SD1800A has four columns of DSP48As. Each DSP48A has an associated

block RAM. The DCMs are positioned in the center with two at the top and two at

the bottom of the device and in the two outer columns of the 4 or 5 columns of block

RAM and DSP48As.

4.3.2 Configuration

Spartan-3A DSP FPGAs are programmed by loading configuration data

into robust, reprogrammable, static CMOS configuration latches (CCLs) that

collectively control all functional elements and routing resources. The FPGA’s

configuration data is stored externally in a PROM or some other non-volatile

medium, either on or off the board. After applying power, the configuration data is

written to the FPGA using Boundary Scan (JTAG), typically downloaded from a

processor or system tester.

Figure 4.5 Spartan 3A DSP - XS3D1800A-FG676 board

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Spartan-3A DSP FPGAs support multiboot configuration, allowing two

or more FPGA configuration bit streams to be stored in a single SPI serial Flash or a

parallel NOR Flash. The FPGA application controls the type and time of

configuration loaded. Additionally, each Spartan-3A DSP FPGA contains a unique,

factory programmed device DNA identifier useful for tracking purposes, anti-

cloning designs, or IP protection.

Figure 4.5 shows the Spartan-3A DSP board which is used in the test rig

for generating gating pulses. Figure 4.6 illustrates the design flow diagram of FPGA.

Xilinx owns and maintains a complete tool set for the entire FPGA design flow

which are integrated under one umbrella called the Integrated Software Environment

(ISE) package. Simulation and testing are done using system generator, a system

level modeling tool from Xilinx [94]. This tool can be used for designing and testing

DSP systems for FPGAs in visual data flow environments such as MATLAB

Simulink. The design is synthesized using Xilinx ISE’s project navigator. ModelSim

block invokes ModelSim simulator and actually simulates the design. The

simulator’s output is fed back to Simulink for verification and the results can be

displayed using Simulink’s sinks. ModelSim behavioural synthesis tool that reads in

high level descriptions of DSP applications written in MATLAB automatically

generates synthesizable RTL models in VHDL.

FPGA configuration is generally specified using a Hardware Description

Language (HDL), which can be entered using any basic text editor. Therefore,

source code is written in VHDL to realize an electronic circuit, system or design and

is saved in a file with the extension of .vhd with the same name as its entity.

Depending on the type of design, the test-benches monitor the design

outputs by using additional logic to check the results and thereby creating automated

self checking tests. Therefore, it is necessary to visually verify and debug the signals

at all levels of hierarchy in the design on wave simulator. A company called Mentor

Graphics produces an HDL simulation and debug environment called ModelSim. If

an HDL design is purely behavioural, the simulator will most likely be able to

properly simulate the design. However, since the HDL source code may contain

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either Xilinx IP cores, or lower level macros specific to the FPGA architecture, a set

of Xilinx libraries that indicate how each of the higher level blocks should behave

must be made available to the simulator. Xilinx solves this issue by working with its

own version of ModelSim, which includes all necessary Xilinx libraries to

functionally verify any abstraction level for any Xilinx FPGA. ModelSim can be run

as a stand-alone program, or it can be executed from within ISE [98].

After testing, the process of synthesis takes place. The first step in the

synthesis process is compilation. Compilation is the conversion of the high level

VHDL language, which describes the circuit at the Register Transfer Level (RTL),

in to a net list at the gate level.

Once the net list has been completed, it needs to be functionally verified.

Functional verification tests the design to determine if it is working as intended.

First, a test bench (high level HDL stimulus file) is created that wraps around a

design to stimulate the design inputs [13].

The second step is the optimization, which is performed at the gate level

for speed or for area. Core Generator is a GUI based tool that offers a designer

parameterized logic Intellectual Property (IP) cores that have been optimized (for

area & speed) to be implemented in Xilinx FPGAs. These readymade cores offer

functions that range from simple counters, comparators, adders, multipliers, to full

system-level building blocks, such as memories, FIFOs, filters, and transforms. The

design now is simulated. After simulating the code, it is dumped into an FPGA. This

programmable logic device, after dumping, acts like a designed system. The

interconnections of these devices need to be made as per the code.

The program code which might be logic based is converted into a

physically realizable structure using a place and route software. Thus, a physical

structure is built within an FPGA. This process involves converting the VHDL code

into a format that can be understood by FPGA.

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A .bit file is generated for being downloaded into the FPGA device. The

JTAG connector is interfaced to download the program as .bit file in boundary scan

mode. Then the design is implemented, a programming file is generated and the

target device is configured. As shown in Figure 4.7, the FPGA kit generates 12

positive and 12 negative gating signals required for triggering the switches of three

phase cascaded five level inverter. A dead time of 3 µs is inserted between the

complementary switches. The Electronic Design Automation (EDA) tool Xilinx ISE

suite combined with ModelSim is used for synthesis, implementation and simulation

using VHDL.

Figure 4.6 FPGA design flow diagram for generation of pulses

During the full compilation of the project for five level inverter,

including PWM modulator with dead time, only 2360 logic elements (14%) are used

out of 16,640 of logic resources available in FPGA. Thus a cost effective

implementation of PWM algorithm is accomplished which can be understood from

Figure 4.8.

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Figure 4.7 Block diagram of PWM generation developed for a single phase in FPGA

Figure 4.8 Compilation results of PWM algorithm in XS3D1800A-FG676

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4.4 EXPERIMENTAL RESULTS AND DISCUSSION

The main focus of this section is to develop MCPWM technique using VHDL and to analyze the performance of three phase cascaded H-bridge multilevel inverter under different modulation indices.

For the experimental verification of the designed MCPWM control strategy, a prototype of three phase FPGA (XS3D1800A-FG676) controlled cascaded H-bridge five level is constructed with IRF 540 N MOSFET and tested. Aseries connection of resistor and inductor (RL load) is used as a load device in which R = 100Ohms and L = 55mH.

The experimental investigation is conducted for different multicarrier PWM techniques. For three phase cascaded five level inverter shown in Figure. 4.1, gating pulses are generated by comparing a sinusoid with the four carrier signals which are arranged in a level shifted or phase shifted fashion.

4.4.1 Phase Disposition Pulse Width Modulation

The designed inverter is practically implemented using FPGA and the performance of three phase cascaded multilevel inverter is analyzed.

The phase disposition PWM method, as one of the carrier based PWM methods, is based on a comparison of a sinusoidal reference waveform, with vertical shifted carriers. As it can be seen from Figure 4.11, the carrier signals have the same frequency of fc (3150Hz), same amplitude Ac and are in phase. The sinusoidal modulating signal has a frequency of fr (50Hz) and amplitude Ar. Figure 4.11 shows the carriers along with modulating sine wave and the resulting PWM signals which directly yield the gating signals for the MOSFETs.

After suitably scaling down the simulation values, in view of laboratory constraints, the peak output voltage obtained experimentally is 40V. Figure 4.9 shows the three-phase output voltage obtained for PD PWM method for a ma = 0.9 and mf = 63 and it is seen that cascaded H-bridge five level inverter provides an RMS voltage of 24.667V. Also Figure 4.9 and Figure 4.12 depict that the significant harmonic is concentrated at carrier frequency (mf = 63) and harmonic energies are

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concentrated as sidebands around the carrier frequency. Figure 4.10 provides the harmonic details of phase voltage obtained for single reference based PD PWM at ma = 0.9 and mf = 63 which illustrates that the output voltage has a total harmonic distortion of 4.899%.

Figure 4.9 Five level cascaded H-bridge inverter phase voltage with single reference based PD PWM (ma = 0.9, mf = 63)

Figure 4.10 Harmonic details of phase voltage with single reference based PD PWM (ma = 0.9, mf = 63)

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Figure 4.11 Multicarrier arrangement and pulse generation for PD technique

Figure 4.12 Phase voltage harmonic spectrum with single reference based PD PWM (ma = 0.9, mf = 63)

4.4.2 Alternative Phase Opposition Pulse Width Modulation

In case of APOD modulation, every carrier waveform is out of phase

with its neighboring carrier by 180ο. Figure 4.15 shows the resulting carrier

waveform and the pulse generated for ma = 0.9, mf = 63. Figure 4.13 displays the

phase voltage waveform under single reference based APOD PWM at ma = 0.9, mf =

63. It can also be seen from the Figures 4.13 and Figure 4.14 that the output

produces a fundamental RMS voltage 24.667 with the %THD 5.095.

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Figure 4.13 Five level cascaded H-bridge inverter phase voltage with single reference based APOD PWM (ma=0.9, mf=63)

Figure 4.14 Harmonic details of phase voltage with single reference based APOD PWM (ma = 0.9, mf = 63)

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Figure 4.15 Multicarrier arrangement and pulse generation for APOD technique

Figure 4.16 Phase voltage harmonic spectrum with single reference based APOD PWM (ma = 0.9, mf = 63)

For mf = 63, in APOD strategy the most significant harmonics are

sidebands centered around the carrier frequency fc = 3150, with no harmonics

occurring at fc which is depicted by Figure 4.13 and Figure 4.16.

4.4.3 Phase Opposition Disposition Pulse Width Modulation

With the POD method, the carrier waveforms above the zero reference

value are in phase. The carriers below reference are in phase but are 180ο phase

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shifted from those above zero as shown in Figure 4.19. An example of the inverter

phase output voltage waveform for ma = 0.9, mf = 63 is given in Figure 4.17. Figure

4.17 and Figure 4.20 show that the significant harmonics are located in two side

bands around the carrier frequency. Figure 4.18 illustrates that the output obtained

with POD PWM strategy yields a RMS voltage of 24.669V and has %THD 8.793%.

Figure 4.17 Five level cascaded H-bridge inverter phase voltage with single reference based POD PWM (ma = 0.9, mf = 63)

Figure 4.18 Harmonic details of phase voltage with single reference based POD PWM (ma=0.9, mf=63)

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Figure 4.19 Multicarrier arrangement and pulse generation for POD technique

Figure 4.20 Phase voltage harmonic spectrum with single reference based POD PWM (ma = 0.9, mf = 63)

4.4.4 Phase Shifted Pulse Width Modulation

The phase shifted multicarrier PWM uses four carrier signals of the same

amplitude and frequency (shown in Figure 4.23) which are phase shifted by 90ο to

one another to generate the five level inverter output voltage shown in Figure 4.21.

The figure also depicts that the experimental output produces a voltage having an

RMS value of 24.427 V and %THD 2.820%. Figure 4.21, Figure 4.22 and

Figure 4.24 give harmonic profile of the output voltage generated under PS PWM at

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ma = 0.9, mf = 63 These figures show that the harmonic energy is concentrated as

sidebands around (m-1) mf . The significant harmonic energy is at [(m-1) mf -1] and

at [(m-1) mf +1]. For mf = 63, the significant harmonic energy at 251 and at 253 are

10.267% and 9.479%.

Figure 4.21 Five level cascaded H-bridge inverter phase voltage with single reference based PS PWM (ma = 0.9, mf = 63)

Figure 4.22 Harmonic details of phase voltage with single reference based PS PWM (ma = 0.9, mf = 63)

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Figure 4.23 Multicarrier arrangement and pulse generation for PS technique

Figure 4.24 Phase voltage harmonic spectrum with single reference based PS PWM (ma = 0.9, mf = 63)

4.4.5 Hybrid Pulse Width Modulation

Figure 4.27 shows the set of carriers which generate the gating signal for

MOSFETs. Figure 4.25 shows the phase voltage waveform of the designed

five level inverter for ma = 0.9, mf = 63 and the associated spectrum is presented in

Figure 4.28.

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Figure 4.25 Five level cascaded H-bridge inverter phase voltage with single reference based hybrid PWM (ma=0.9, mf=63)

Figure 4.26 Harmonic details of phase voltage with single reference based hybrid PWM (ma = 0.9, mf = 63)

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It is confirmed from these figures that the significant harmonic is concentrated at

carrier frequency whose value is 17.832%. During the experimental investigation of

the harmonic performance of hybrid modulation shown in Figure 4.26, it is noticed

that the occurrence of sideband harmonics around (m-1) mf. Hybrid modulation

produces a RMS voltage of 25.045V with a total harmonic distortion of 30.842%

which can be verified from Figure 4.26.

Figure 4.27 Multicarrier arrangement and pulse generation for hybrid technique

Figure 4.28 Phase voltage harmonic spectrum with single reference based hybrid PWM (ma=0.9, mf=63)

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4.4.6 Estimation of Performance Parameters

Experimental investigation is carried out for three different values of ma

and mf (ma = 0.9, 0.8 and 0.7; mf = 63, 120 and 200) and the corresponding

performance parameters such as distortion factor, DC utilization rate, total harmonic

distortion and RMS voltage are determined from the output voltage obtained. The

calculated parameters are tabulated (Table 4.1-Table 4.4) for the analysis purpose.

A graphical analysis using various parameters is carried out to determine

the performance of the inverter. Figure 4.29-4.37 illustrate the behavior of the

inverter under different frequency and amplitude modulation indices.

Table 4.1 %THD Vs PWM strategies for single reference

mf 63 120 200ma 0.9 0.8 0.7 0.9 0.8 0.7 0.9 0.8 0.7

APOD 6.486 8.561 9.839 13.151 17.881 20.601 6.066 7.029 8.891POD 8.741 9.626 12.799 5.766 6.395 7.462 6.657 7.560 8.426

Hybrid 28.506 34.806 39.735 6.354 6.990 7.400 8.880 8.989 10.375PD 4.591 6.219 7.889 3.725 4.553 4.892 2.891 3.415 7.897PS 2.820 2.825 3.000 2.986 3.103 3.774 5.202 5.842 6.062

Table 4.2 RMS Values Vs for PWM strategies for single reference

mf 63 120 200ma 0.9 0.8 0.7 0.9 0.8 0.7 0.9 0.8 0.7

APOD 24.91 22.51 19.98 24.77 22.37 19.84 24.69 22.254 19.72POD 24.484 22.181 19.687 24.03 21.80 19.29 23.734 21.31 19.024

Hybrid 25.106 22.819 20.709 25.14 22.90 20.69 24.38 22.02 19.51PD 24.79 22.42 19.88 24.66 22.28 19.75 23.96 21.70 19.23PS 25.057 22.800 20.075 24.936 22.461 20.017 25.104 22.681 20.1324

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Table 4.3 DC Voltage Utilization Rate (DCUR) Vs PWM strategies for single reference

mf 63 120 200ma 0.9 0.8 0.7 0.9 0.8 0.7 0.9 0.8 0.7

APOD 62.275 56.275 49.95 61.925 55.925 49.6 61.725 55.64 49.3

POD 61.21 55.453 49.218 60.075 54.5 48.225 59.335 53.275 47.56

Hybrid 62.765 57.048 51.773 62.85 57.25 51.73 60.95 55.05 48.775

PD 61.975 56.05 49.7 61.65 55.7 49.375 59.90 54.25 48.075

PS 62.643 57.00 50.188 62.34 56.15 50.043 62.76 56.703 50.331

Table 4.4 Distortion factor Vs PWM strategies for single reference

mf 63 120 200ma 0.9 0.8 0.7 0.9 0.8 0.7 0.9 0.8 0.7

APOD 15.24 11.60 10.11 7.582 5.584 4.847 16.266 14.085 11.177

POD 11.37 10.33 7.789 17.088 15.45 13.282 14.855 13.11 11.785

Hybrid 3.51 2.87 2.516 15.547 14.162 13.39 11.19 11.056 9.594

PD 21.28 15.88 12.575 25.928 21.45 20.027 32.690 28.103 12.563

PS 31.87 33.37 31.622 31.756 30.67 25.613 18.878 16.872 19.38

4.4.7 Result Analysis

With the help of Table 4.1- Table 4.4, a comparative analysis between

the MCPWM is carried out through graphical representation of various performance

parameters against modulation indices. Figure 4.29 displays the comparison of total

harmonic distortion with different modulation strategies for ma = 0.9, mf = 63. It can

be noticed that phase shifted method provides lower total harmonic distortion than

other multicarrier PWM strategies. Irrespective of the modulation strategy, %THD

decreases with increase in ma, at constant mf, whereas it increases as mf increases.

The above discussed concept is clearly understood from Figure 4.30 and

Figure 4.31.

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Figure 4.29 THD Vs modulation schemes at ma = 0.9, mf = 63

Figure 4.30 THD Vs modulation schemes with constant mf = 63

Figure 4.31 THD Vs frequency modulation ratio (PS PWM) with constant ma

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Figure 4.32 DF Vs modulation schemes with constant mf = 63

Figure 4.33 DF Vs frequency modulation ratio (PS PWM) with constant ma

Investigating Figure 4.32 and Figure 4.33 reveals that the %DF is higher

for phase shifted method. It can also be noted that for other modulation strategies,

%DF increases with increase in ma. For PS PWM method, %DF decreases with

increase in mf at constant ma.

Examining Figure 4.34 and Figure 4.35, it is clearly understood that as

ma increases, the RMS voltage obtained at the output of the inverter increases,

remains constant for any changes in the mf for constant ma. Thus the role of mf is

negligible in obtaining the fundamental output voltage.

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Figure 4.34 RMS output voltage (PS PWM) Vs amplitude modulation ratio at constant mf

Figure 4.35 RMS output voltage (PS PWM) Vs frequency modulation ratio at constant ma

Figure 4.36 DCUR of PS technique Vs amplitude modulation ratio (mf = constant)

As Figure 4.36 and Figure 4.37 depict %DCUR is improved as amplitude

modulation depth increases and it remains unchanged for any changes in mf.

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Figure 4.37 DCUR of PS technique Vs frequency modulation ratio (ma = constant)

4.5 SUMMARY

From the experimental investigation, several distinct features of the three

phase CHB five level with different MCPWM schemes are identified. The phase

voltage is able to synthesize more levels resembling a more desirable sinusoidal

waveform. Besides that, the phase voltage yields better spectral performance, thus

reducing the need of an output filter. The three phase CHB inverter with PS PWM is

also able to produce phase voltages with higher fundamental with much lower

harmonic distortion as compared to other MCPWM methods.

From the analysis, it can be concluded that there is no particular benefit

in output due to variations of mf. The experimental results suggest that the three-

phase CHB inverter is most suitable to operate at a higher ma not exceeding one and

also at high mf. Higher ma promises a higher fundamental output voltage and lower

significant harmonics. On the other hand, a higher mf ensures that the distance

between the fundamental component and the first significant harmonic is greater,

thus easing the filtering process.

From the investigation, it is clearly seen that the experimental results

verify the validity of the simulated results obtained using MATLAB / SIMULINK.