hcs12 technical training module 14-nvm, slide 1 motorola and the stylized m logo are registered in...

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  • Slide 1
  • HCS12 Technical Training Module 14-NVM, Slide 1 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001. NVM Flash & EEPROM Module
  • Slide 2
  • HCS12 Technical Training Module 14-NVM, Slide 2 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001. System Memory Internal Bus SCI 1 256K FLASH EEPROM 12K SRAM ATD 1 HCS12 CPU BKP INT MMI CM BDM MEBI 4K BYTES EEPROM SIM msCAN 3 msCAN 2 msCAN 1 SCI 1 SPI 2 or PWM CH 4-7 BDLC or msCAN 0 msCAN 4 or IIC SPI 1 or PWM CH 0-3 SPI 0 ATD 0 PLL PIT ECT 8 CHAN PWM 8 CHAN
  • Slide 3
  • HCS12 Technical Training Module 14-NVM, Slide 3 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001. FLASH EEPROM 256K bytes of Flash made of four 64K byte blocks Single supply program and erase. Automated program and erase algorithm. Interrupt on command completion. All four flash blocks can be programmed and erased in parallel. Read-While-Write into different block. Fast sector erase and word program operation. Flexible protection scheme against accidental program or erase. Security feature to prevent intrusive access.
  • Slide 4
  • HCS12 Technical Training Module 14-NVM, Slide 4 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001. Memory Map & Flash Control Vectors 4K EEPROM Registers 12K RAM 16K Flash (Fixed) 16Kx16 Flash Pages (Windowed) 16K Flash (Fixed) $0000 $0400 $1000 $4000 $8000 $C000 $FF00 $FFFF Page $30 Page $31 Page $3F Page $3E Page $3F Flash Control Registers $0100 $010F Flash Protect Low Area.5K, 1K, 2K, 4K Flash Protect High Area 2K, 4K, 8K, 16K Page $3E $30 - $3F Denotes contents of PPAGE Register Flash Protect High Area Address Description $FF00 -$FFF7 Backdoor comparison key $FF08-$FF09 Reserved $FF0A Flash block 3 protection $FF0BFlash block 2 protection $FF0CFlash block 1 protection $FF0DFlash block 0 protection $FF0E Reserved $FF0F Security Byte Flash 0 Protection/Security Fields
  • Slide 5
  • HCS12 Technical Training Module 14-NVM, Slide 5 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001. Flash Control Registers All four Flash Blocks Occupy 16 Bytes In The I/O Register Area. Registers Are Divided Into Banked and Unbanked Banked Registers Are Selected With BLKSEL1: BLKSEL0 In FCNFG Unbanked Registers Control State Machine Clock, Security, Interrupts Banked Registers Control Erasure, Programming, Protection Banked Registers Allow Erasure and Programming All Four Blocks in Parallel
  • Slide 6
  • HCS12 Technical Training Module 14-NVM, Slide 6 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001. Flash Clock Divider Register FLCKDIV - Flash Clock Divider Register Address Offset $0000 FDIVLD Flash Clock Divider Loaded This bit is set when the FCLKDIV register is written to. An attempt to program or erase the flash without having written to this register previously will result in an access error and the command will not be executed. 1 = Register has been written to since the last reset. 0 = Register has not been written to. PRDIV8 Enable Prescaler by 8 1 = Enables a prescaler by 8 before feeding into the FCLKDIV divider. 0 = OSCCLK is directly fed into the FCLKDIV divider FDIV[5:0] Flash Clock Divider The combination of FDIV8 and FDIV[5:0] is used to divide the oscillator clock down to a frequency of 150KHz - 200KHz. This resulting clock, FCLK, is used to drive the program and erase state machines for the flash. For frequencies of OSCCLK > 12.8MHz the Prescaler bit PRDIV8 must be set on. FCLKDIV Settings
  • Slide 7
  • HCS12 Technical Training Module 14-NVM, Slide 7 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001. Flash Security Memory Security Mechanism Prevents Unauthorized Access To Flash and EEPROM. Prevents Access via BDM or Expanded Bus Unless Flash and EEPROM Are Erased. Security Is Controlled By The Two LSBs of The FSEC Register. These Bits Are Loaded From Flash Location $FF0F. Two Bits of Opposite Polarity Are Used To Prevent Security Mechanism From Being Tricked. Security Mechanism Can Be Temporarily Disabled, But It Requires Firmware Support In The Target Application. 64-bit Access Key Ensures That Security Mechanism Can Not Be Easily Disabled By A Hacker.
  • Slide 8
  • HCS12 Technical Training Module 14-NVM, Slide 8 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001. Flash Security Control FSEC - Flash Security Register Address Offset $x001 This register is loaded from flash address $FF0F during the reset sequence, indicated by F in the reset row of the register description. KEYEN Enable backdoor key to security 1 = Backdoor to flash read via BDM or external bus interface is enabled 0 = Backdoor to flash read via BDM or external bus interface is disabled. When KEYEN is set, the user can then bypass the security by: 1. Setting the KEYACC bit in the configuration (FCNFG) register. 2. Writing the correct four 16 bit words to the flash using the backdoor comparison keys addresses. 3. Clear the KEYACC bit. 4. If all four 16bit words match the flash content, the MCU is unsecured by forcing the bits SEC[1:0] to the unsecured state. 5. If any of the four 16bit words does not match the flash content the MCU remains secured and a security violation signal is sent to the CPU. NV[6:2] = Non-Volatile Flags These Non-Volatile Flags are available to the user
  • Slide 9
  • HCS12 Technical Training Module 14-NVM, Slide 9 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001. Flash Configuration FCNFG - Flash Configuration Register Address Offset $0003 This unbanked register enables the interrupts, gates the security backdoor writes and selects the register bank to be operated on. CBEIE Command Buffers Empty Interrupt Enable This bit enables the interrupts in case of empty address, data and command buffers. 1 = An interrupt will be requested whenever the CBEIF flag is set 0 = Command Buffers Empty Interrupts disabled CCIE Command Complete Interrupt Enable This bit enables the interrupts in case of all commands being completed. 1 = An interrupt will be requested whenever the CCIF flag is set 0 = Command Complete Interrupts disabled KEYACC Enable Security Key Writing 1 = Writes to flash module are interpreted as keys to open the backdoor. 0 = Flash writes are interpreted as the start of a program or erase sequence. BKSEL[1:0] Register bank select These two bits are used to select which of the four register banks are addressed. The register bank associated with Flash 0 is the default out of reset. 00 = Bank 0 01 = Bank 1 10 = Bank 2 11 = Bank 3
  • Slide 10
  • HCS12 Technical Training Module 14-NVM, Slide 10 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001. Flash Protection FPROT - Flash Protection Register Address Offset $0004 This register determines whether a whole block or subsections of a block are protected against accidental program or erase. Each flash block can have two protected areas, one starting from relative address $8000 (called lower) towards higher addresses and the other growing downwards from $FFFF (called higher). FPOPEN Opens the flash block or subsections of it for program or erase. 1 = The flash block or subsections are enabled to program or erase. 0 = The whole flash block is protected. FPHDIS Flash Protection Higher address range disable This bit determines whether there is a protected area at the higher end of the flash block address map. 1 = Protection disabled 0 = Protection enabled FPHS[1:0] Flash Protection Higher address size. These bits determine the size of the protected area. FPLDIS Flash Protection Lower address range disable This bit determines whether there is a protected area at the lower end of the flash block address map. 1 = Protection disabled 0 = Protection enabled FPLS[1:0] Flash Protection Lower Address size These 2 bits determine the size of the protected area. Note: F indicates that registers are loaded from Flash control area as follows:. $FF0D --> Block 0, $FF0C --> Block 1, $FF0B --> Block 2, $FF0A --> Block 3
  • Slide 11
  • HCS12 Technical Training Module 14-NVM, Slide 11 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001. Higher Address Range Protection
  • Slide 12
  • HCS12 Technical Training Module 14-NVM, Slide 12 MOTOROLA and the Stylized M Logo are regis