Gumstixr Zircon Computer-on-Module

System Reference Manual

Version 1.0

Revised April 4, 2018

Gumstix, Inc. shall have no liability of any kind, express or implied, arising out of the use of the information in thisdocument, including direct, indirect, special or consequential damages.

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© Copyright 2017, Gumstixr, Inc. All Rights Reserved.

Gumstixr Zircon Computer-on-Module

System Reference Manual

Version 1.0

Gumstix, Inc.© 2017

April 4, 2018

Contents

1 Product Overview 1

2 Internal Signals 2

3 External Signals 33.1 general purpose I/Os (GPIOs) and pulse width modulations (PWMs) . . . . . . . . . . . . . . . . . . . . 33.2 Ethernet and Audio CODEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33.3 eMMC/µSDHC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43.4 Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43.5 High Speed Differential Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63.6 Clocks and Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4 Physical Design 8

5 Expansion Board Design Considerations 95.1 Intel Joule Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5.1.1 HDMI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95.1.2 MIPI DSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5.2 Internal and On-Board Pull-Up and Pull-Down Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . 95.3 Startup Pin Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Appendices 12

A J6 Header Signals by Pin 12

B J7 Header Signals by Pin 13

C JCAM1 Header Signals by Pin 14

List of Figures

1 Zircon COM Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Gumstix Zircon Mechanical Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

List of Tables

1 List of Internal Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 GPIO Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Ethernet and Audio Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 micro-SD High Capacity (µSDHC) signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Serial Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 High Speed Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 J6 Header Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 J6 Header Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 J7 Header Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 J7 Header Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1410 JCAM1 Header Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1 Product Overview

The Zircon Computer-on-Module (COM) is comprised of an Arm Cortex-A9-based NXPr-Semiconductor SCM-i.MX™ 6QuadSingle Chip Module (SCM), A TIr WiLink8™ WiFi/Bluetooth 4.0 module, 16GB Embedded Multimedia Card (eMMC)storage and USB 3.1 over PCI-Express (PCIe) controller, including USB Type-C.

Its mechanical configuration adheres to that of the discontinued Intelr Joule™ module and is pin-compatible withboards designed for it. Figure 1 provides a general overview of the Zircon’s on-board components and exposed buses. Inaddition to the features outlined in the image J6 and J7 also provide several general purpose I/O (GPIO), pulse widthmodulation (PWM) and analog to digital converter (ADC) pins.

Figure 1: Zircon COM Functional Block Diagram

1

2 Internal Signals

The Zircon makes use of several interfaces provided by the SCM, as is indicated by Figure 1. Table 1 specifies the signalsas defined by the SCM-i.MX 6Quad datasheet1. The behavior of these signals must be left unchanged in order for theCOM to function properly.

Table 1: List of Internal Signals

Bus Ball SignaleMMC

SD4

U15 SD4_RESETP9 SD4_CLKN9 SD4_CMDN8 SD4_DATA0P8 SD4_DATA1N7 SD4_DATA2P7 SD4_DATA3N6 SD4_DATA4P6 SD4_DATA5N5 SD4_DATA6P5 SD4_DATA7

WiFi and Bluetooth Module

UART 2

AC17 UART2_RTSAC17 SD3_CMD UART2_CTSY17 SD3_DAT4 UART2_RXY18 SD3_DAT5 UART2_TX

SD 1AE14 SD1_CLKAD14 SD1_CMDAE16 SD1_DATA0AD16 SD1_DATA1AE15 SD1_DATA2AD15 SD1_DATA3

WLAN_EN P16 GPIO1_IO19

WLAN_IRQ D11 GPIO1_IO25

BT_EN R16 GPIO1_IO17

BT_TXD E18 GPIO5_IO23

BT_TXFS F17 GPIO5_IO24

BT_RXD F18 GPIO5_IO25USB 3.1 Via PCIe

PCIe

Y20 PCIE_RXMY19 PCIE_RXP

AA19 PCIE_TXMAA20 PCIE_TXP

USB Type-C ControllerUSB_OTG_ID C11 USB_OTG_ID

1https://www.nxp.com/docs/en/data-sheet/SCMIMX6DQIEC.pdf

2

3 External Signals

The two 100-pin headers that connect the Zircon COM to expansion boards provide a large number of signals, manyof which can be multiplexed in a variety of configurations. The pin assignments listed here are based on the Gumstixdefault pinmux configuration. For a full listing of multiplexing modes consult the i.MX 6Quad Technical ReferenceManual (TRM)2.

The tables listed in this section include the bus signal name, ball number and header pin for each exposed bus.

3.1 GPIOs and PWMs

Table 2 lists all of the general-purpose signals available on J6 and J7. Two of these pins are pre-configured to bePWMs.

Table 2: GPIO Signals

Signal Ball PinGPIO1_IO25 D11 J7.56GPIO4_IO06 E12 J7.82GPIO4_IO07 E11 J7.52GPIO4_IO16 A4 J7.75GPIO4_IO28 A6 J7.58GPIO4_IO29 D7 J7.72GPIO4_IO30 C7 J7.86GPIO4_IO31 B7 J7.88GPIO5_IO05 A7 J7.71GPIO5_IO06 D8 J7.66GPIO5_IO07 C8 J7.68GPIO5_IO08 B8 J7.70GPIO5_IO11 C9 J7.62GPIO5_IO13 A9 J7.64GPIO6_IO00 K17 J6.35GPIO6_IO04 L17 J6.40GPIO6_IO05 M17 J6.67GPIO7_IO06 AB18 J6.84GPIO7_IO11 M15 J6.91GPIO7_IO13 AD12 J6.94PWM1 M16 J6.1PWM2 E15 J6.3

3.2 Ethernet and Audio CODEC

Included on the J7 header signals is an RGMIIs bus capable of providing a 10/100/1000 Gigabit Ethernet connection. TheJ6 header contains the signals for the Audio CODEC. The header pins for these buses are indicated in Table 3.

2https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf

3

Table 3: Ethernet and Audio Signals

Bus Signal Ball Pin

RGMII

RX_CTL P2 J7.50RXC P1 J7.69RD0 N1 J7.40RD1 N2 J7.38RD2 M1 J7.14RD3 M2 J7.12

TX_CTL U2 J7.98TXC U1 J7.100TD0 T1 J7.94TD1 T2 J7.92TD2 R1 J7.83TD3 R2 J7.81

Audio CODEC

CCM_CLKO1 C18 J6.71CCM_CLKO2 A19 J6.43AUD6_TXFS B3 J6.45AUD6_TXC A2 J6.39AUD6_TXD B4 J6.49AUD6_RXD A3 J6.47

3.3 eMMC/µSDHC Bus

The Zircon’s external buses include a micro-SD High Capacity (µSDHC) connection for use with Non-Volatile Memory(NVM) media such as a µSD card slot or eMMC module. The eMMC bus is located on the J6 header and Table 4provides pin-by-pin detail.

Table 4: µSDHC signals

Bus Signal Ball Pin

SD2

CMD J6.89CLK J6.75CD J6.79

DAT0 J6.81DAT1 J6.83DAT2 J6.85DAT3 J6.87

3.4 Serial Ports

Many low-speed serial ports are available to connecting boards through the headers on the underside of the Zircon COM.Table 5 provides a full pin-out of every available Serial Peripheral Interface (SPI), Controller Area Network (CAN),Inter-Integrated Circuit (I2C), and UART bus.

4

Table 5: Serial Bus Signals

Bus Signal Ball Pin

ECSPI1

SCLK D10 J6.53SS0 A10 J6.55SS1 A8 J6.14

MISO B10 J6.63MOSI C10 J6.51

ECSPI2

SCLK H3 J6.22SS0 B9 J6.27

MISO G1 J6.25MOSI H2 J6.24

ECSPI3

SCLK D5 J7.59SS0 A5 J7.77SS1 D6 J7.79SS2 C6 J7.53SS3 B6 J7.73

MISO B5 J6.25MOSI C5 J6.24

FLEXCAN1TX J16 J6.32RX L16 J6.34

I2C1SCL G18 J6.16, J6.21SDA G17 J6.18, J6.23

I2C2SCL W13 J6.57, J6.68SDA W12 J6.70, J6.95

I2C3SCL G16 J7.28, J7.43, JCAM1.9SDA H16 J7.26, J7.45, JCAM1.5

UART1

TX W18 J6.78RX W17 J6.80CTS AC18 J6.76RTS AB17 J6.74

UART3

TX T5 J6.93RX N3 J7.51CTS AA17 J7.55RTS AB16 J7.47

UART4TX J17 J6.26RX J18 J6.28CTS N16 J7.77RTS M18 J6.90

UART5TX E13 J7.15RX F14 J7.13CTS D15 J7.11RTS C15 J7.9

5

3.5 High Speed Differential Signals

High speed buses are used for High Definition (HD) cameras, high-resolution displays, and USB connections. Table 6describes the header pins for each set of differential pairs as well as their accompanying control signals.

Table 6: High Speed Signals

Bus Signal Ball Pin

HDMI

CLK_N K19 J6.46CLK_P K20 J6.44D0_N J20 J6.62D0_P J19 J6.64D1_N G19 J6.58D1_P G20 J6.56D2_N F19 J6.50D2_P F20 J6.52HPD K18 J6.65

USB0

DN AC19 J6.8DP AC20 J6.6

OTG_ID C11 J6.20CC1 J6.59CC2 J6.61

SSTX_N J7.6SSTX_P J7.4SSRX_N J7.48SSRX_P J7.44

USBC_SEL J7.18

USB1

DN J7.65DP J7.63

SSTX_N J7.89SSTX_P J7.87SSRX_N J7.97SSRX_P J7.95

CSI-2

CLK_N N20 JCAM1.14CLK_P N19 JCAM1.18D0_N R20 JCAM1.6D0_P R19 JCAM1.10D1_N P19 JCAM1.22D1_P P20 JCAM1.23RST1 A12 JCAM1.11RST2 A11 JCAM1.4

PWRDN B12 JCAM1.15CLK_24M JCAM1.24

DSI

CLK_N J7.27CLK_P J7.25D0_N J7.19D0_P J7.21D1_N J7.31D1_P J1.33

6

3.6 Clocks and Control Signals

In addition to the GPIOs and buses available from the Zircon COM, dedicated control and clock pins are provided. Table7 highlights these pins.

Table 7: Control Signals

Bus Ball PinONOFF AD13 J6.9LICELL Y11 J6.11RESET AE12 j6.13PWRGOOD J6.33CLK_32K J7.7CLK_24M JCAM1.21

7

4 Physical Design

The Zircon COM connects to compatible expansion boards via two 0.4mm-pitch 100-pin Hirose connectors, labeled asJ6 and J7. JCAM1, located at the western edge of the board mates with the KaiLapTechr KLT-OV5640-V4320 V4.0.Figure 2 provides detailed measurements of the COM’s physical features.

Figure 2: Gumstix Zircon Mechanical Diagram

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5 Expansion Board Design Considerations

Expansion boards for the Gumstixr Zircon COM can be designed and purchased through Gumstixr’s online board designsuite, Geppetto™ D2O

5.1 Intel Joule Compatibility

The Zircon COM has been designed to implement the hardware interface initially provided by the Intelr Joule™ modulewith several added or modified behaviours, signals, or mechanical properties.

5.1.1 HDMI Signals

The HDMI lanes from the Zircon differ from those of the Intel Joule in that they do not require decoupling capacitors.Beyond Electrostatic Discharge (ESD) protection, no components are required on the differential pairs.

5.1.2 MIPI DSI

The Zircon’s MIPI Display Serial Interface (DSI) interface provides only 2 data lanes, compared to the 4 lanes providedby the Intel Joule module.

5.2 Internal and On-Board Pull-Up and Pull-Down Resistors

Some signals require pull-up resistors in order to operate their associated devices correctly. The SCM-i.MX 6Quad’sSystem-on-Chip (SoC) includes programmable pull-up / -down resistors for many of its GPIOs. Also, some on-boardresistors are present where devices are particularly sensitive to signal impedance.

5.3 Startup Pin Protection

In order to protect certain pins on device startup, the PWRGOOD signal can be used to control the activation of peripheralIntegrated Circuits (ICs).

9

List of Acronyms

COM Computer-on-Module

SoC System-on-Chip

SCM Single Chip Module

eMMC Embedded Multimedia Card

PCIe PCI-Express

GPIO general purpose I/O

PWM pulse width modulation

ADC analog to digital converter

TRM Technical Reference Manual

SPI Serial Peripheral Interface

UART Universsal Asynchronous Reciever-Transmitter

I2C Inter-Integrated Circuit

CAN Controller Area Network

RGMII Reduced Gigabit Machine Independent Interface

HD High Definition

USB Universal Serial Bus

CODEC Encoder/Deoder

µSDHC micro-SD High Capacity

NVM Non-Volatile Memory

IC Integrated Circuit

ESD Electrostatic Discharge

HDMI High Definition Media Interface

DSI Display Serial Interface

MIPI Mobile Industry Processor Interface

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External Links

https://geppetto.gumstix.com, 9https://www.nxp.com/docs/en/data-sheet/SCMIMX6DQIEC.pdf, 2https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf, 3

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Appendices

Appendix A J6 Header Signals by Pin

Table 8: J6 Header Pins

Signal Pin SignalPWM1 1 2 VSYSPWM2 3 4 GNDVSYS 5 6 USB0_PVSYS 7 8 USB0_NONOFF 9 10 GNDVRTC 11 12 VSYSRESET 13 14 ECSPI1_SS1VSYS 15 16 I2C1_SCLVSYS 17 18 I2C1_SDAGND 19 20 USB0_OTG_IDI2C1_SCL 21 22 ECSPI2_SCLKI2C1_SDA 23 24 ECSPI2_MOSIECSPI1_MISO 25 26 UART4_RXECSPI2_SS0 27 28 UART4_TXENET_MDC 29 30 VCC_3V3ENET_REF_CLK 31 32 FLEXCAN1_TXPWRGOOD 33 34 FLEXCAN1_RXGPIO6_IO01 35 36 VCC_1V8VDC_IN 37 38 ENET_MDIOAUD6_TXC 39 40 GPIO6_IO04NC 41 42 GNDCCM_CLKO2 43 44 HDMI_CLK_PAUD6_TXFS 45 46 HDMI_CLK_NAUD6_RXD 47 48 GNDAUD6_TXD 49 50 HDMI_D2_NECSPI1_MOSI 51 52 HDMI_D2_PECSPI1_SCLK 53 54 GNDECSPI1_SS0 55 56 HDMI_D1_PI2C2_SCL 57 58 HDMI_D1_NUSB0_CC1 59 60 GNDUSB0_CC2 61 62 HDMI_D0_NECSPI1_MISO 63 64 HDMI_D0_PHDMI_HPD 65 66 GNDGPOIO6_IO05 67 68 I2C2_SCLOTG_EN 69 70 I2C2_SDACCM_CLKO1 71 72 GNDGND 73 74 UART1_RTSSD2_CLK 75 76 UART1_CTSUART4_CTS 77 78 UART1_TX

12

Table 8: J6 Header Pins

Signal Pin SignalSD2_CD 79 80 UART1_RXSD2_DAT0 81 82 GNDSD2_DAT1 83 84 GPIO7_IO06SD2_DAT2 85 86 GNDSD2_DAT3 87 88 SD2_VSELECTSD2_CMD 89 90 UART4_RTSGPIO7_IO11 91 92 NCUART3_TX 93 94 GPIO7_IO13I2C2_SDA 95 96 GNDNC 97 98 GNDVBUS_SENSE 99 100 GND

Appendix B J7 Header Signals by Pin

Table 9: J7 Header Pins

Signal Pin SignalVSYS 1 2 GNDVSYS 3 4 USB0_SSTX_PGND 5 6 USB0_SSTX_NCLK_32K 7 8 GNDUART5_RTS 9 10 GNDUART5_CTS 11 12 RGMII_RD3UART5_RX 13 14 RGMII_RD2UART5_TX 15 16 GNDGND 17 18 USBC_SELDSI_D0_N 19 20 VSYSDSI_D0_P 21 22 VSYSGND 23 24 GNDDSI_CLK_P 25 26 I2C3_SDADSI_CLK_N 27 28 I2C3_SCLGND 29 30 GNDDSI_D1_N 31 32 VSYSDSI_D1_P 33 34 VSYSGND 35 36 GNDNC 37 38 RGMII_RD1NC 39 40 RGMII_RD0GND 41 42 GNDI2C3_SCL 43 44 USB0_SSRX_NI2C3_SDA 45 46 USB0_SSRX_PUART3_RTS 47 48 GNDECSPI3_MISO 49 50 RGMII_RX_CTLUART3_RX 51 52 RGMII_RX_CTLECSPI3_SS2 53 54 GPIO4_IO07

13

Table 9: J7 Header Pins

Signal Pin SignalUART3_CTS 55 56 GNDECSPI3_MOSI 57 58 GPIO1_IO25ECSPI3_SCLK 59 60 GPIO4_IO28GND 61 62 GPIO5_IO11USB1_P 63 64 GPIO5_IO13USB1_N 65 66 GPIO5_IO06GND 67 68 GPIO5_IO07RGMII_RXC 69 70 GPIO5_IO08GPIO5_IO05 71 72 GPIO4_IO29ECSPI3_SS3 73 74 GNDGPIO4_IO16 75 76 NCECSPI3_SS0 77 78 NCECSPI3_SS1 79 80 GNDRGMII_TD3 81 82 GPIO4_IO06RGMII_TD2 83 84 GNDGND 85 86 GPIO4_IO30USB1_SSTX_P 87 88 GPIO4_31USB1_SSTX_N 89 90 GNDGND 91 92 RGMII_TD1GND 93 94 RGMII_TD0USB1_SSRX_P 95 96 GNDUSB1_SSRX_N 97 98 RGMII_TX_CTLGND 99 100 RGMII_TXC

Appendix C JCAM1 Header Signals by Pin

Table 10: JCAM1 Header Pins

Signal Pin SignalVCC_2v8 1 2 AF_GNDGND 3 4 JCAM_RST2I2C3_SDA 5 6 CSI_D0_NVCC_2v8 7 8 GNDI2C3_SCL 9 10 CSI_D0_PJCAM_RST1 11 12 GNDGND 13 14 CSI_CLK_NPWRDN 15 16 GNDGND 17 18 CSI_CLK_PDVDD 19 20 AGNDVCC_1V8 21 22 CSI_D1_NCSI_D1_P 23 24 REF_CLK_24M

14