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John van Tol

May 21st, 2019 - Eindhoven

From High-Level Algorithms to ASML Automated Digital Design Flows

Competence Leader Embedded Logic and Firmware (ELF) Development

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11-03-2019

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Key Takeaways

1. ASML business drivers: Quality and Time-to-Market, require an efficient workflow for getting smart algorithms into high speed digital hardware (FPGAs)

2. Adoption of Model-Based Design into the ASML Digital Design Flow achieves this with automatic generation of HDL source code and test bench code

3. Model-Based Design reduces the gap between system architect and design engineer

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Chips are everywhere!In 2015, 230 billion ICs were made, 30 for every man, woman and child on the planet

Data: WSTS

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IC units, in billions

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We develop and build lithography systems for manufacturing those IC’s

150 tons of precision equipmentPublic

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works with single nano-meter precision: Grass grows at a speed of 33 nano-meter per second

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2018

1000 $, 512 MB + GB flash, 200 g,< 1W

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Moore’s Law means doing “More with Less”

Cray Super Computer

1976

30M$, 8 Mb, 5500 kg, 150 kW

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The industry is driven by Moore’s law, which continues, through ideas and value creation

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le S

yste

m P

erf

orm

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ce

/Wa

tt

2008 2018 2028

>2X/2.4 years

2X/2.4 years

¹Lisa Su, AMD, “Immersive era in consumer computing”, IEDM, dec 2017

²Gordon Moore, “Progress in digital integrated Electronics” International; Electronic Device Meeting,, IEEE, 1975, p p 11-13

ASML Market Research

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This is what we’re doing it for!

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Our systems enable the faster, better, cheaper chips of tomorrow

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1984 1987 1990 1993 1996 1999 2002 2005 2008 2011 2014 2017 2020 2023TBD

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NXE:3400B

Res. 13nm

300mm 125wph NXT:1950i

Res 38nm,

300mm 190wph

XT:1400

Resolution 65nm

300mm 145wph

High NA EUV

Res. <8nm

300mm 185wph

AT:850

Res. 110nm

300mm 102wph

PAS 5500/60

Res. 450nm

200mm 48wph

PAS 2500/10

Res. 900nm,

150mm 66wph

Source: ASML Product specs, Market Research

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ASML makes the machines for making IC’s2018-07-25

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Electronic Development within D&E ASML2018-07-25

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EDEV Wilton USA

EDEV San DiegoUSA

EDEV VeldhovenThe Netherland

Embedded

Logic

Firmware

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Goals and Challenges

27-11-2018

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Challenges

Algorithm

complexity

Performance

need

Algorithms in

Software

Algorithms in

Embedded Hardware

(FPGA)

Trend

Implementation

complexity

Increased

performance

Need:

High level design

and implementation

workflow for FPGAs

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Goals

1. One ASML common method of developing algorithms in FPGAs

2. Make modeling, simulation and code generation accessible for ELF engineer

3. Reduce the gap between system architect and ELF engineer

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How we do it

27-11-2018

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ASML ELF Way-of-Working (WoW)

HDL3rd

party

IP

GDBSimulink

HDL

Integration

GDB = Generic Design Block, HDL = Hardware Description Language

Integration

Verification

Minimal impact on

existing WoW

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ASML ELF Way-of-Working, elaborated

SimulinkSimulation Model

GenerateRTL Code

Generate Verification

Items

Generate Block

Level TB

Block Level Simulation

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ASML workflow to create algorithm subsystem, an example

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Automated Build and Test

1. Buildfiles are used to automate the various tasks involved in the FPGA design flow

2. The “Build process” makes extensive use of (GNU) Make

DesignCompilation

and Simulation

System generation

(PlatformDesigner, XPS, Vivado)

Synthesis and place and route

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Achievements and Outlook

27-11-2018

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Using HDL Coder in ELF projects

• Established workflow within the entire ASML organization. • IT team (IT4E) maintains development software and Linux servers for any ELF project• Standard use of HDL Code Generation in ELF Design Flow (DDM2/Buildfiles) • Integrated with workflow for communication protocols (GDB), integration tool (QSYS/Platform

designer/Vivado Block design), hardware interfaces (VHDL)

• Improved development of Digital Signal Processing (DSP) functions (vs. handwritten RTL and/or Testbench)

• Easier to make changes in a late stage of the project without compromising quality• Especially suited for complex DSP functions

• Future work: automatic FPGA-In-the-Loop (FIL)

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Key Takeaways

1. ASML business drivers: Quality and Time-to-Market, require an efficient workflow for getting smart algorithms into high speed digital hardware (FPGAs)

2. Adoption of Model-Based Design into the ASML Digital Design Flow achieves this with automatic generation of HDL source code and test bench code

3. Model-Based Design reduces the gap between system architect and design engineer

Public