ese 570: digital integrated circuits and vlsi …ese570/spring2019/handouts/...gate layout algorithm...

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

Lec 16: March 19, 2019 Euler Paths and Energy Basics &

Optimization

Penn ESE 570 Spring 2019 – Khanna

Lecture Outline

!  Pass Transistor Logic !  Logic Comparison !  Transmission Gates !  Euler Paths !  Energy Basics & Optimization

2 Penn ESE 570 Spring 2019 – Khanna

Pass Transistor Logic


Restore Output


Voltage of Chain

!  What is voltage at output?

5 Penn ESE 570 Spring 2019 - Khanna

Vdd=1V Vthn=-Vthp=0.3V

How compare

!  Compare


DC Analysis – chain of 3


DC Analysis – chain of 6


Conclude

!  Can chain any number of pass transistors and only drop a single Vth

9

…

Penn ESE 570 Spring 2019 - Khanna

Transient


Transient: Zoomed Closeup


Gate Cascade?

!  What are voltages?


Vdd=1V Vthn=-Vthp=0.3V

Chain Together


Cascaded Pass Gates


Delay A=1, B=0, CDB=Cdiff=Cd?

!  What’s the equivalent RC circuit?


3Cd 2Cd+2Cg

2Cg


!  What’s the equivalent RC circuit? "  What is the total delay?

"  From A to Y


3Cd 2Cd+2Cg

2Cg

17

!  What’s the equivalent RC circuit?



2Cg

Cascading Pass Gates

/b

b

/b

W=1 L=1

W=1 L=1

/c

c

/c

/d

d

/d

y

/y

W=1 L=1

W=1 L=1

W=1 L=1

W=1 L=1

A

one stage

W=1 L=1

W=1 L=1

Penn ESE 3570 Spring 2019 - Khanna 18

!  Extract key path

19

Chain without Inverters


/a

a

Logic Types

!  CMOS Gates "  Dual pull-down and pull-up networks, only one enabled at a time "  Performance of gate is strong function of the fanin of gate

"  Techniques to improve performance include sizing, input reordering, and buffering (staging)

!  Ratioed Gates "  Have active pull-down (-up) network connected to load device "  Reduced gate complexity at expense of static power asymmetric transfer

function "  Techniques to improve performance include sizing to improve noise margins and reduce

static power

!  Pass Gates "  Implement logic gate as switch network for reduced area and load

capacitance "  Long cascades of switches result in quadratic increase in delay "  Also suffer from reduced noise margins (VT drop)

"  Use level-restoring buffers to improve noise margins

!  Dynamic logic … coming up soon 20 Penn ESE 570 Spring 2019 – Khanna

Transmission Gates


CMOS Transmission Gates

22

Kenneth R. Laker, University of Pennsylvania,

updated 26Feb15


CLK

CLK


23


updated 26Feb15



24


updated 26Feb15

at t = 0-: Vin = 0, Vout = 0 at t = 0+: Vin = 0 -> VDD

Note



25


updated 26Feb15


Note

- VTp

≥ ≥

≤



26


updated 26Feb15


Note

- VTp

≥ ≥

≤



27


updated 26Feb15


Note

- VTp

≥ ≥

≤



28 - VTp

≥ ≥

≤


Transmission Gate, Req

29

kp (- VDD - VTp)2

kp [2(- VDD - Vtp) (Vout – VDD) - (Vout – VDD)2]

kp [2(- VDD - Vtp) - (Vout – VDD)]

kp [2(- VDD - Vtp) (Vout – VDD) - (Vout – VDD)2]

kp [2(- VDD - Vtp) - (Vout – VDD)]


30


updated 26Feb15



31


updated 26Feb15



Transmission Gate Layouts

32


updated 26Feb15


Transmission Gate Layouts

33


updated 26Feb15


Euler Paths


NOR2 Layout

35


updated 26Feb15


NAND2 Layout


Layout of Complex CMOS Gate

37


updated 26Feb15

DS DSGND



38


updated 26Feb15


39


updated 26Feb15

d

d d

d

d

i.e. n, p Euler paths with identical sequences of inputs

diffusion breaks



Minimize Number of Diffusion Paths

40


updated 26Feb15



41


updated 26Feb15



42


updated 26Feb15



43


updated 26Feb15


Gate Layout Algorithm

!  1. Find all Euler paths that cover the graph !  2. Find common n- and p- Euler paths !  3. If no common n- and p- Euler paths are found in

step 2, partition the gate n- and p- graphs into the minimum number of sub-graphs that will result in separate common n- and p- Euler paths

44


updated 26Feb15


Energy and Power Basics

Review


Total Power

!  Ptot ≈ Pstatic + Pdyn + Psc


Static

Leakage Power


Operating Modes

!  Steady-State: Vin=Vdd

"  PMOS: subthreshold "  NMOS: resistive

48

€

IDSp = −IS#WL

$

% &

'

( ) e

−VGS −VTnkT / q

$

% &

'

( )

1− eVDSkT / q$

% &

'

( )

$

% & &

'

( ) ) 1− λVDS( )

IDSn = µnCOXWL

!

"#

$

%& VGS −VT( )VDS −

VDS2

2(

)*

+

,-


Static Power – Ratioed Logic

!  Istatic ?

!  Input low-Output high? "  Ileak


Static Power – Ratioed Logic

!  Istatic ?

!  Input low-Output high? "  Ileak

!  Input high-Output low? "  Ipmos_on

"  ~Vdd/Rp,on


Total Static Power

!  Pstatit ≈ p(Vout=low)V2/Rp,on

+p(Vout=high)VI’s(W/L)e-Vt/(nkT/q)

p(Vout=low) – probability the output is low p(Vout=high) – probability the output is high p(Vout=high)=1-p(Vout=low)


Switching

Dynamic Power


Switching Currents

!  Iswitch(t) = Isc(t) + Idyn(t)

53

Isc

Idyn


Isw

Switching Energy

54

!  Do we know what this is?

!  What is Q? Idyn

Q = Idyn (t)dt∫

E = P(t)dt∫= I(t)Vdd dt∫=Vdd I(t)dt∫

€

Q = CV = I(t)dt∫

€

E = CVdd2

Capacitor charging energy


Switching Power

!  Every time output switches 0#1 pay: "  E = CV2

!  Pdyn = (# 0#1 trans) × CV2 / time

!  # 0#1 trans = ½ # of transitions

!  Pdyn = (# trans) × ½CV2 / time


Switching

56

Short Circuit Power


Short Circuit Power

!  Between VTN and Vdd - VTP

"  Both N and P devices conducting


Short Circuit Power

!  Between VTN and Vdd - VTP

"  Both N and P devices conducting

!  Roughly:

58

Isc

Vin

time

Vout

Isdp

time

time

time

Vthn

Vdd

Vdd

Vdd-Vthp

Isc

tsc tsc Penn ESE 570 Spring 2019 – Khanna

Vin

time

Vout

Isdp

time

time

time

Vthn

Vdd

Vdd

Vdd-Vthp

Isc

tsc tsc

Peak Current

!  Ipeak around Vdd/2 "  If |VTN|=|VTP| and sized equal rise/fall

59

€

IDS ≈νsatCOXW VGS −VT −VDSAT

2%

& '

(

) *

€

I(t)dt∫ ≈ Ipeak × tsc ×12%

& ' (

) *

€

E =Vdd × Ipeak × tsc ×12#

$ % &

' (


Short Circuit Energy

!  Make it look like a capacitance, CSC

"  Q=I×t "  Q=CV

60

E =Vdd × I peak × tsc ×12"

#$%

&'

"

#$

%

&'

E =Vdd ×QSC

E =Vdd × (CSCVdd ) =CSCV2dd



!  Every time switch "  Also dissipate short-circuit energy: E = CV2

"  Different C = Csc

"  Ccs “fake” capacitance (for accounting)



!  When transistors switch, both nMOS and pMOS networks may be nano-tarily ON at once

!  Leads to a blip of “short circuit” current !  < 10% of dynamic power if rise/fall times are

comparable for input and output !  We will generally ignore this component in hand

analysis, but simulated measured results include it


Switching Waveforms


Switching Power

!  Every time output switches 0#1 pay: "  E = CV2

!  Pdyn = (# 0#1 trans) × CV2 / time

!  # 0#1 trans = ½ # of transitions

!  Pdyn = (# trans) × ½CV2 / time


Charging Power

!  Pdyn = (# trans) × ½CV2 / time !  Often like to think about switching frequency !  Useful to consider per clock cycle

"  Frequency f = 1/clock-period

!  Pdyn = (#trans/clock) ½CV2 f


Charging Power

!  Pdyn = (# 0#1 trans) × CV2 / time !  Often like to think about switching frequency !  Useful to consider per clock cycle

"  Frequency f = 1/clock-period

!  Pdyn = (# 0#1 trans/clock) CV2 f


Switching Power

!  Pdyn = (#0#1 trans/clock) CV2 f !  Let a = activity factor

a = average #tran0#1/clock

!  Pdyn = aCV2 f


Activity Factor

!  Let a = activity factor "  a = average #tran0#1/clock


a = p(outi = 0)p(outi+1 =1)

a =N02NN12N

=N0(2

N − N0 )22N

Activity Factor

!  Let a = activity factor "  a = average #tran0#1/clock



a = N0

2NN12N

=N0 (2

N − N0 )22N

Reduce Dynamic Power?

!  Pdyn = aCV2 f

!  How do we reduce dynamic power?


Reduce Activity Factor


A B

C D

O1

O2

F

A B

C

D

O1

O2

F

Tree Chain


a = N0

2NN12N

=N0 (2

N − N0 )22N



A B

C D

O1

O2

F

A B

C

D

O1

O2

F

Tree Chain


a = N0

2NN12N

=N0 (2

N − N0 )22N

3/16

3/16



A B

C D

O1

O2

F

A B

C

D

O1

O2

F

Tree Chain


a = N0

2NN12N

=N0 (2

N − N0 )22N

3/16

3/16

15/256



A B

C D

O1

O2

F

A B

C

D

O1

O2

F

Tree Chain

3/16

7/64

15/256


a = N0

2NN12N

=N0 (2

N − N0 )22N



A B

C D

O1

O2

F

A B

C

D

O1

O2

F

Tree Chain

3/16

7/64

15/256


a = N0

2NN12N

=N0 (2

N − N0 )22N

3/16

3/16

15/256

Total Power

!  Ptot = Pstatic + Psc + Pdyn

!  Psw = Pdyn + Psc ≈ a(CloadV2f)

!  Ptot ≈ a(CloadV2f) + VI’s(W/L)e-Vt/(nkT/q)

!  Let a = activity factor a = average #tran0#1/clock


Idea

!  CMOS "  Design for worst case input switching case and delay

!  There are other logic disciplines "  Ratioed logic "  Can use pass transistors for logic

"  Transmission gates "  Will see in use in dynamic logic


Midterm Exam

!  Midterm – 3/21 "  During class; starts at exactly 1:30pm, ends at exactly 2:50pm (80

minutes) "  Location: College Hall 200 "  Old exams posted on old course websites "  Covers Lec 1- 14 + in-class worksheet "  Closed book, no notes or cheat sheets "  Calculators allowed and recommended, no smart phones


Midterm Topics List

!  Identify CMOS/non-CMOS

!  Any logic function $# CMOS gate

!  Noise Margins !  Circuit first order

switching rise/fall times "  Output equivalent

resistance "  Load capacitance

!  Transistor "  Regions of operation "  Parasitic Capacitance

Model

!  Layout and stick diagrams

!  Sizing !  1st order delay

"  Worst case "  Elmore delay

!  Ratioed logic !  Pass logic 80 Penn ESE 570 Spring 2019 – Khanna

ese 570: digital integrated circuits and vlsi …ese570/spring2019/handouts/...gate layout algorithm...

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