ESE570 Spring 2017

University of PennsylvaniaDepartment of Electrical and System Engineering

Digital Integrated Cicruits AND VLSI Fundamentals

ESE570, Spring 2017 Final Wednesday, May 3

• 4 Problems with point weightings shown. All 4 problems must be completed.

• Calculators allowed.

• Closed book = No text or notes allowed.

• Clearly label all final answers.

Name:

Grade:

Q1

Q2

Q3

Q4

Total

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ESE570 Spring 2017

University of PennsylvaniaDepartment of Electrical and System Engineering

Digital Integrated Cicruits AND VLSI Fundamentals

ESE570, Spring 2017 Formulas and Data Friday, May 6th

Physical Constants:ni = intrinsic concentration (undoped) silicon = 1.45× 1010 cm−3 @ 300◦Kk = Boltzman’s constant = 1.38× 10−23J/◦Kq = electronic charge = 1.60× 10−19C1 angstrom = 10−8cmεSi = permittivity of Si = 1.06× 10−12F/cmεSiO2 = εox = permittivity of SiO2 = 0.34× 10−12F/cm

MOS Transistor IV Characteristics:nMOS:

VGS VDS Mode IDS

≤ VTh Subthreshold IS(WL

)e

VGS−VThnkT/q

(1− e

VDS−kT/q

)(1 + λVDS)

> VTh < VGS − VTh Resistive kn2

(2(VGS − VTh)VDS − V 2DS)(1 + λVDS)

≥ VGS − VTh Saturation kn2

(VGS − VTh)2(1 + λVDS)

kn = µnCoxWn

Ln

pMOS:

VGS VDS Mode IDS

≥ VTh Subthreshold IS(WL

)e

VGS−VThnkT/q

(1− e

VDS−kT/q

)(1 + λVDS)

< VTh > VGS − VTh Resistive kn2

(2(VGS − VTh)VDS − V 2DS)(1 + λVDS)

≤ VGS − VTh Saturation kn2

(VGS − VTh)2(1 + λVDS)

kp = µpCoxWp

Lp

Threshold Voltage:

VTh = VT0 + γ(√| − 2φF + VSB| −

√| − 2φF |

)(p-sub) φF = kT

qln ni

NAand (n-sub) φF = kT

qlnND

ni

γ =√

2εSiqNA

Cox

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ESE570 Spring 2017

CMOS Capacitors:Cox = εox

toxCO = CGSO = CGDO = CoxWLD

MOS Gate Capacitance:

MOS Diffusion Capacitance:Cdiff = Cdb = ADCj0 + PDCj0swAD = Area of diffusion regionPD = Perimeter of diffusion region

Static/Dynamic Characteristics of Gates:

V50% = 12(VOL + VOH)

τPHL = time for output voltage to fall from VOH to V50%

τPLH = time for output voltage to rise from VOL to V50%

τP = τPHL+τPLH

2

Average Current Delay Model:τPHL = Cload∆VHL

Iavg,HL= Cload(VOH−V50%)

Iavg,HL

τPLH = Cload∆VLH

Iavg,LH= Cload(V50%−VOL)

Iavg,LH

First-order RC Delay Model:τPHL = 0.69 · Cload ·RPD

τPLH = 0.69 · Cload ·RPU

Power Equations:Ptot = Pdyn + PSC + PstatPdyn = dynamic power = a

(12

)CloadV

2f

PSC = short circuit power = aCSCV2f

Pstat = static power = V Istatwhere a=acitivity factor, f=switching frequency

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ESE570 Spring 2017

For this first question:

• µn=400 cm2/(V · s), µp=200 cm2/(V · s),

• |VTp | = |VTn|

• Run=resistance of Wn = 1 NMOS transistor

• Cg = gate capacitance of Wn = 1 transistor

• Cdiff=CSB=CSD=0.5 Cg

We will use the following circuit implementations (for which you will determine transistorsizing).

Inverter

Nand2

Tristate

Tristate Mux2

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ESE570 Spring 2017

1. (30 points) You will size each of the following circuits for minimum delay from the datainputs (assume the select inputs are not switching—they are set once before the circuitoperates and does not change during operation). Identify the delay of the optimizedcircuit. You should size each labeled instance of a gate independently. Assume:

• input drivers with strength Run that do not fan out to anything else.

• output load of 48Cg

There are many parameters, so a brute-force search of possible widths will likely be tootime consuming. You will need to apply insights to solve this problem efficiently. Beginfirst by identifying the critical path and writing the delay expression. Then simplifyand make assumptions to minimize the delay. Hint: Think derivatives to minimize...

(a) Tristate Mux4

Gate Trans. Size

I0 WP0

WN0

N0 WP1

WP2

WN1

WN2

I1 WP0

WN0

T0 WP3

WP4

WN3

WN4

Delay

Symbolic Delay Expression:

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ESE570 Spring 2017

(b) Tristate Mux2 tree

Gate Trans. Size

M0.I0 WP0

WN0

M0.T0 WP3

WP4

WN3

WN4

M1.I0 WP0

WN0

M1.T0 WP3

WP4

WN3

WN4

Delay

Symbolic Delay Expression:

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ESE570 Spring 2017

For the rest of the exam the following technology parameters should be used:

Parameter NMOS PMOSVT0 0.8V -0.8VµCox 300µA/V2 100µA/V2

γ, λ 0 V 1/2 0 V 1/2

Wmin 1µm 1µmLmin 1µm 1µmVDD 5V 5V

2. (25 points) The following level sensitive latch circuit with transistor sizes is designedas shown below

(a) Is this circuit a static or dynamic sequential circuit? Justify your answer.

(b) Is this a positive or negative latch? I.e. For which clock phase is the output equalto the input? Justify your answer.

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ESE570 Spring 2017

(c) The delay through the latch is determined by the rise and fall times at internalnode X. Suppose Cx = 25fF . Assume Cx >> Cg and Cx >> Cdiff . Using theswitch RC model for the transistors, calculate the rise and fall times of node Xassuming simultaneous ideal steps on D and CLK or CLK and that the initialresistance remains unchanged throughout the transition.

(d) Briefly describe a set of conditions on CLK and CLK which could cause the latchto operate incorrectly.

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ESE570 Spring 2017

3. (25 points) For this problem, assume all transistor widths and lengths are 1µm, unlessotherwise specified. Below is shown an eight transistor memory cell. The inverters areCMOS inverters.

(a) What type of memory cell is shown above (I.e SRAM, DRAM, ROM, etc.)?Justify your answer

(b) Label the figure (fill in the boxes) to clearly indicate the storage (data) node Q,the write word line WWL, the read word line RWL, the write bit line WBL, andthe read bit line RBL. Also label the complements of any signals if necessary.

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ESE570 Spring 2017

(c) Assume Node 1 is a storage node and NMOS M1 connects to a bidirectionalbit line. If Node 1 stores a logic 0 and the bit line is held at VDD , write anequation which can be solved for the voltage V1 at Node 1. State any reasonableassumptions you make. Simplify the equation but you do not need to solve forV1.

(d) Under the same assumptions as in part (c), if Node 1 stores a logic 1 and the bitline is held at 0V , write an equation which can be solved for the voltage V1 atNode 1. State any reasonable assumptions you make. Simplify the equation butyou do not need to solve for VI.

(e) What is the principal advantage of the 8T memory cell over a conventional 6TSRAM cell?

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ESE570 Spring 2017

4. (20 pts) Short Answer Questions: Answer the questions briefly. Include diagrams andequations as needed. Be clear in your explanation and handwriting.

A Draw the IV relationships between drain current and the drain-to-source voltageand gate-to-source voltage (Id vs. VGS and Id vs. VDS) Label all relevant features.

B What is short circuit power and how can you estimate it?

C What is a standard cell?

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ESE570 Spring 2017

D What is crosstalk and how can it affect the performance of your design?

E What affect does glitching have on energy consumption of a design? Be specifichow/why it affects the energy.

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