“esd phenomena” esd mitigation techniques events/ieee_esd_april_2_2008.pdf · “esd...
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April 2, 2008 Cyrous Rostamzadeh 1
“ESD Phenomena”ESD Mitigation Techniques
Cyrous Rostamzadeh
April 2, 2008 Cyrous Rostamzadeh 2
Opening Question:
“It has Failed, Why?”
April 2, 2008 Cyrous Rostamzadeh 3
Engineers get involved into System Level ESD through questions like……How to Fix an ESD problem on a DUT?
April 2, 2008 Cyrous Rostamzadeh 4
Which Design Choices will preventESD problems? Or...
How do I optimize an IC design for the
Best System level ESD Performance?
April 2, 2008 Cyrous Rostamzadeh 5
Is there a Correlation between
System level and IC level ESD?
To help to answer such questionsWe need to understand the fundamentals of ESD.
April 2, 2008 Cyrous Rostamzadeh 6
Immediate Concern:Semiconductor Devices Fail when Exposed to ESD.
Why should We care about ESD?
April 2, 2008 Cyrous Rostamzadeh 7
It is one of the most importantReliability problems in the“Integrated Circuit” Industry.
~ 50% of all “Field Failures”are due to ESD. It cannot be ignored.
April 2, 2008 Cyrous Rostamzadeh 8
Requires “Knowledge”, and “Right Tools” to
Resolve ESD Problems.
SolutionSolution
April 2, 2008 Cyrous Rostamzadeh 9
There is a purpose for every tool….Can I use soldering iron in place of screw driver? May be someone does! We should not!
ToolsTools……
April 2, 2008 Cyrous Rostamzadeh 10
Knowledge is the key tool.Instrumentation is necessary.Critical Measurement is essential.
Knowledge, ToolsKnowledge, Tools,,……
April 2, 2008 Cyrous Rostamzadeh 11
Microelectronic industry has led to an interest in ESD.Last 35 years, with the growth of Semiconductor industry, ESD has become a discipline of significant interest.
April 2, 2008 Cyrous Rostamzadeh 12
In 1970’s as a result of concerns in the Cold War, EMP (Electromagnetic Pulses)
Excellent Physical Models were produced to understand the ESD Robustness of Electrical Components.
April 2, 2008 Cyrous Rostamzadeh 13
In the 1980’s with the growth of Semiconductor Fabrication andthe Semiconductor Industry, ESD remained an issue as:Human handling, tooling, shipping and garments, influenced the reliability of Semiconductor Components.
April 2, 2008 Cyrous Rostamzadeh 14
In 1990’s, tremendous growth in ESD understanding, as new fields and new issues continued to emerge...Transition from µ-Electronics to Nanostructures, Semiconductors, Magnetic Recording Devices, µ-Machines, MEM’s… Huge concern with ESD
April 2, 2008 Cyrous Rostamzadeh 15
2000 - 2008, huge growth in ESD understanding, as new fields and new issues continue to emerge...Further transition in Nanostructures, High K Dielectric µ−processors, High Density FPGA, DSP…Mobile Phones, Portable Electronics….
April 2, 2008 Cyrous Rostamzadeh 16
ESD means different things to different people
April 2, 2008 Cyrous Rostamzadeh 17
For System User it means presence
or absence of Spark
ESD means different things to different people
April 2, 2008 Cyrous Rostamzadeh 18
For Manufacture Engineer, it means wrist strap, ground mat, air ionizer, ESD shoe, ESD Garment, ANSI/ESD S20.20
ESD means different things to different people
April 2, 2008 Cyrous Rostamzadeh 19
For Semiconductor Engineer, it means Conductive Packaging
ESD means different things to different people
April 2, 2008 Cyrous Rostamzadeh 20
For Test Engineer, it means ESD GunsESD means different things to different people
April 2, 2008 Cyrous Rostamzadeh 21
ESD means different things to different people
For you Design Engineers, it means:
Bulletproof Design, or ESD ROBUST DesignESD ROBUST Design.
April 2, 2008 Cyrous Rostamzadeh 22
For ESD testing, as for reliability
testing, the purpose of the test is
to verify that the item tested will
operate acceptably in actual use.
April 2, 2008 Cyrous Rostamzadeh 23
In order to achieve this purpose
the test must achieve both
Realism and Repeatability.
April 2, 2008 Cyrous Rostamzadeh 24
If not repeatable, then it cannot
be trusted to detect problems,
or judge the success of solutions.
April 2, 2008 Cyrous Rostamzadeh 25
If the test is not representative
of the reality, then it will not be
successful as a predictor of the
Reliability of the device in the
Real world.
April 2, 2008 Cyrous Rostamzadeh 26
To be considered realistic, an ESD TESTESD TEST
must Recreate the key components of an
actual ESD Threat.
IC’s fail due to Excessive Voltage or EnergyEnergy
April 2, 2008 Cyrous Rostamzadeh 27
Excessive VoltageExcessive Voltage can cause
Dielectric BreakdownDielectric Breakdown in IC’s
such as Oxide Barriers.
April 2, 2008 Cyrous Rostamzadeh 28
Excessive Energy can cause Thermal Failure
by “Melting Silicon” or “Metallization” of IC.
Melting Temperature of Silicon ~ 1,420Melting Temperature of Silicon ~ 1,42000CC
Melting Temperature of Metallization ~ 600Melting Temperature of Metallization ~ 60000CC
April 2, 2008 Cyrous Rostamzadeh 29
One might expect metal would always be damaged first.
Thermal Conductivity of Metal is >> Thermal Conductivity of Silicon.
Short, Intense Pulse may deposit Energy in
Silicon more quickly than Silicon can
spread and dissipate the resulting Heat.
April 2, 2008 Cyrous Rostamzadeh 30
Metallization
April 2, 2008 Cyrous Rostamzadeh 31
Metallization
April 2, 2008 Cyrous Rostamzadeh 32
Metallization
April 2, 2008 Cyrous Rostamzadeh 33
Pre-ESD Capacitor Characteristics
April 2, 2008 Cyrous Rostamzadeh 34
Post-ESD Capacitor Damage
DC – 20 kHz
April 2, 2008 Cyrous Rostamzadeh 35
Post-ESD Capacitor Damage
DC – 20 kHz
April 2, 2008 Cyrous Rostamzadeh 36
IC Level ESD Standards DO NOT Test for Soft-Errors (Bit Errors, Upsets, Resets, etc..). They only test if the ICs are Damaged by ESD
April 2, 2008 Cyrous Rostamzadeh 37
System Level ESD Test Standards applied to operating systems while observing the functionality of the system in addition to observing for any damages.
April 2, 2008 Cyrous Rostamzadeh 38
System Level Human ESD Model is based on a Discharge of a Human via a piece of Metal.
IC Level ESD Model is based on a Discharge from the Skin to Grounded IC
April 2, 2008 Cyrous Rostamzadeh 39
ESD is Not only a Broadband Event, but an ESD test is a Combination of Different Physical Stresses to a System.
April 2, 2008 Cyrous Rostamzadeh 40
Electrostatic Problems:
Manufacturing.Field Operation.
April 2, 2008 Cyrous Rostamzadeh 41
ESD Solutions:
Manufacturing ESD Control Program
Field Failures ESD Robust Design
April 2, 2008 Cyrous Rostamzadeh 42
Important Distinction“ESD Control Program” during
Manufacturing Does NOT
imply “ESD Robust Product” !
April 2, 2008 Cyrous Rostamzadeh 43
Hard FailuresJunction burnoutIC metal burnoutDielectric breakdownTransient Interference
Soft FailuresLogic ErrorsSystem ResetLost DataLost program Flow
April 2, 2008 Cyrous Rostamzadeh 44
Direct Connection
Secondary Arcing
Electric Field
Magnetic Field
April 2, 2008 Cyrous Rostamzadeh 45
April 2, 2008 Cyrous Rostamzadeh 46
April 2, 2008 Cyrous Rostamzadeh 47
ESD voltages as high as 30 kV has been observed in automotive environment.ESD is rich in high-frequency (> 3 GHz) !ESD event can create currents in excess of 30 Amps!ESD currents can destroy IC’s, PCB traces and other
components.ESD can create time-varying Magnetic Field: 25 A/m.ESD can create time-varying Electric Field as high as: 10 kV/m.ESD can create Susceptibility Problems.
April 2, 2008 Cyrous Rostamzadeh 48
April 2, 2008 Cyrous Rostamzadeh 49
ESD phenomena involves Electrical & Thermal Electrical & Thermal
TransportsTransports on the Scale of nanometers (nm), Circuits
and Electronics on the Scale of micrometers (µm),
Semiconductor Chip designs range from picoseconds
(ps) to microseconds (µs), Electrical Currents of interest
range from mA to 10’s of Amperes.Voltages range from
Volts to kiloVolts (kV). Temperatures vary from room
temperature to melting temperatures of 1000’s 0K…….
April 2, 2008 Cyrous Rostamzadeh 50
Must Quantify the Scale in Space & TimeSpace & TimeESD phenomena involves:
Microscopic to Macroscopic Scales.
ESD is a Thermo-Electric Transport of Material Physics
April 2, 2008 Cyrous Rostamzadeh 51
April 2, 2008 Cyrous Rostamzadeh 52
Electrostatic Equilibrium, Post-ESD
Φ−∇=|| Er
Electrostatic Field, Pre-ESD
0E ,0 ==Φr
ESD Physics
April 2, 2008 Cyrous Rostamzadeh 53
Tribos - Greek for "rubbing"
The triboelectric effect is a type of contact
electrification in which certain materials become
electrically charged after they come into contact
with another different material and are then
separated.
ESD Physics
April 2, 2008 Cyrous Rostamzadeh 54
Positive (+)1) Air
2) Human Skin
3) Asbestos
4) Glass
5) Mica
6) Human Hair
7) Nylon
8) Wool
9) Fur
10) Lead
11) Silk
12) Aluminum
13) Paper
14) Cotton
15) Wood
16) Steel
17) Sealing Wax
18) Hard Robber
19) Mylar
20) Epoxy Glass
21) Nickel, Copper
22) Brass, Silver
21) Gold, Platinum
22) Polystyrene foam
23) Acrylic
24) Polyester
25) Celluloid
26) Orlon
27) Polyethylene foam
28) Polyethylene
29) PVC (Vinyl)
30) Silicon
31) Teflon Negative (-)
Triboelectric Series
April 2, 2008 Cyrous Rostamzadeh 55
1.5 kV18 kVSitting on chair padded with Polyurethane foam
1.2 kV20 kVPicking up common Polyethylene bag
600 Volts7 kVOpening a Vinyl envelope
100 Volts6 kVWorker moving at bench
250 Volts12 kVWalking on Vinyl Floor
1.5 kV35 kVWalking across carpet
65% to 90% Relative Humidity
10% to 20 % Relative Humidity
Means of Static Generation
Typical Electrostatic VoltagesTypical Electrostatic Voltages
April 2, 2008 Cyrous Rostamzadeh 56
Capacitance – ESD
Charge Storage Element
April 2, 2008 Cyrous Rostamzadeh 57
⎟⎟⎠
⎞⎜⎜⎝
⎛−
=
21
114
rr
C πε
r1
r2
( ) pF 50C sphere,diameter
meter 1 toarea surfacea has humana pF, 111/1085.8 space, freefor and ,r
BodyHuman
122
≈⇒≈×=
×=∞⇒ −
rCmFif ε
Charge Storage CapacitanceCharge Storage Capacitance
April 2, 2008 Cyrous Rostamzadeh 58
1 pFAn object a size of marble
700 µFEarth’s Capacitance
50 pFHuman Body Capacitance
In addition, we must consider In addition, we must consider Parallel Plate Parallel Plate CapacitanceCapacitance due to the proximity of an object due to the proximity of an object to the surroundingto the surrounding
FreeFree--Space CapacitanceSpace Capacitance
April 2, 2008 Cyrous Rostamzadeh 59
100 pF
50 pF to infinity
50 - 100 pF
500 Ω to 10 kΩ
Self-Capacitance
Human Body Model (HBM)Human Body Model (HBM)
April 2, 2008 Cyrous Rostamzadeh 60
Human Body Model (HBM)Human Body Model (HBM)
Therefore, the Capacitance of a Human Body is Therefore, the Capacitance of a Human Body is the Combination of Freethe Combination of Free--Space Capacitance Space Capacitance ++ParallelParallel--Plate Capacitance and can vary from Plate Capacitance and can vary from
50 50 pFpF to 250 to 250 pFpF
April 2, 2008 Cyrous Rostamzadeh 61
kVtoVkR
pFC
HB
HB
HB
25 0 10 500
25050
=Ω−Ω=
−=
VHB
Human Body Model (HBM)Human Body Model (HBM)
April 2, 2008 Cyrous Rostamzadeh 62
mJ 30 Energy
)000,25(1010021
21 2122
≈
×××== −CVEnergy
For a Human Body of 100 pF Capacitance, Charged Up
to 25 kVolt, Energy Released Per Discharge…….
Human Body Model (HBM)Human Body Model (HBM)
April 2, 2008 Cyrous Rostamzadeh 63
The Discharge of a Human (via a small, hand-held metal piece) is basis for the current waveform most often used IEC 61000-4-2 standard.
Human Body Model (HBM)Human Body Model (HBM)
April 2, 2008 Cyrous Rostamzadeh 64
GM3097 (July 2006)
Ford ES-XW6T-1A276-AC
Chrysler DC 11224ISO 10605 (2001) & IEC 61000ISO 10605 (2001) & IEC 61000--44--22 Standards with some Modifications.
Ambient Temperature: 23 +/- 3oC Relative Humidity 20 to 40% Prefer 20oC and 30% RH.Contact Rise Time: tr < 1 nsAir Discharge Rise Time: tr < 20 ns. Discharge Networks: 150 pF/2 kΩ and 330 pF/2 kΩ
OEM ESD Test ParametersOEM ESD Test Parameters
April 2, 2008 Cyrous Rostamzadeh 65
1.1.Electrostatic,Electrostatic, describing the ChargingCharging and Charge Charge DistributionDistribution prior to Breakdown.
Events during an ESD Discharge
April 2, 2008 Cyrous Rostamzadeh 66
From Static to GHz PropagationFrom Static to GHz PropagationHuman ESD: The beginning scenario is a Human holding a small piece of metal (e.g., a key, ring, screwdriver). He has been charged and is approaching a grounded part of a system.
Events during an ESD Discharge
April 2, 2008 Cyrous Rostamzadeh 67
2. Physics of Sparking,Physics of Sparking,describing the development of the Conductivity in the Arc.
Events during an ESD Discharge
April 2, 2008 Cyrous Rostamzadeh 68
3.3. Fast Transient Fast Transient ElectromagneticsElectromagnetics,during the first phase of the Discharge EM WavesDischarge EM Waves travel on DUT. Local differences and Temporal Changes are
Strong. Consequently, the Structure is Electrically Large; Antenna
Theory, Shielding and Coupling are the appropriate methods for
describing ESD in this phase. Picture this as if a 3 GHz pulses
impinges on the DUT.
Events during an ESD Discharge
April 2, 2008 Cyrous Rostamzadeh 69
4.4. Slower Currents and Charge Slower Currents and Charge Redistribution, Redistribution, after the first phase
Current and Voltage derivatives have been
reduced by Radiation and Reflection to levels
that the dominating frequencies are slow
enough, such that the structure can be treated as
Electrically Small, A description by equivalent
circuit is suitable in this phase of the discharge.
Events during an ESD Discharge
April 2, 2008 Cyrous Rostamzadeh 70
Fast Transient Electromagnetic Fast Transient Electromagnetic Phase is the most challenging, but it Phase is the most challenging, but it is the Rootis the Root--Cause for Most of the Cause for Most of the SoftSoft--Errors Observed. One should Errors Observed. One should Concentrate on Currents and Concentrate on Currents and Voltages present during this phase Voltages present during this phase of the Discharge.of the Discharge.
Fast Transient Phase of ESD Discharge
April 2, 2008 Cyrous Rostamzadeh 71
1-15 kV, 0.7 – 1 ns time3.75 A/kV Peak Current
Soft-Error (upset, Reset) and Hard Error (Damage)
IEC 61000-4-2Human Discharging through a small piece of metal
Main ParametersFailure IndicationStandard/ModelReference Event
April 2, 2008 Cyrous Rostamzadeh 72
System level upset, and damageOnly damage to the IC
Most test up to 8000 VoltsVoltage usually < 4000 Volts
trise < 850 pstrise < 5 ns
Rseries = 330 ΩRseries = 1500 Ω
C = 150 pFC = 150 pF
System Level HBMIC Level HBM (Human Body Model)
IC Level – System Level ESD
April 2, 2008 Cyrous Rostamzadeh 73
ESD Process is associated with Strong Electromagnetic Fields
Example: for 5 kV discharge:
•18 Amp Peak Current,
•Rise Time of 850 ps,
•|E| = 10 kV/m (10 cm distance)
•|H| = 25 A/m (10 cm distance)
5 kV ESD Discharge
April 2, 2008 Cyrous Rostamzadeh 74
1.Human Body Model (HBM)
2.Charged Device Model (CDM)
3.Machine Model (MM)
4.Transmission Line Pulse Model (TLP)
ESD Modeling
April 2, 2008 Cyrous Rostamzadeh 75
Prior to Discharge………
an Electrostatic Field exists.
There is NO Current flowing (or only very little Current).
Therefore, NO relevant Magnetic Field is present.
Events during an ESD Discharge
April 2, 2008 Cyrous Rostamzadeh 76
Once the Distance is sufficiently small………a Dielectric Breakdown will occur…………….The Electric Field Starts Collapsing……..It collapses down to about 25 - 40 V within 50 ps-5 ns...The collapse time depends on Arc Parameters, Voltage,……
Events during an ESD Discharge
April 2, 2008 Cyrous Rostamzadeh 77
Events during an ESD Discharge
A Current starts flowing on the metal part and the DUT. The foremost current front expands with the velocity of light. Within the 800 ps it has reached the arm of the person. Current will expand further on the DUT and the arm. It will experience Reflections and Losses due to Radiation and Resistance …complex pattern of Current Density of the DUT and the person. During this phase the person and the DUT act an antenna. This phase is about 10 ns long. The Highest frequency components of the current will be attenuated mainly due to Radiation leading to a smoother current (less high frequency)
April 2, 2008 Cyrous Rostamzadeh 78
As the higher frequency components do not dominate anymore a description as equivalent circuit is possible for a time frame from about 10 ns until the body reaches a new electrostatic equilibrium. The remaining charge may not zero, as the arc might extinguish before this has been reached. If the hand is approaching the DUT further, a second discharge will occur at a lower voltage. This can lead to a sequence of ESDs, each one at a lower voltage, but each one having a faster rise time.
Events during an ESD Discharge
April 2, 2008 Cyrous Rostamzadeh 79
ESD Mathematical Analysis
April 2, 2008 Cyrous Rostamzadeh 80
⎟⎟⎠
⎞⎜⎜⎝
⎛ −•
⎟⎟⎠
⎞⎜⎜⎝
⎛+
⎟⎟⎠
⎞⎜⎜⎝
⎛
•+⎟⎟⎠
⎞⎜⎜⎝
⎛ −•
⎟⎟⎠
⎞⎜⎜⎝
⎛+
⎟⎟⎠
⎞⎜⎜⎝
⎛
•=4
3
3
2
2
2
1
1
1
1 exp
1
exp
1
)(τ
τ
ττ
τ
τ t
t
t
kit
t
t
kiti n
n
n
n
, exp/1
1
2
2
11 ⎟
⎟
⎠
⎞
⎜⎜
⎝
⎛⎟⎟⎠
⎞⎜⎜⎝
⎛−=
nnkττ
ττ
⎟⎟
⎠
⎞
⎜⎜
⎝
⎛⎟⎟⎠
⎞⎜⎜⎝
⎛−=
nnk
/1
3
4
4
32 exp
ττ
ττ
τ4 = 58 nsτ2 = 1.7 nsI2 = 10.1 Amp
n = 3τ3 = 6 nsτ1 = 1.3 nsI1 = 21.9 Amp
April 2, 2008 Cyrous Rostamzadeh 81
April 2, 2008 Cyrous Rostamzadeh 82
April 2, 2008 Cyrous Rostamzadeh 83
HBM ESD Time ConstantHBM ESD Time Constant
nspFCR
HB
HBHBHB
150 100 1500 =×Ω==
ττ
Similar to Thermal Diffusion Time of many
materials used in semiconductor industry
April 2, 2008 Cyrous Rostamzadeh 84
ESD is a Non-Linear Electro-Thermal Physical Event.
Very Difficult to Model Accurately.
Simple Linear Model is insightful.
April 2, 2008 Cyrous Rostamzadeh 85
MM ESD Time ConstantMM ESD Time Constant
nspFtoCR
MM
MMMMMM
2 200 )25 10( =×Ω==
ττ
Typically 100 times faster than HB time constant, and
it is oscillatory. Protection needed is 5 to 10 times lower
than required for HB protection.
April 2, 2008 Cyrous Rostamzadeh 86
VGen = 8 kV
ESD Generator Model
April 2, 2008 Cyrous Rostamzadeh 87
Time (ns)
Cur
rent
(A)
VGen = 8 kV
ESD Generator Model
April 2, 2008 Cyrous Rostamzadeh 88
VHBM = 25 kVESD HBM Model
April 2, 2008 Cyrous Rostamzadeh 89
Time (ns)
Cur
rent
(A)
VHBM = 25 kV
ESD HBM Model
April 2, 2008 Cyrous Rostamzadeh 90
“PCB Via”“ESD Protection Interconnect Dilemma”
April 2, 2008 Cyrous Rostamzadeh 91
S = Via Separation, in.
R = Via Radius, in.
H = Via Length, in.
L = Inductance, nH.
Inductance between 2 Connector Pins or Vias
⎟⎠⎞
⎜⎝⎛××=
RSHL elog16.10
ESD Protection Interconnect Dilemma
April 2, 2008 Cyrous Rostamzadeh 92
⎟⎠⎞
⎜⎝⎛××=
RSHL elog16.10
ESD Protection Interconnect Dilemma
April 2, 2008 Cyrous Rostamzadeh 93
⎥⎦
⎤⎢⎣
⎡+⎟
⎠⎞
⎜⎝⎛= 14ln08.5via d
hhL
h
d
Typical Value
Lvia = 1 nH
ESD Protection Interconnect Dilemma
April 2, 2008 Cyrous Rostamzadeh 94
Ω==
====
⎥⎦
⎤⎢⎣
⎡+⎟
⎠⎞
⎜⎝⎛=
8.3X
nH 1.2 Lns 1tmil 16 dmil 63
14ln08.5
L
r
via
rtL
hdhhL
π
h
d
ESD Protection Interconnect Dilemma
April 2, 2008 Cyrous Rostamzadeh 95
12
1via
41.1DDTDC r
−=
ε
Clearance Hole
Pad
Typical Value
Cvia = 0.5 pF
ESD Protection Interconnect Dilemma
April 2, 2008 Cyrous Rostamzadeh 96
Pad
Example: Via Pad Diameter = 0.8 mm
Via Hole Diameter = 0.3 mm (----> 0.25 mm)
h = 1.6 mm,or 63 mil
Clearance Hole
ESD Protection Interconnect Dilemma
April 2, 2008 Cyrous Rostamzadeh 97
D2 = Diameter of Clearance hole in GND Plane, in.
D1 = Diameter of pad surrounding via, in.
T = Thickness of printed circuit board, in
C = Capacitance in pF.
Typical Value
Cvia = 0.5 pF
12
1via
41.1DDTDC r
−=
ε
Clearance Hole
Pad
Inner Layer GND Planer
D2 = Diameter of Clearance hole in GND Plane, in.
D1 = Diameter of pad surrounding via, in.
T = Thickness of printed circuit board, in
C = Capacitance in pF.
Typical Value
Cvia = 0.5 pF
12
1via
41.1DDTDC r
−=
ε
Clearance Hole
Pad
Inner Layer GND Planer
ESD Protection Interconnect Dilemma
April 2, 2008 Cyrous Rostamzadeh 98
ESD Failure Modes
Direct Hit.Direct Hit.
PrePre--ESD Electric Field.ESD Electric Field.
Magnetic Field.Magnetic Field.
Electromagnetic Field.Electromagnetic Field.
Ground Bounce. Ground Bounce.
April 2, 2008 Cyrous Rostamzadeh 99
Avoid Avoid Direct ConnectionDirect Connection from an exposed from an exposed external point to an Integrated Circuit.external point to an Integrated Circuit.
ESD Strategies
““E ~ 30 E ~ 30 mJmJ””
April 2, 2008 Cyrous Rostamzadeh 100
ESD Strategies
In no case should there be a directIn no case should there be a direct
connection from an Integrated Circuitconnection from an Integrated Circuit
to an exposed external point. to an exposed external point.
April 2, 2008 Cyrous Rostamzadeh 101
ESD Strategies
Divert or limit the ESD Energy awayDivert or limit the ESD Energy away
from Circuit Inputs using Filters orfrom Circuit Inputs using Filters or
Transient Suppressors. Transient Suppressors.
April 2, 2008 Cyrous Rostamzadeh 102
ESD Strategies
Determine the most vulnerable internal Determine the most vulnerable internal
circuits. Most likely to be upset by circuits. Most likely to be upset by
Electromagnetic EffectsElectromagnetic Effects……Resets, Resets,
Interrupts and critical control lines. Interrupts and critical control lines.
April 2, 2008 Cyrous Rostamzadeh 103
ESD Capacitor…?100 pF, 1 nF, 10 nF, 47 nF 100 nF…?
MLCC 0805, 0603, 0402?
100 Volts, 50 Volts?
April 2, 2008 Cyrous Rostamzadeh 104
ESD Capacitor Value
April 2, 2008 Cyrous Rostamzadeh 105
ESD Capacitor Mounting Strategy
How far from Connector Pin…
PCB layer stackup…
Y-Connection…
April 2, 2008 Cyrous Rostamzadeh 106
ESD Capacitor Failure Mode
Voltage – Pressure
Current – Force
Dielectric Breakdown
April 2, 2008 Cyrous Rostamzadeh 107
IHF
April 2, 2008 Cyrous Rostamzadeh 108
SolutionSolutionESD Strategies
April 2, 2008 Cyrous Rostamzadeh 109
SolutionSolutionESD Strategies
April 2, 2008 Cyrous Rostamzadeh 110
SolutionSolutionESD Strategies
April 2, 2008 Cyrous Rostamzadeh 111
Use LOW Capacitance Protection
High Capacitance Protection --- 6X Longer Delay Time Low Capacitance Protection
SolutionSolution
ESD Strategies
April 2, 2008 Cyrous Rostamzadeh 112
IHF
SolutionSolutionESD Strategies
April 2, 2008 Cyrous Rostamzadeh 113
l > λ
ESD
““Fast Transient Fast Transient ElectromagneticsElectromagnetics””
Structure “Electrically Large”
Frequency ~ 3 GHz
Field Collapses to 25 Field Collapses to 25 -- 40 V within 40 V within ““50 50 psps –– 5 ns5 ns””
April 2, 2008 Cyrous Rostamzadeh 114
1. TVS (Transient Voltage Suppressor)2. MOV Multilayer Zinc Oxide3. Diode4. Capacitor5. Spark Gap6. Filters7. Ferrites
ESD Protection Devices
April 2, 2008 Cyrous Rostamzadeh 115
Capacitor Placement
April 2, 2008 Cyrous Rostamzadeh 116
20 nH
20 nHReturn
ESD Protection Interconnect Dilemma
April 2, 2008 Cyrous Rostamzadeh 117
0 nHReturn
20 nH20 nH
ESD Protection Interconnect Dilemma
April 2, 2008 Cyrous Rostamzadeh 118
7.94 MHz
20 nH
20 nHReturn
C = 10 nF
ESL = 200 pH
ESR = 22 mΩ
ESD Protection Interconnect Dilemma
April 2, 2008 Cyrous Rostamzadeh 119
11.27 MHz
20 nH
0 nHReturn
C = 10 nF
ESL = 200 pH
ESR = 22 mΩ
ESD Protection Interconnect Dilemma
April 2, 2008 Cyrous Rostamzadeh 120
112.98 MHz0 nH
Return
20 nH20 nH
C = 10 nF
ESL = 200 pH
ESR = 22 mΩ
ESD Protection Interconnect Dilemma
April 2, 2008 Cyrous Rostamzadeh 121
Poor Better Best
ESD Protection Interconnect Dilemma
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ESD Protection Interconnect Dilemma•All dimensions are in inches
0.0075
0603 Skinny
0603 Capacitor
0.030 square soldering pad 0.050
0.024 round via pad
0.010 dia. hole
0.030
0603 Fat
0603 Capacitor
0.030 square soldering pad 0.050
0.024 round via pad0.010 dia. hole
0603 end
0402 end Same via
and hole
0.020 squaresoldering pad
0402 side
April 2, 2008 Cyrous Rostamzadeh 129
0.210.250.320.430.260.320.400.600402 side
0.380.440.580.820.420.500.671.010402 end
0.330.380.510.670.360.460.610.850603 side
0.420.530.681.070.500.590.771.160603 end
0.891.121.472.070.951.171.522.230603 fat
1.511.662.132.681.511.772.182.870603 skinny
0.0040.0060.0100.0200.0040.0060.0100.020Via Length
Hole Diameter 0.020 inHole Diameter 0.010 in
ESD Protection Interconnect Dilemma
April 2, 2008 Cyrous Rostamzadeh 130
ESD Strategies
High Density Connector Restricts
Optimized Mounting Strategy
For ESD Capacitors.
April 2, 2008 Cyrous Rostamzadeh 131
Prevent ESD Current flow into PCB Ground Structure.This problem can be sneaky!
Do NOT assume PCB Ground has a low Impedance!tr = 1nsec (300 MHz +), ZGround is NOT LOW!
Ground BOUNCE CMOS Latch-up. In reality ESD does NOT cause
damage; it just sets things up so the power supply can destroy the part!
April 2, 2008 Cyrous Rostamzadeh 132
Due to ESD Transient Nature:Fast (edge rate ~< 1 nsec) Digital Circuits are
Highly Susceptible!Slow Analog Circuits are Immune!
NOTE: This is NOT a Direct ESD Discharge!It is due to Electromagnetic Fields and Pre-ESD Electric Field.
April 2, 2008 Cyrous Rostamzadeh 133
Minimize interconnect Inductance.
Use lowest value Capacitors to prevent degradation of High-Speed signals.
April 2, 2008 Cyrous Rostamzadeh 134
Spark Gap “Protection Mechanism”
April 2, 2008 Cyrous Rostamzadeh 135
Spark Gap
April 2, 2008 Cyrous Rostamzadeh 136
Vs/m 105-2 Constant Process
)()()(
length arc d Process; SurfacePressure Normalat Vs/m 108 Constant
)()()(
:Process" Discharge Gas" LawTopler
4-0
4-0
×≈=
⋅⋅
=
=×≈=
⋅⋅
=
∫
∫
Surfacea
dIdatUtI
Toplera
dIdatUtI
M
t
surfM
arcsurf
T
t
gasT
arcgas
ζξ
ζξ
Spark Gap Physics
April 2, 2008 Cyrous Rostamzadeh 137
PSPICE Model for Spark Gap
RHB = 330 Ω
CHB = 150 pF
< 0.1 uH Iarc (t)
Isurf (t) Igas (t)
Cgap
Spark Gap
April 2, 2008 Cyrous Rostamzadeh 138
Spark Gap
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Spark Gap
April 2, 2008 Cyrous Rostamzadeh 140
Connector Area ESD Capacitors
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Connector Area ESD Capacitors
April 2, 2008 Cyrous Rostamzadeh 142
High Frequency Design Practice ESD
ESD
April 2, 2008 Cyrous Rostamzadeh 143
ESD Exteremely Fast Transient
ESD Has Several Failure Modes
Several Design Tactics
Several Strategic Concepts
ESD Circuit Protection
ESD Grounds
ESD Shuelding
April 2, 2008 Cyrous Rostamzadeh 144
Thank you for your
Participation.