D A T A S H E E T

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Custom Integrated Circuit DesignEldo PremierFaster Full-Accuracy IC Simulation

NEW LEVEL OF IC CIRCUIT SIMULATION—ELDO PREMIEREldo® Premier is an accelerated transistor-level time-domain simulator. On average, Eldo Premier runs 2.5 times faster than Eldo Classic, and as much as 20 times faster in some cases, while delivering uncompromised SPICE accuracy. Designers benefit from speed improvements without any subtle “optimization” that might affect accuracy. Hundreds of industry test cases have been used to validate the technology and results and were compared to the golden simulation results from Eldo Classic.

Eldo Premier significantly extends the capacity of Eldo Classic to as many as 10 million devices. This increased capacity is important for post-layout circuits and enables SPICE-accurate simulation of extremely large analog IPs and mixed-signal ICs, TFT panels, and SRAMs/DRAMs.

ADVANCED SIMULATION TECHNOLOGYThe Eldo Premier simulator accelerates single-thread and multi-thread simulations. The acceleration of single-thread simulation is accomplished by new algebraic techniques for the resolution of the system of non-linear differential equations. The acceleration of multi-threaded simulations is

Key Benefits

• 2.5x on average, and up to20x, speed-up over EldoClassic accelerates designand verification cycle

• Uncompromised SPICE-quality accuracy to fit in sign-off flow

• 10 million transistors capacity allows accurate verification of largest analog IPs and mixed-signal ICs

• Optimized natively paralleland scalable code takes bestadvantage of multicoremachines

• Tight integrations to ICdesign frameworks from Mentor Graphics and Cadence Design Systems maximize productivity

Compared performance of Eldo Premier (Eldo-P) and Eldo Classic (Eldo-C), on 1 core, 4 cores, and 8 cores. All circuits are real customer test cases and cover a wide variety of applications and technologies. The horizontal scale shows directly the speed-up factor over Eldo Classic. As is evident from the figure, performance of the Eldo Premier simulator really shines with large circuits containing several hundred thousand elements.

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achieved by the natively parallel code of the new simu-lation kernel and its dedicated data structures. Eldo Premier multi-threads the entire matrix solution and device evaluation.

These two acceleration factors combine tooffer a significant speed increase over Eldo Classic. The greatest increase in speed is observed for large circuits (typi-cally 10K or more devices) that exhibit some degree of hierarchi-cal regularity.

This increase in speed is also scalable. Speed-up factors of three times or more on four cores and up to six to seven times on eight cores have been routinely observed for large circuits with many devices.

WIDE SCOPE APPLICABILITYThe Eldo Premier simulator targets applications that require CPU-intensive transient simula-tions, such as PLLs and DLLs, frequency synthesizers, delta-sigma converters, ADC/DAC audio and video converters, au-tomotive circuits, DC-DC converters, regulators, power management circuits, memory critical paths analysis and TFT panels.

The scope of applicability is the same as Eldo Classic because the algorithms do not presuppose any particu-lar structure within the simulated circuit.

BENEFITS OF HIGHER SPICE PERFORMANCEBoosting performance of standard analog simulation can help in two ways. Critically important simula-tions that require extremely long simulations times,

sometimes measured in days or weeks, can be reduced significantly, from 2.5x (average) to 20x (peak).

Multiplying performance can dramatically improve the productivity of a design team—and sometimes simply allow the verification task to be fit into the global de-sign cycle time. Alternatively, the additional raw simu-

lation power can be used to run many more process corners or operating conditions and thus verify a design or analog IP block much more thoroughly.

For example, it may become practical to verify an entire temperature range or power-supply range instead of just the nominal point of the specifications. This can dramatically improve the confidence in the design or IP before tapeout, with the goal of eliminating silicon re-spins and improving the final manufacturing yield.

Eldo Premier simulation for a PLL.

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FAMILIAR USE MODEL OF ELDO CLASSICEldo Premier use model is similar to Eldo Classic. It uses the same netlist format, device models, and librar-ies as Eldo Classic. It supports the .extract, .meas, .step, and .alter commands of Eldo Classic.

Eldo Premier supports RCC parasitic network reduction (reduction is always optional and must be explicitly activated—it never happens by default, nor silently). Eldo Premier is integrated in Questa ADMS for mixed-signal verification including VHDL/Verilog and VHDL-AMS/Verilog-AMS descriptions.

DEVICE MODELSEldo Premier supports all standard device models, just like Eldo Classic, including BSIM3, BSIM4, PSP, HiSIM, HiSIM/HV, EKV, HICUM, VBIC, MEXTRAM, BSIMSOI models, and TFT models etc., covering all IC technologies.

Mentor Graphics device modeling ex-perts participate in the Compact Model-ing Council (CMC) and contribute to the support and continuous improvements of the state-of-the-art complex device mod-els that are needed for technology nodes at 45 nm, 32 nm, and below.

Mentor Graphics strictly respects and accurately imple-ments community approved standards, while at the same time aggressively optimizing performance. As a result, sophisticated device models such as PSP run significantly faster in Eldo Classic and Eldo Premier than in any other competitive simulator.

VERILOG-A SUPPORT OPTIONThe Eldo Verilog-A option complements Eldo Premier with a state-of-the-art Verilog-A compiler, compatible

with the Verilog-AMS compiler in Mentor Graphics Questa® ADMS mixed-signal simulator. Compiling and including Verilog-A modules in a netlist is easy and often allows significant speedup for system-level simulations or architectural exploration tasks. Verilog-A can also be used to extend core device models, such as BSIM4 or PSP, with additional custom parasitic effects for RF, high-voltage, or other specializedapplications.

WAVEFORM ANALYSIS WITH EZWAVEThe EZwave™ graphical post-processor is the natural companion of Eldo Premier for waveform analysis and post-processing. The native waveform format of EZwave, called “wdb,” is extremely efficient for the manipulation of huge databases. EZwave can load gi-gabytes of data in seconds. EZwave can also load most popular waveform formats. And of course it operates on both analog and digital signals—the ideal solution for analog and mixed-signal applications.

Eldo Premier simulation for a VCO.

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Visit our website at www.mentor.com/dsmCopyright © 2012 Mentor Graphics Corporation. Mentor products and processes are registered trademarks of Mentor Graphics Corporation.All other trademarks mentioned in this document are trademarks of their respective owners.

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DESIGN FRAMEWORK INTEGRATIONAND COMPATIBILITYEldo Premier is fully integrated in Mentor Graphics IC-Flow and in Cadence ADE, and all functions including netlisting, analysis and options setup, cross-probing, and back-annotation are fully supported and available at no charge. In the Cadence context, sophisticated utilities create the Eldo views and libraries or designers can make direct use of existing libraries already format-ted for other simualtors.

Eldo Premier supports both HSPICE® and Spectre® formatted netlists. Eldo Premier supports the .tr0/.mt0, .psf, .fsdb, and .wdf output formats for interoperability with other viewers.

FOUNDRY SUPPORTEldo is supported by all major foundries that deliver certified Eldo electrical models to their customers. Eldo can also read and simulate netlist and libraries format-ted for other popular simulators such as HSPICE and Spectre without modifications.

The Mentor Graphics Custom IC flow and its integrated schematic, extraction, and

simulation tools allow you to take a design from system specifications to post-layout

verification with a virtually seamless approach.