eecs 373 midterm 2 exam - eecs.umich.edu · throughout the exam “standard logic gates” means...

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EECS 373 Midterm 2 Exam Winter 2018 Name: ___SOLUTION_____________________ unique name: _______________ Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. ___________________________________ Scores: Problem # Points 1 /15 2 /15 3 /15 4 /15 5 /40 Total /100 NOTES: There are 16 pages including this one. Closed book, closed notes. Calculators are allowed, but no PDAs, Portables, Cell phones, etc. Don’t spend too much time on any one problem and be sure you get to the design problem with plenty of time to spare. You have about 120 minutes for the exam. Be sure to show work and explain what you’ve done when asked to do so. Getting partial credit without showing work will be rare. Throughout the exam “standard logic gates” means arbitrary input ANDs, ORs, NANDs, NORs, XORs and XNORs as well as NOT gates. Do not write on the back of pages, as they will not scan into the grading system. An additional page is left at the end if you need additional space. Page 1 of 16

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Page 1: EECS 373 Midterm 2 Exam - eecs.umich.edu · Throughout the exam “standard logic gates” means arbitrary input ANDs, ORs, NANDs, NORs, XORs and XNORs as well as NOT gates. Do not

EECS 373 Midterm 2 Exam

Winter 2018

Name: ___SOLUTION_____________________ unique name: _______________

Sign the honor code:

I have neither given nor received aid on this exam nor observed anyone else doing so.

___________________________________

Scores:

Problem # Points

1 /15

2 /15

3 /15

4 /15

5 /40

Total /100

NOTES: There are 16 pages including this one. Closed book, closed notes.

Calculators are allowed, but no PDAs, Portables, Cell phones, etc. Don’t spend too much time on any one problem and be sure you get to the

design problem with plenty of time to spare. You have about 120 minutes for the exam. Be sure to show work and explain what you’ve done when asked to do so. Getting

partial credit without showing work will be rare.

Throughout the exam “standard logic gates” means arbitrary input ANDs, ORs,

NANDs, NORs, XORs and XNORs as well as NOT gates.

Do not write on the back of pages, as they will not scan into the grading system. An

additional page is left at the end if you need additional space.

Page 1 of 16

Page 2: EECS 373 Midterm 2 Exam - eecs.umich.edu · Throughout the exam “standard logic gates” means arbitrary input ANDs, ORs, NANDs, NORs, XORs and XNORs as well as NOT gates. Do not

1. Interrupts [15 pts]

Part A

Write a generic function in C which would set the priority of a certain interrupt, given desired preemption and subpriority values. The interrupt

priority register ranges from address 0xE000E400 - 0xE000E4EF, with each byte in the register storing the priority for a single interrupt. Assume

that the board is set to PRIGROUP 6, and that all possible priorities are implemented.

void setIntPriority(int interrupt, int subPriority, int

preemption) {

uint8_t* baseAddr = (uint8_t*)0xE00E400;

baseAddr += interrupt;

uint8_t priority = (preemption << 7) | subPriority; *baseAddr = priority;

}

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Page 3: EECS 373 Midterm 2 Exam - eecs.umich.edu · Throughout the exam “standard logic gates” means arbitrary input ANDs, ORs, NANDs, NORs, XORs and XNORs as well as NOT gates. Do not

Part B

You are an intern at NASA tasked with assigning priorities to various interrupts on the Mars Rover. The interrupts are related to checking the battery, collecting data, motion planning, and communicating with Earth. If the robot checks its battery and finds it is low, it will enable its solar panels in order to charge. Assume that the battery check interrupt occurs at the frequency at which it is set to occur, then it will be impossible for the battery to run out. The board on the Mars Rover is set to be on PRIGROUP 5 and the priorities of the 4 interrupts are given below.

Interrupt Priority

Battery check 0x00

Communicate 0x74

Motion Planning 0xA5

Collect Data 0xF3

Explain a situation in which the Mars Rover under these settings could

run out of battery.

NOT GRADED

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Page 4: EECS 373 Midterm 2 Exam - eecs.umich.edu · Throughout the exam “standard logic gates” means arbitrary input ANDs, ORs, NANDs, NORs, XORs and XNORs as well as NOT gates. Do not

Part C

Briefly explain how “Late Arrival” support uses “Tail Chaining” to improve

interrupt performance on ARM systems. Be sure to indicate the advantages

and how they are achieved.

From

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0337e/DDI0337E_cort

ex_m3_r1p1_trm.pdf 5.6 and 5.7

Page 5: EECS 373 Midterm 2 Exam - eecs.umich.edu · Throughout the exam “standard logic gates” means arbitrary input ANDs, ORs, NANDs, NORs, XORs and XNORs as well as NOT gates. Do not
Page 6: EECS 373 Midterm 2 Exam - eecs.umich.edu · Throughout the exam “standard logic gates” means arbitrary input ANDs, ORs, NANDs, NORs, XORs and XNORs as well as NOT gates. Do not
Page 7: EECS 373 Midterm 2 Exam - eecs.umich.edu · Throughout the exam “standard logic gates” means arbitrary input ANDs, ORs, NANDs, NORs, XORs and XNORs as well as NOT gates. Do not

2. Timers [15 pts]

You have a robot named Renee 2.0, who has a few different tasks

that must be handled at different time intervals. She has:

A motor driven by a PWM signal with 75% duty cycle and 200 Hz

Bumper sensors that should be sampled every second

A Lidar scanner that sends pulses at 100kHz

Headlights that toggle every second

A temperature sensor that samples every 5 minutes

a. Please describe how to use two hardware timers clocked at 50MHz and

additional virtual timers to handle monitoring and sampling the sensors.

Please explain how to set the overflow and/or compare values and what is done at overflow and/or compare for each of the timers. Describing what

is done with the sensors’ data and how to implement what is done is not necessary. If there is a virtual/hardware timer you do not need, write N/A

under that timer.

(Multiple possible answers, but here is one) Hardware Timer 1: Overflow Value: 500

At overflow send lidar pulse

Hardware Timer 2: Overflow Value: 250000 Compare Value: 187500

At compare send PWM signal from high to low. At Overflow send PWM signal from low to high

Virtual Timer 1: Based on Hardware Timer 2: Overflow Value: 200

At overflow toggle headlights and sample the bumpers.

Virtual Timer 2: Based on Hardware Timer 2: Overflow Value: 60000

Sample the temperature sensor at Overflow

Virtual Timer 3: N/A

Page 8: EECS 373 Midterm 2 Exam - eecs.umich.edu · Throughout the exam “standard logic gates” means arbitrary input ANDs, ORs, NANDs, NORs, XORs and XNORs as well as NOT gates. Do not

3. Serial Busses [15 pts]

You are tasked with communicating with an accelerometer over I2C.

You are trying to read the acceleration along the x -axis by reading from

the address 0x48. You put the transaction on the Salae and see that it is

not the data you expected. Here is the timing diagram:

Why was the data different than you expected? The read/write bit should be high for a read.

Page 6 of 16

Page 9: EECS 373 Midterm 2 Exam - eecs.umich.edu · Throughout the exam “standard logic gates” means arbitrary input ANDs, ORs, NANDs, NORs, XORs and XNORs as well as NOT gates. Do not

You are now tasked with writing the code for a I2C write transaction to a

16- bit DAC. You want to output approximately 1V from the DAC. Assume

the reference voltage is 5V and ignore quantization error. The address for

writing to the DAC in 0x49. Assume the SmartFusion is running at 40MHz

and the DAC has a maximum I2C speed of 1MHz. You want the

transmission to be as fast as possible. Fill in the blanks in the code below:

#include <stdio.h>

#include <inttypes.h>

#include "drivers/mss_i2c/mss_i2c.h"

#define TARGET_ADDRESS 0b1001001

int out1v()

{

uint8_t transmit_buf[] = { 0x33, 0x33 };

uint8_t receive_buf[10];

MSS_I2C_init(&g_mss_i2c1 , TARGET_ADDRESS,

MSS_I2C_PCLK_DIV_60);

MSS_I2C_write

(

&g_mss_i2c1,

TARGET_ADDRESS,

transmit_buf,

sizeof(transmit_buf), // 2

MSS_I2C_RELEASE_BUS

);

MSS_I2C_wait_complete(&g_mss_i2c1,

MSS_I2C_NO_TIMEOUT);

return(0);

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Answer the following questions about serial interfaces:

a. The peripheral you are using has both I2C and UART available as options. Dedicated hardware for both are unused on your SmartFusion. Which one is the higher performance option and why?

I2C because it is faster.

b. You are designing an embedded system and trying to decide

which microcontroller to use on our board. Keeping the price down

is the highest priority. One peripheral you are communicating with

can interface with can communicate over SPI and UART. Which

serial interface is better for this situation and why? UART because it uses fewer pins and pins are money.

c. Consider the serial interfaces we covered in class (I2C, SPI,

UART). For which one do the devices communicating have to

predetermine the speed at which data will be transmitted and why? UART because it is asynchronous.

Page 8 of 16

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4. DAC/ADC [15 pts] a. Using 2-3 sentences, describe monotonicity and why it is important for ADCs/DACs.

Monotonicity is when the output voltage/number continues to increase or stay the same over time with increasing input. This is important to ADCs/DACs because they are converting ways to represent data and should match the linear rise of input. If the output is not increasing with increasing input, this could cause large inaccuracies in the data.

b. Consider the following 3-bit ADC. Draw the conversion transfer function (binary vs. input

voltage) on the top graph. Draw the quantization error transfer function (error voltage vs. input voltage) on the bottom graph. Make sure transition points are clear. Assume Vref is 5V. Clearly show any work below the graph to receive partial credit.

Page 12: EECS 373 Midterm 2 Exam - eecs.umich.edu · Throughout the exam “standard logic gates” means arbitrary input ANDs, ORs, NANDs, NORs, XORs and XNORs as well as NOT gates. Do not

5. Design Problem: XY Plotter [40 Points]

Overview

Your task is to implement the motor control for an XY plotter. Two motors will position the XY plotter

head by turning one way or the other for some number of rotations to position the plotter head. The X

and Y motors will be controlled with single bit signals that will turn them on and off and control

whether they spin clockwise or counter clockwise. The motors also have an integrated sensor that

produces several pulses per rotation. Consequently, the plotter head can be positioned from a known

starting point by counting the pulses.

Positioning Hardware

The pulses will be counted with a hardware counter. The count value will be continuously compared to

a MMIO compare register. If the compare value is equal to the count value, an interrupt will be

generated to notify the software that the motor has finished rotating the designated number of counts.

Since we will be controlling two motors, we will need two counters and compare registers. To verify that

both counters have reached their compare values, the compare equal bit will have to be read by the

software via MMIO.

Software Function

Setting the compare value, motor direction and turning the motors on and off will be handled by a

software driver you will write. Stopping the motor will be handled in an interrupt that you will write.

Considerations and Design Assumptions

1. The pulses that come from the rotational sensors are not synchronous with your hardware

clock (PCLK). 2. FABINT is a 10ns high pulse. 3. You can assume the XY plotter was initialized to X position = 0, Y position = 0; 4. A 32-bit counter is sufficient size and should be used for the rotational pulse counter. 5. PCLK is 100MHz

Memory Mapped IO Addresses: Table 1

Register Address Bit Map

X Counter Register 0x40050000, 32 bit read write 31 MSB, 0 LSB

Y Counter Register 0x40050004, 32 bit read write 31 MSB, 0 LSB

X Counter Compare Register 0x40050008, 32 bit read write 31 MSB, 0 LSB

Y Counter Compare Register 0x4005000C, 32 bit read write 31 MSB, 0 LSB

Motor Control Register 0x40050010, 32 bit read write Bit 0 X Motor On/Off, Bit 1 X Motor DIR Bit 2 Y Motor On/Off, Bit 3 Y Motor DIR

Compare Status Register 0x40050014, 32 bit read only Bit 0 X Compare, Bit 1 Y Compare

There are 3 parts to this problem. Read them all before doing any one part.

Consider how the functionality will be divided across the parts.

Page 10 of 16

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Part 1: Hardware Design (20pts) Provide the Verilog that implements the motor rotational pulse counters, interrupt generation and

MMIO interface listed in Table 1. The following module interface is provided along with its decleration.

module bob( /*** APB3 BUS INTERFACE ***/ input PCLK, // clock input PRESERN, // system reset input PSEL, // peripheral select input PENABLE, // distinguishes access phase output wire PREADY, // peripheral ready signal output wire PSLVERR, // error signal input PWRITE, // distinguishes read and write cycles input [31:0] PADDR, // I/O address input wire [31:0] PWDATA, // data from processor to I/O device (32 bits) output reg [31:0] PRDATA, // data to processor from I/O device (32-bits) /*** I/O PORTS DECLARATION ***/ output reg FABINT, output xmon, // x motor on or off, logical 1 is on output

xmdir, // x motor direction, logical 1 is clockwise output

ymon, // y motor on or off, logical 1 is on output ymdir,

// y motor direction, logical 1 is clockwise input xmp, // x motor compare register status, 1 is equal 0 is not equal

input ymp ); // y motor compare register status, 1 is equal 0 is not equal

Two answer pages follow. Please use these pages instead of writing on the back.

Hint: Organize your answer into functional sections. Variable declaration, MMIO interface,

rotational pulse counter, etc.

Page 11 of 16

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Part 1: Hardware Design (answer page 1) assign PSLVERR = 0; assign PREADY = 1;

wire write = PENABLE & PSEL & PWRITE; wire read = PENABLE & PSEL & !PWRITE; reg [31:0] comparex, comparey, mcontrol, countx, county; reg Q0, Q1, xmpsynch, ympsynch, xeq, yeq, F1, F2;

/* assign motor control bits */ assign xmon = mcontrol[0]; assign xdir = mcontrol[1]; assign xdir = mcontrol[2]; assign xdir = mcontrol[3];

/*mmio interface */ always @(posedge PCLK) begin /* MMIO */ if (write) begin case (PADDR[7:0]) 'h0: countx <= PWDATA; 'h4: county <= PWDATA; 'h8: comparex <= PWDATA; 'hC: comparey <= PWDATA; 'h10: mcontrol <= PWDATA; default: countx <= PWDATA; endcase end else if (read) begin case (PADDR[7:0]) 'h0: PRDATA <= countx; 'h4: PRDATA <= county; 'h8: PRDATA <= comparex; 'hC: PRDATA <= comparey; 'h10: PRDATA <= mcontrol; 'h14: PRDATA <= {30'b0, yeq, xeq}; default: PRDATA <= countx; endcase end

Page 15: EECS 373 Midterm 2 Exam - eecs.umich.edu · Throughout the exam “standard logic gates” means arbitrary input ANDs, ORs, NANDs, NORs, XORs and XNORs as well as NOT gates. Do not

/* synch pulses */ Q0 <= xmp; xmpsynch <= Q0; Q1 <= ymp; ympsynch <= Q1;

/* count pulse */ if ( countx == comparex) xeq <= 1; if ( county == comparey) yeq <= 1; if (xmpsynch & !xeq) countx <= countx+1; if (ympsynch & !yeq) county <= county+1;

/* FABINT generation needs rising edge detection*/ Q0 <=xeq; Q1 <= Q0; F1 <= Q0 & !Q1; Q0 <=yeq; Q1 <= Q0; F2 <= Q0 & !Q1; FABINT <= F1 | F2; end endmodule

Page 16: EECS 373 Midterm 2 Exam - eecs.umich.edu · Throughout the exam “standard logic gates” means arbitrary input ANDs, ORs, NANDs, NORs, XORs and XNORs as well as NOT gates. Do not

Part 2: Software: Motor Driver (10pts) Wirte a C function that turns the motor on and off, sets the direction and the number of counts the motor

must travel from the current position. Assume you do not know the current count for the sensor rotational

pulses. Each motor will have its own driver. You need only write the driver for motor_x

void motor_x(int monoff, int mdir, int counts) ;

monoff turns the motor on and off. Logical 1 is on and logical 0 is off.

mdir sets the direction of the motor. Logical 1 turns the motor clockwise, logical 0 turns counter

clockwise.

counts are the number of pulses the motor must rotate from the current position.

void motor(int monoff, int mdir, int counts){ int* counterx = (int *)0x40050000; int* comparex = (int *)0x40050008; int* mcontrol = (int *)0x400500010;

*counterx = 0; *comparex = counts;

*mcontrol &=FFFC;

*mcontrol |=monoff|(mdiv<<1)

}

Page 17: EECS 373 Midterm 2 Exam - eecs.umich.edu · Throughout the exam “standard logic gates” means arbitrary input ANDs, ORs, NANDs, NORs, XORs and XNORs as well as NOT gates. Do not

Part 3: Software: Compare Interrupt (10pts) Complete the following interrupt compare function that will stop the motors once the compare value is

reached. No other control features or registers should be changed.

_attribute_((interrupt)) void Fabric_IRQHandler( void ) { int* status = (int *)0x40050014; int* mcontrol = (int *)0x400500010;

if ()*status & 1) *mcontrol = *mcontrol & 0xfffe; if ()*status & 2) *mcontrol = *mcontrol & 0xfffb; }