ece 331 – digital system design single-bit adder circuits (lecture #11)

ECE 331 – Digital System Design

Single-bit Adder Circuits

(Lecture #11)

ECE 331 - Digital System Design 2

The Half Adder (HA)



Binary Addition

0 0 1 1+ 0 + 1 + 0 + 1 0 1 1 10

Sum Carry Sum


The Half Adder

A B Sum Carry

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Sum = A'.B + A.B' = A xor B

Carry = A.B


The Half Adder

HA

(c) Circuit (d) Graphical symbol

A

BSum

Carry

A

B

Sum

Carry


LIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY halfadd ISPORT ( A, B : IN STD_LOGIC ;

Sum, Cout : OUT STD_LOGIC ) ;END halfadd ;

ARCHITECTURE LogicFunc OF halfadd ISBEGIN

Sum <= A XOR B;Cout <= A AND B;

END LogicFunc ;

The Half Adder in VHDL

Filename: halfadd.vhdl

Contains both the entity andthe architecture statements


The Full Adder (FA)



Binary Addition

0 0 0 00 0 1 1

+ 0 + 1 + 0 + 1 0 1 1 10

Carry-out Sum

1 1 1 10 0 1 1

+ 0 + 1 + 0 + 1 1 10 10 11

Carry-in


The Full Adder

A B Cin Sum Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1


The Full Adder

Sum = A xor B xor Cin

Cout = A.B + A.Cin + B.Cin

00 01 11 10

0

1 1

1

1

1

A B

Cin 00 01 11 10

0

1 1

1

1 1

A B

Cin

Sum Cout


The Full Adder

A

B

Cin

Sum

Cout



ENTITY fulladd ISPORT ( Cin, A, B : IN STD_LOGIC ;

Sum, Cout : OUT STD_LOGIC ) ;END fulladd ;

ARCHITECTURE LogicFunc OF fulladd ISBEGIN

Sum <= A XOR B XOR Cin ;Cout <= (A AND B) OR (Cin AND A) OR (Cin AND

B) ;END LogicFunc ;

The Full Adder in VHDL


The Full Adder

HA

HAs

c

s

c

(a) Block diagram

(b) Detailed diagramHalf Adder

Half Adder

A

B

Cin

A

B

Cin

Sum

Cout

Sum

Cout



Construct Full Adder from two Half Adders Use Structural VHDL Realize using hierarchical design

Design half adder Interconnect half adders Include any additional logic


VHDL: Components Specify the logical sub-circuits (i.e. components) that

will be used in the hierarchical design. Define the interface to the sub-circuit.

Uses the same format as the Entity Statement.

Sub-circuits are interconnected using “wires”. This is known as Structural VHDL.

The architecture statement for the sub-circuit may be included in the same file as the upper level design or in a separate file.

If included in a separate file, it must be compiled prior to compilation of the upper level design.


VHDL: Components

COMPONENT <component name> PORT ( <interface signals> : mode

type ) ;END COMPONENT ;

Component Statement

Component Instantiation

<instance name> : <component name> PORT MAP ( <component port names> => <signal

names> ) ;

<instance name> : <component name> PORT MAP ( <signal names> ) ;

named association

positional association



Half Adder

Half Adder

A

B

CinSum

Cout

ports

ports


ENTITY fulladd ISPORT ( Cin, A, B : IN STD_LOGIC

; Sum, Cout : OUT STD_LOGIC ) ;

END fulladd ;

18


Half Adder

Half Adder

A

B

CinSum

Cout

signals

signal

ARCHITECTURE Structure OF fulladd IS SIGNAL s1, c1, c2: STD_LOGIC ; COMPONENT halfadd PORT ( A, B : IN STD_LOGIC ;

Sum, Cout : OUT STD_LOGIC ) ; END COMPONENT ;BEGIN ha1 : halfadd PORT MAP ( A => A, B => B, Sum => s1, Cout => c1 ) ; ha2 : halfadd PORT MAP ( A, B, Sum, c2 ); Cout <= c1 OR c2 ;END Structure ;

componentinstantiation

named association

positional association

componentdeclaration


VHDL: Packages

Packages (and libraries) allow frequently used functions and components to be “centrally” located.

Component declarations are included in package files rather than in the VHDL code for the hierarchical design.

The associated VHDL models for the components are included in separate files.

The compiled VHDL models are typically included in the same library.

When the package file is compiled, the package is created and stored in the working directory.


VHDL: Packages

Package DeclarationLIBRARY ieee ;USE ieee.std_logic_1164.all ;

PACKAGE <package name> IS<package declarations> ;

END <package name> ;

Package DeclarationLIBRARY work ;USE work.<package name>.all ;


The Full Adder in VHDL(The Package File)


PACKAGE halfadd_package ISCOMPONENT halfadd

PORT ( A, B: IN STD_LOGIC ; Sum, Cout: OUT

STD_LOGIC ) ;END COMPONENT ;

END halfadd_package ;


The Full Adder in VHDL(The Design File)

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE work.halfadd_package.all ;

ENTITY fulladd ISPORT ( Cin, A, B : IN STD_LOGIC ; Sum, Cout : OUT STD_LOGIC ) ;

END fulladd ;

ARCHITECTURE Structure OF fulladd IS SIGNAL s1, c1, c2: STD_LOGIC ;BEGIN ha1 : halfadd PORT MAP ( A => A, B => B, Sum => s1, Cout => c1 ) ; ha2 : halfadd PORT MAP ( A, B, Sum, c2 ); Cout <= c1 OR c2 ;END Structure ;


Multi-bit Adder Circuits


Implementations of Multi-bit Adders:

1. Ripple Carry Adder2. Carry Lookahead Adder


Ripple Carry Adder


Ripple Carry Adder

1 0 1 0

1 0 0 1+

1 Carry-in

0 1 0 01Carry-out

11

Carry ripples from one column to the next


FA

x n – 1

c n c n 1 ”

y n 1 –

s n 1 –

FA

x 1

c 2

y 1

s 1

FA

c 1

x 0 y 0

s 0

c 0

MSB position LSB position

Ripple Carry Adder

Carry ripples from one stage to the next

Carry-inCarry-out


Ripple Carry Adder

n-bit Ripple Carry Adder Composed of n 1-bit Full Adders Carries ripple from LSB stage to MSB stage

Delay ~ (n)*(delay of single FA stage) Area required is linear in n

4-bit Ripple Carry Adder Composed of 4 1-bit Full Adders


The Ripple Carry Adder is slow!

Why?

How can the speed of the adder be increased?

ece 331 – digital system design single-bit adder circuits (lecture #11)

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