ripple-free multiphase interleaved stacked converter for high

IEEE POWER ELECTRONICS REGULAR PAPER/LETTER/CORRESPONDENCE

Ripple-free Multiphase Interleaved Stacked Converter for High-power Applications

Mohammed A. Alharbi, Student Member, IEEE, Mohamed S. A. Dahidah, Senior Member, IEEE, Saleh A. Ali,

Salaheddine Ethni, and Volker Pickert, Member, IEEE

Abstract- A novel control technique that guarantees a

ripple-free output current and voltage of a DC-DC multiphase staked interleaved converter is proposed. The conventional multiphase interleaved converters have been extensively used in various applications. However, ripple cancellation in these converters solely depends on the number of phases and can only be achieved at specific duty cycles. On the other hand, wide-range and ripple-free output are important paramount features for many modern applications. Therefore, the presented converter aims to combine the advantages of both the multiphase interleaved and the stacked converters into a single-unit converter suitable for high-power applications. Ripple-free output current/voltage is always guaranteed regardless of the number of phases and duty cycle values. This feature is accomplished by adding a fractionally-rated phase-leg to the conventional multiphase interleaved converter and modulating it with the proposed control approach. The Configurable Logic Block (CLB), a state-of-the-art tool developed by Texas Instruments, is utilized to reduce the hardware size of the entire conversion system while increasing its speed and flexibility. Extensive simulation studies are carried out to confirm the functionality of the proposed control scheme. A laboratory porotype is developed to validate the effectiveness of the proposed control method experimentally. With only a few more components, significant reductions in output ripples are achieved.1

Keywords- Ripple cancellation, DC-DC converters,

Stacked converter, Multiphase converter, Configurable logic block.

I. INTRODUCTION In response to global warming and environmental concerns,

energy storage systems (ESSs) such as batteries, fuel cells (FCs), and ultracapacitors (UCs) have recently been actively researched. ESSs are integral parts of renewable energy sources (RESs) deployment to ensure high reliability, lower cost, and meeting peak load demand. They are also exceptionally vital for transport applications such as FC vehicles (FCVs), hybrid

M. Alharbi is with the School of Engineering, Newcastle University, Merz

Court, Newcastle upon Tyne, NE1 7RU, United Kingdom and also with the Department of Electrical Engineering, Taibah University, Medina 42353, Saudi Arabia, (e-mail: [email protected]; [email protected]). M. Dahidah, S. Ali, S. Ethni and V. Pickert are with the School of Engineering, Newcastle University, Merz Court, Newcastle upon Tyne, NE1 7RU, United

electric vehicles (HEVs), and battery EVs (BEVs), in which energy storage technologies, such as battery cell, FC, and UCs are the main source of power [1], [2]. Depending on the technology and the application, ESSs are always integrated with power electronics converters to regulate their output voltage or current to the required level. The main desirable features of those converters are efficiency, load-transient response, current and voltage ripples, cost, and size [3]. The use of smaller output filter inductors can help acquire superior results for these features at the expense of a higher current ripple at the output side of the converter. However, the impact of high current ripple on the lifetime and the performance of EESs cannot be ignored and may degrade the quality of the output power, particularly in high current applications [4]. Therefore, in order to extend the lifetime of EESs and improve the efficiency and reliability of the overall system, ripples in these converters must be reduced [5].

Several studies have looked at the adverse impacts of AC ripple on ESSs. Authors in [6]–[10] have reported that current ripples on FC systems significantly increase losses, resulting in fuel waste and a considerable reduction in FCs durability and lifespan. Specifically, the work in [11] reported shown that by reducing the ripple from 24.3% to 9.9%, the efficiency of an FC system increases by around 2%. Hence, reducing or eliminating output current ripple is one of the primary characteristics expected to maximize the lifespan and efficiency of an FC system. Similarly, different studies have evaluated the impact of current ripples on battery performance [12]–[22]. A recent critical review on the impact of ripples or pulse charging of Li-ion batteries is presented in [12]. Superimposed AC ripples have been shown in [13]–[15] to have an adverse influence on the degradation of Li-ion batteries, increasing capacity fading by up to 3%. Moreover, ripples in the charging or discharging current result in additional heating losses for Li-ion batteries, increasing the cell temperature and reducing the battery's lifespan, as reported in [16]–[21]. Furthermore, when the temperature of the battery rises due to current ripple, internal heat is generated, raising the risk of potential safety concerns such as thermal runaway [22]. Ultracapacitors have also been utilized in various high-power applications due to their high power capability and long cycle life [23], [24]. However, a

Kingdom (e-mail: [email protected]; [email protected]; [email protected]; [email protected]).

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constant current ripple can cause a supercapacitor to overheat, decreasing its lifespan [25]. Voltage and current ripples also affect the resolution and precision of measurement instruments in power electronic converters, which are commonly used to interface ESSs with electric power networks [26]. Conduction losses are also created in passive components and proportionally increased with higher current ripples. Consequently, the overall efficiency of power converters may be degraded [27].

In order to avoid the adverse effects of AC ripples on ESSs and the efficiency of power electronic converters, many ripple minimization techniques have been discussed in the literature, which are mainly divided into three types. The first common type uses passive components in DC-DC converters. Bulky inductors (L) and capacitors (C) or even several LC filters are used for such ripple reduction techniques [28], [29]. This method, however, results in increased system size and affects the converter's transient response. Particularly in high current applications, where the AC ripple effects on the parasitic components of the filters are prominent [30]. The second ripples minimization approach uses multiphase interleaved converters [31]–[33]. In these topologies, the ripples are easily reduced by phase-shifting the ripple waveform of each phase, resulting in a reduced ripple in the final synthesized overall input/output currents. Although multiphase interleaved converters have been successfully employed for high current applications and have been shown to reduce overall ripples, the degree of ripple cancellation or reduction solely depends on the duty cycle and the number of phases. For instance, a complete ripple cancellation in a two-phase interleaved converter can only be achieved at a 50% duty cycle. The amount of the output ripple produced varies across all the other duty cycles. More phases can be used to reduce the ripples at the cost of increasing the size and cost of the system. Different configurations of multiphase interleaved converters for EV battery fast charging applications with complex control strategies have been proposed in [34], [35], generating ripple-free output current across wide output voltage ranges. The author in [36] proposes a technique for controlling ripple suppression in multiphase converters using logic circuits; however, it cannot ensure ripple cancellation when the duty cycle or number of phases is changed, and the results have not been experimentally validated. The third common ripple minimization approach uses a stacked converter [37], [38], which consists of two phases: the first phase conducts the output current, and the second phase is used for ripple cancellation purposes. As only a single phase is used to handle the output current, this topology is inefficient for high-current applications.

It is evident that ESS applications are increasingly growing, particularly for high-power applications such as power systems and electrified transportation. Therefore, the development of highly efficient and cost-effective power electronic converters that facilitate the integration of those ESSs is becoming extremely important than ever. The work presented in this paper addresses the above-discussed limitations by combining the features of multiphase interleaved converters and stacked converters in a single unit. The main contributions of this paper

are summarized as follows: 1) adding a partially-rated phase-leg to the multiphase interleaved converter suitable for high-power (current) applications (e.g. extreme fast chargers for EVs). This offers superior performance in terms of ripple elimination, which impacts the lifetime of batteries and other EEs, without sacrificing the volume and/or the cost of the overall system. The DC-DC converter proposed in this paper is referred to as a multiphase interleaved stacked converter (ISC). 2) Propose a cost-effective and simple control approach based on logic circuits that allows the interleaved converter to achieve ripple-free operation over the entire duty cycle range. This was not possible with the conventional interleaved converter, limiting its performance and ability to reduce the ripples, particularly for applications with a broad output voltage range. The proposed control technique can be implemented digitally using Texas Instruments' Configurable Logic Block (CLB) tool, avoiding the need for extra hardware. This, in turn, reduces the cost/size further and increases the system’s overall reliability.

The remainder of the manuscript is organized as follows: the conventional ripple minimization methods for DC-DC converters are highlighted in Section II. The architecture of the proposed converter, along with the proposed control technique, are presented in Section III. The simulation and experimental results are then provided in Sections IV and V, respectively, to demonstrate the validity of the proposed control technique.

II. CONVENTIONAL RIPPLE MINIMISATION METHODS FOR DC-DC CONVERTERS

A. Ripple Minimization Using Passive Filtering Techniques One common method to reduce voltage and current ripples

in DC-DC converters is to apply a high switching frequency. However, this comes at the expense of increased switching losses, thereby reducing the overall efficiency of the converter [39]. Using larger passive filtering (with bulky capacitors and inductors) is another means of ripple reduction. However, increasing the inductor size degrades the transient response speed of the converter. Furthermore, the size and cost of the converter also increase [40], [41].

The voltage ripple is also influenced by the capacitor's internal series resistance (ESR), where the ripple increases as the value of ESR increases. Ceramic capacitors have a low ESR value, but their cost is high for high capacitance values. In contrast, aluminum electrolytic tantalum capacitors are comparatively low-cost for higher capacitance; nonetheless, their ESR is substantially higher, which results in a higher ripple [42]. Many designers attempt to decrease the value of ESR by connecting many capacitors in parallel. However, this approach increases the cost and size of the converter, making it impractical [43].

An alternative method to improve ripple filtration is to use an additional LC filter [44]. This technique, however, results in a fourth-degree system, increasing the complexity of the controller. As the order of the filter increases, the control stability of systems decreases, impacting overall performance [43]. In short, the passive filtering technique in DC-DC converters leads to an increase in component count, resulting in converters of higher weight, volume, and cost.


B. Multiphase Interleaved DC-DC Converter

Fig. 1 N-Phase Multiphase Interleaved Buck Converter.

The multiphase interleaved converter topologies offer many advantages, such as reduced input and output voltage/current ripples and increased efficiency by equally sharing the total power between the N phases of the converter [45]. Fig. 1 shows an N-phase interleaved buck converter (IBC) schematic diagram. Each phase of the converter consists of an inductor and two active switches. The upper and lower active switches in each phase operate in a complementary manner, with a phase difference of 360°/N between them [46].

Fig. 2 shows the current ripple cancellation factor of the IBC (i.e., an example of 6-phase IBC). The total output current ripple of the IBC decreases as the number of phases increases. Only at certain combinations of duty cycle (D) and number of phases (N), (particularly at discrete duty cycle values, 𝐷𝐷𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑. =𝑘𝑘 𝑁𝑁⁄ , where 𝑘𝑘 = 1,2, … ,𝑁𝑁 − 1), the output current ripple is completely eliminated. For example, a two-phase interleaved converter achieves a complete ripple elimination only at a duty cycle of 50%. Hence, the degree of reduction of current ripples in multiphase interleaved converters relies on both the number of interleaved phases and the duty cycle [46]. For this reason, multiphase interleaved converters are not the best option for applications that require a wide range of operational duty cycles, as they are incapable of eliminating ripples throughout the whole duty cycle range.

Fig. 2 Current ripple cancellation factor of IBC vs. duty cycle.

C. Stacked Buck Converter The stacked buck converter is an alternative topology that

offers ripple cancellation using an auxiliary phase. The main advantage of this topology is the ability to produce ripple-free output across the whole range of the duty cycle using only two phases. The basic stacked converter consists of two phases, primary and auxiliary, as shown in Fig. 3.

Fig. 3 Stacked buck converter topology.

The primary phase (S1, L1, and Co) is responsible for handling both the DC current required by the load and the AC current ripple, which has a triangular shape of a similar to that of a conventional buck converter. This phase operates with a duty cycle D. The auxiliary phase (Sx, Lax, and Cax), on the other hand, carries only the inductor’s AC current ripple, while the DC component is blocked by Cax. The auxiliary phase operates in a complementary manner to the primary phase with a duty cycle 1-D, resulting in inverted AC ripples in both phases. Consequently, the auxiliary phase continuously generates a compensating current that eliminates the current ripple produced by the primary phase for all duty cycle values [36], [38].

Fig. 4 shows a comparison of the current ripple cancellation factors of the conventional buck, stacked, and multiphase converters. Clearly, the primary benefit of the stacked converter is its ability to produce a ripple-free output current regardless of the duty cycle using only an extra phase. However, since the output current flows only in one phase, this converter is not suitable for high-current applications, necessitating the use of multiphase interleaved converters [47].

Fig. 4 Comparison of current ripple characteristics.


III. PROPOSED DESIGN AND CONTROL A hybrid version of the multiphase interleaved and stacked

converters is proposed in this paper to blend the advantages of both types. However, the challenge is to operate the auxiliary switches in a complementary manner in order to produce the compensating current that cancels out the ripple produced by the converter’s primary phases over the whole range of duty cycles. Like the conventional stacked converter, the proposed multiphase ISC can completely suppress ripples regardless of the number of phases or duty cycle values, as illustrated in Fig. 4, with the additional benefit of accommodating high current operation.

In the proposed converter, a simple logic gate circuitry is designed to provide the required operation of the auxiliary switches, which enables the total elimination of output voltage/current ripples. By cancelling the current ripple, the filter size may be reduced significantly compared to other conventional DC-DC topologies, increasing the transient response. Another benefit of the proposed design is the improvement in efficiency and better thermal management that may be attained by lowering the operating switching frequency. Furthermore, the power loss of the output capacitor is also reduced since the ripple is eliminated. The proposed control technique is extraordinarily promising for applications that require low ripple and high current while utilizing a converter of smaller size and volume.

A. Circuit Description and Design Fig. 5 illustrates the overall configuration and control

approach of the proposed multiphase ISC. It is composed mostly of two circuits: main and auxiliary. The former comprises N interleaved phases along with the associated inductors Li, (where, 𝑖𝑖 = 1,2, … ,𝑁𝑁) of equal inductance and an output capacitor, Co. The latter is built using two switches (that is, one-phase) and a single inductor, Lax, and capacitor Cax. The main function of the primary circuit is to control the transfer of power within the system, while the auxiliary circuit is responsible for eliminating the ripples in the output side of the converter, regardless of the duty cycle and number of phases.

Fig. 5 General structure of the multiphase ISC and the proposed control.

As mentioned above, the upper and lower active switches of each phase of the primary circuit operate in a complementary manner, and each phase is shifted by 360°/N with respect to one another. The output current, 𝐼𝐼𝑜𝑜, is equally shared between all of the N operating phases of the primary circuit. The peak-to-peak inductor current, ∆𝐼𝐼𝐿𝐿 , of each individual phase and the combined ripple of the primary circuit, ∆𝐼𝐼𝑜𝑜, are represented by (1) and (2), respectively [48].

∆𝐼𝐼𝐿𝐿 =(𝑉𝑉𝑑𝑑𝑖𝑖 − 𝑉𝑉𝑜𝑜) ⋅ 𝐷𝐷

𝑓𝑓𝑑𝑑 ⋅ 𝐿𝐿 (1)

𝛥𝛥𝐼𝐼𝑜𝑜 = 𝑉𝑉𝑜𝑜

𝑓𝑓𝑑𝑑 ∙ 𝐿𝐿 �1 −

𝑚𝑚𝑁𝑁 ∙ 𝐷𝐷

� ∙ [1 + 𝑚𝑚 − 𝑁𝑁 ∙ 𝐷𝐷] (2)

where, D is the duty cycle, fs is the switching frequency, 𝐿𝐿 is the phase inductance, and 𝑚𝑚 = 𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓 (𝑁𝑁 ∙ 𝐷𝐷) is the maximum integer that cannot be greater than the product of 𝑁𝑁 ∙ 𝐷𝐷.

In contrast, the main purpose of the auxiliary circuit is to cancel ∆𝐼𝐼𝑜𝑜at any duty cycle value and for any number of phases. The capacitor Cax in the auxiliary phase blocks the DC current component and only allows the AC ripple to flow through this phase. Hence, the load output current only flows through the primary circuit, while the auxiliary phase's average DC current is zero. The ripple cancellation feature is improved with a higher value of 𝐶𝐶𝑎𝑎𝑎𝑎 at the expense of limiting the bandwidth of the controller. Furthermore, the inductor 𝐿𝐿𝑎𝑎𝑎𝑎 must be the same size as the other inductors in the primary circuit to produce the same ripple amplitude. Hence, 𝐶𝐶𝑎𝑎𝑎𝑎 is dependent on the trade-offs between size and the auxiliary phase ripple. Nonetheless, lower-rated and less expensive semiconductor devices can be utilized since the auxiliary phase typically carries a low current.

B. Control Strategy and Steady-State Operation The well-known average-current-mode control (ACMC) is

implemented first to guarantee equal current sharing among the phases of the primary circuit and to regulate the output voltage. The compensated signal of the control loop produced is compared with a fixed frequency sawtooth wave signal to generate the PWM signals to drive the power switches of the primary circuit. Generally, in the conventional multiphase interleaved converter, a ripple-free output current can be produced if the PWM signals of the primary circuit are switched on/off in a manner complementarily with one another. However, this can only be achieved if the duty cycle at 𝐷𝐷𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑. =𝑘𝑘 𝑁𝑁⁄ , where 𝑘𝑘 = 1,2, … ,𝑁𝑁 − 1 . For this reason, the main objective of the proposed control is to generate customized PWM gating signals that will drive the switches SXA and SXB of the auxiliary phase in a complementary way to that of the primary circuit. This task is performed by comparing the PWM signals of the primary circuit using logic gates and subsequently generating a compensating current ripple, ∆𝐼𝐼𝑎𝑎𝑎𝑎 , with zero average value, which cancels out the combined ripple of the primary circuit, ∆𝐼𝐼𝑝𝑝. As a result, a ripple-free output current, 𝐼𝐼𝑜𝑜 (that is, only the DC component) is produced by the output capacitor of the converter. Fig. 6 demonstrates the corresponding control waveforms and the compensating current of a 3-phase ISC.


Fig. 6 Key-waveforms of 3-phase ISC.

Fig. 7 Generic criteria for the proposed control.

The types of logic gates used in the auxiliary phase to produce the compensating current ripple are either XOR or NXOR, which are selected according to the duty cycle. The flowchart in Fig. 7 describes the generic criteria for the proposed control to guarantee ripple-free output current. It

should be noted that, if the duty cycle is at: 𝐷𝐷𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑. ={𝑘𝑘 𝑁𝑁⁄ | 𝑘𝑘 = 1,2, … ,𝑁𝑁 − 1} , then the output current ripple is inherently eliminated by the primary circuit; thereby, the auxiliary phase is no longer required, and hence the auxiliary switches should be turned off. For instance, for 𝑁𝑁 = 2, then 𝐷𝐷𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑. = {𝑘𝑘 2⁄ | 𝑘𝑘 = 1}. Consequently, if the duty cycle is 𝐷𝐷 =1/2, then the switches of the auxiliary phase are turned off. Meanwhile if 0 < D < 1/2, the upper switch, 𝑆𝑆𝑋𝑋𝑋𝑋, should then be driven by a pulse signal generated by the NXOR-ing the pulses driving the switches in the converter's primary circuit. The lower switch, 𝑆𝑆𝑋𝑋𝑋𝑋 , conversely, is always driven by the complementary signal of the upper switch (that is, SXB = XOR of the pulses driving the switches in the converter's primary circuit). In contrast, if 1/2 < D < 1 , then, 𝑆𝑆𝑋𝑋𝑋𝑋 should be controlled by a pulse signal generated by XORing the pulses driving the switches in the converter's primary circuit, whereas 𝑆𝑆𝑋𝑋𝑋𝑋 is driven by its complementary pulse signal.

C. Theoretical Analysis of Ripple-cancelation in Multiphase ISC The cancelation of the current ripple can be evaluated by

simplifying the multiphase stacked converter shown in Fig. 5 using Thevenin's theorem. As shown in Fig. 8, considering continuous conduction mode (CCM) operation, each phase of the primary circuit is epitomized as a voltage source (which is equal to 𝑉𝑉𝑑𝑑𝑖𝑖 or 0, depending on whether the upper switch is closed or open, respectively) and an output inductor. All the inductors are assumed to be equal. Additionally, the parasitic components of the switches, inductors, and capacitors are neglected as they have an insignificant influence on the output current ripple. Moreover, the output voltage ripple is assumed to be much smaller than the DC value; hence, the output capacitor of the primary circuit, 𝐶𝐶𝑜𝑜 , is replaced by an ideal voltage source, 𝑉𝑉𝑜𝑜𝑝𝑝. In contrast, the voltage across the auxiliary capacitor 𝐶𝐶𝑎𝑎𝑎𝑎 is not necessarily constant; thereby, it is indicated by a voltage source 𝑉𝑉𝑜𝑜𝑎𝑎𝑎𝑎 to represent the DC component along with a capacitor connected in series with zero initial voltage to represent the AC component. The circuit can be further simplified by representing the different input voltage sources of the primary circuit with an equivalent voltage source 𝑣𝑣𝑝𝑝_𝑒𝑒𝑒𝑒(𝑡𝑡), which reflects the instantaneous average of all phase voltages [48], [49]. Furthermore, all phase inductances in the primary circuit are of the same value represented by an equal phase inductance, 𝐿𝐿.

Fig. 8 Thevenin equivalent circuit of the multiphase ISC.


As can be observed from Fig. 6, the natural operation of the primary circuit of the multiphase ISC dictates that some phases will be operated at 𝑉𝑉𝑑𝑑𝑖𝑖 or 0 volts during each cycle. Consequently, according to the Thevenin equivalent circuit, the equivalent phase voltage, 𝑉𝑉𝑝𝑝ℎ_𝑒𝑒𝑒𝑒, can be termed as follows [48]:

𝑣𝑣𝑝𝑝ℎ_𝑒𝑒𝑒𝑒(𝑡𝑡) =1𝑁𝑁� 𝑣𝑣𝑝𝑝ℎ𝑑𝑑(𝑡𝑡) =

𝑘𝑘

𝑑𝑑=1

𝑉𝑉𝑑𝑑𝑖𝑖𝑁𝑁⋅ [𝑚𝑚 + 1] (3)

𝑘𝑘 = 0,1, . . . ,𝑁𝑁 − 1

where, 𝑚𝑚 = 𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓 (𝑁𝑁 · 𝐷𝐷); is the maximum integer that cannot exceed 𝑁𝑁 · 𝐷𝐷. The, 𝑣𝑣𝑝𝑝ℎ_𝑒𝑒𝑒𝑒(𝑡𝑡) has an effective period of 𝑇𝑇𝑑𝑑_𝑒𝑒𝑒𝑒𝑒𝑒 , which is equal to 𝑇𝑇𝑑𝑑/𝑁𝑁.

For the following analysis, only a half cycle of the Thevenin equivalent voltage at the turn-on time (𝑡𝑡𝑜𝑜𝑖𝑖_𝑒𝑒𝑒𝑒𝑒𝑒) is considered, as shown in Fig.6. The effective duty cycle, 𝐷𝐷𝑜𝑜𝑖𝑖_𝑒𝑒𝑒𝑒𝑒𝑒 during this time interval is given as [48]:

𝐷𝐷𝑜𝑜𝑖𝑖_𝑒𝑒𝑒𝑒𝑒𝑒 =𝑡𝑡𝑜𝑜𝑖𝑖_𝑒𝑒𝑒𝑒𝑒𝑒

𝑇𝑇𝑑𝑑_𝑒𝑒𝑒𝑒𝑒𝑒=𝑡𝑡𝑜𝑜𝑖𝑖_𝑒𝑒𝑒𝑒𝑒𝑒𝑇𝑇𝑑𝑑

𝑁𝑁�= (𝑁𝑁 ⋅ 𝐷𝐷 − 𝑚𝑚) (4)

Applying Kirchhoff's law to the equivalent circuit of Fig. 8, during the 𝑡𝑡𝑜𝑜𝑖𝑖_𝑒𝑒𝑒𝑒𝑒𝑒 time-interval, equations (5) and (6) can then be derived as follows:

𝑉𝑉𝑝𝑝ℎ_𝑒𝑒𝑒𝑒 − 𝐿𝐿𝑑𝑑𝑖𝑖𝑝𝑝(𝑡𝑡)𝑑𝑑(𝑡𝑡)

− 𝑉𝑉𝑜𝑜𝑝𝑝 = 0 (5)

𝑉𝑉𝑎𝑎𝑎𝑎 − 𝐿𝐿𝑎𝑎𝑎𝑎𝑑𝑑𝑖𝑖𝑎𝑎𝑎𝑎(𝑡𝑡)𝑑𝑑(𝑡𝑡)

− 𝑉𝑉𝑜𝑜𝑎𝑎𝑎𝑎 − 𝑉𝑉𝑜𝑜𝑝𝑝 = 0 (6)

As shown in Fig.6, the current waveform of each phase is a

ramp and therefore, the terms 𝑑𝑑𝑑𝑑𝑝𝑝(𝑑𝑑)𝑑𝑑(𝑑𝑑)

and 𝑑𝑑𝑑𝑑𝑎𝑎𝑎𝑎(𝑑𝑑)𝑑𝑑(𝑑𝑑)

can be

rewritten as 𝛥𝛥𝐼𝐼𝑝𝑝

𝛥𝛥𝑇𝑇𝑠𝑠_𝑒𝑒𝑓𝑓𝑓𝑓 and 𝛥𝛥𝐼𝐼𝑎𝑎𝑎𝑎

𝛥𝛥𝑇𝑇𝑠𝑠_𝑒𝑒𝑓𝑓𝑓𝑓, respectively, where:

• 𝛥𝛥𝐼𝐼𝑝𝑝 and 𝛥𝛥𝐼𝐼𝑎𝑎𝑎𝑎 are the amplitudes of the output currents ripples of the primary and auxiliary circuits, respectively.

• 𝛥𝛥𝑇𝑇𝑑𝑑_𝑒𝑒𝑒𝑒𝑒𝑒= 𝐷𝐷𝑜𝑜𝑖𝑖_𝑒𝑒𝑒𝑒𝑒𝑒 ∙ 𝑇𝑇𝑑𝑑_𝑒𝑒𝑒𝑒𝑒𝑒 = 𝐷𝐷𝑜𝑜𝑖𝑖_𝑒𝑒𝑒𝑒𝑒𝑒 ∙𝑇𝑇𝑑𝑑

𝑁𝑁�

Equations (5) and (6) can then be re-written as follows:

𝛥𝛥𝐼𝐼𝑝𝑝 = �𝑉𝑉𝑝𝑝ℎ_𝑒𝑒𝑒𝑒 − 𝑉𝑉𝑜𝑜𝑝𝑝� ∙𝐷𝐷𝑜𝑜𝑖𝑖_𝑒𝑒𝑒𝑒𝑒𝑒

𝐿𝐿· 𝑇𝑇𝑑𝑑_𝑒𝑒𝑒𝑒𝑒𝑒 (7)

𝛥𝛥𝐼𝐼𝑎𝑎𝑎𝑎 = �𝑉𝑉𝑎𝑎𝑎𝑎 − 𝑉𝑉𝑜𝑜𝑎𝑎𝑎𝑎 − 𝑉𝑉𝑜𝑜𝑝𝑝� ∙𝐷𝐷𝑜𝑜𝑖𝑖_𝑒𝑒𝑒𝑒𝑒𝑒

𝐿𝐿𝑎𝑎𝑎𝑎· 𝑇𝑇𝑑𝑑_𝑒𝑒𝑒𝑒𝑒𝑒 (8)

During the considered time-interval �𝑡𝑡𝑜𝑜𝑖𝑖_𝑒𝑒𝑒𝑒𝑒𝑒 = 𝐷𝐷𝑜𝑜𝑖𝑖_𝑒𝑒𝑒𝑒𝑒𝑒 ·𝑇𝑇𝑑𝑑_𝑒𝑒𝑒𝑒𝑒𝑒� only, the voltage sources are as follows:

𝑉𝑉𝑝𝑝ℎ_𝑒𝑒𝑒𝑒 = 𝑉𝑉𝑑𝑑𝑖𝑖 (9)

𝑉𝑉𝑎𝑎𝑎𝑎 = 0 (10)

𝑉𝑉𝑜𝑜𝑝𝑝 = 𝑉𝑉𝑑𝑑𝑖𝑖 ⋅ 𝐷𝐷𝑜𝑜𝑖𝑖_𝑒𝑒𝑒𝑒𝑒𝑒 (11)

𝑉𝑉𝑜𝑜𝑎𝑎𝑎𝑎 + 𝑉𝑉𝑜𝑜𝑝𝑝 = 𝑉𝑉𝑑𝑑𝑖𝑖 ⋅ �1 − 𝐷𝐷𝑜𝑜𝑖𝑖_𝑒𝑒𝑒𝑒𝑒𝑒� (12)

where, 𝑉𝑉𝑜𝑜𝑝𝑝 is the primary circuit's output voltage and 𝑉𝑉𝑜𝑜𝑎𝑎𝑎𝑎 + 𝑉𝑉𝑜𝑜𝑝𝑝 is the auxiliary circuit's output voltage. Substituting (9-12) into (7) and (8), defines the primary and the auxiliary current ripples as:

𝛥𝛥𝐼𝐼𝑝𝑝 =�𝑉𝑉𝑑𝑑𝑖𝑖 ⋅ �1 − 𝐷𝐷𝑜𝑜𝑖𝑖_𝑒𝑒𝑒𝑒𝑒𝑒�� × 𝐷𝐷𝑜𝑜𝑖𝑖_𝑒𝑒𝑒𝑒𝑒𝑒

𝐿𝐿 ⋅ 𝑓𝑓𝑑𝑑 ⋅ 𝑁𝑁 (13)

𝛥𝛥𝐼𝐼𝑎𝑎𝑎𝑎 =�−𝑉𝑉𝑑𝑑𝑖𝑖 ⋅ �1 − 𝐷𝐷𝑜𝑜𝑖𝑖_𝑒𝑒𝑒𝑒𝑒𝑒�� × 𝐷𝐷𝑜𝑜𝑖𝑖_𝑒𝑒𝑒𝑒𝑒𝑒

𝐿𝐿𝑎𝑎𝑎𝑎 ⋅ 𝑓𝑓𝑑𝑑 ⋅ 𝑁𝑁 (14)

The output current ripple of the auxiliary circuit 𝛥𝛥𝐼𝐼𝑎𝑎𝑎𝑎 has an identical amplitude to that of the total output current ripple of the primary circuit 𝛥𝛥𝐼𝐼𝑝𝑝 , but with the opposite polarity. As a result, a ripple-free output current, 𝐼𝐼𝑜𝑜 with only the DC part is always guaranteed at the output capacitor of the converter.

IV. ILLUSTRATIVE SIMULATION RESULTS Extensive simulation studies were conducted using

MATLAB Simulink software to demonstrate the effectiveness of the proposed multiphase ISC in terms of ripple cancellation compared to the equivalent conventional interleaved converters. Illustrative operating scenarios were considered with the specifications listed in Table I.

Table I Key parameters of the ISC.

Parameters Value

Input voltage, Vin 30 V

Output voltage range, Vo 8 - 24 V

Maximum output power, Pmax 1 kW

Phase switching frequency, fs 40 kHz

Phase inductance, L 23 µH

Auxiliary capacitor, Cax 10 µF

Fig. 9 Simulation results of 2-phase IBC and ISC:

a) D=65% conventional, b) D=65% proposed c) D=35% conventional, d) D=35% proposed


Fig. 10 Simulation results of 3-phase IBC and ISC:


Referring to Fig. 2, a conventional two-phase IBC can only achieve complete ripple cancellation at a 50% duty cycle. Hence, two distinct duty cycles values are selected such that a ripple is produced using the conventional control method. Fig. 9(a) shows the waveforms of the inductor currents and the resulting output current of the conventional two-phase IBC for an output voltage 𝑉𝑉𝑜𝑜 = 19.5𝑉𝑉 (that is, 𝐷𝐷 = 0.65). The peak-to-peak phase inductor current ripple of each phase is approximately 7.4A, while the ripple of the output current is around 3.5A with an efficiency of 96.18%. In contrast, Fig. 9(b) shows the simulation results of the proposed control technique for the same duty cycle and the same number of phases. It can be observed that the auxiliary phase carries a current ripple, which is produced by the proposed logic gate circuit, that is equal in amplitude but in the opposite direction to the resulting output ripple of the primary circuit; consequently, a ripple-free output current is obtained at the output with an efficiency of 96.11%. Due to the utilization of the capacitor in the auxiliary phase, Cax, the average current in the auxiliary phase is zero.

The second set of waveforms shown in Fig. 9(c) and (d) illustrate the operation of the converter at 𝐷𝐷 = 35%. The output current ripple is eliminated using the proposed control technique with an efficiency of 95.65%, while almost 3.5A of the output current ripple is observed in the conventional IBC with an efficiency of 95.95%.

In the same manner, Fig. 10 shows a comparison of the simulation results for a conventional 3-phase IBC and a stacked 3-phase IBC under two different values of duty cycle. It can be observed that, unlike in the conventional IBC, the proposed multiphase ISC eliminates the duty-cycle dependency, and a free-ripple output current is always guaranteed.

As a result of switching and conduction losses caused by power dissipation in the auxiliary phase of the proposed ISC, there is a slight decrease in overall system efficiency when

compared to IBC. However, these losses are negligible as only ripple current is conducted in the auxiliary phase.

It is worth mentioning that the simulation study presented in this paper is for only two scenarios, namely 2-phase and 3-phase converters, in order to match the following experimental validation in Section V. However, the method was proven to work perfectly for any number of phases.

Fig. 11 Experimental setup.

V. EXPERIMENTAL RESULTS In order to verify the theoretical and simulation analysis, a

laboratory prototype is developed, as portrayed in Fig. 11. An electronic DC load is used to emulate different operating scenarios. The control algorithms and associated gating signals are all implemented using the Texas Instruments TMS320F28379D microcontroller unit (MCU) board. Currents and voltages are sensed using LA 55-P and LV 25-P transducers to facilitate the closed-loop control system. A. Generation of Customized Gating Signals Using CLB tool:

Usually, a system’s customized logic is implemented using external hardware circuitry such as Field-Programmable Gate Arrays (FPGAs), Complex Programmable Logic Devices (CPLDs), or external logic circuits paired with an MCU. Nevertheless, in this paper, the customized pulses required to drive the auxiliary switches of the proposed multiphase stacked converter are generated using the Texas Instruments Configurable Logic Block (CLB) tool, eliminating the requirement for additional logic circuits. The CLB is a powerful state-of-the-art tool built into most of the widely used C2000 real-time microcontrollers (MCUs). As the CLB is integrated into the C2000 peripheral and has access to a lot of important signals that exist inside the MCU, it allows the integration of critical and customized functions without requiring signals to be transferred from the MCU to any other external logic circuits, thereby reducing the system’s overall size and cost. Moreover, unlike external logic circuits, the CLB is a self-configurable and rapid software tool that can be modified easily, improving the overall system’s reliability since no hardware electronics are used. Additionally, the CLB can minimize feedback latency by eliminating pin delays that may arise when external components are interfaced, resulting in an increase in control loop time [50].

All the signals used to drive the upper switches of the multiphase ISC, including the upper auxiliary switch signal, are presented in Fig. 12. The gate driving signals of the lower switches are complementary to those used to drive the upper switches.


Fig. 12 Control waveforms of a 3-phase ISC.

B. Analysis of the Experimental Results: The same operating conditions with the same number of

phases and duty cycles discussed in the simulation results are experimentally validated. Interestingly, the experimental waveforms are in good agreement with the simulation results. Fig. 13 presents two operating conditions when N = 2, where it can be clearly seen that the output voltage (purple color) and output current (green color) ripples are eliminated using the proposed control method. The compensating current produced by the auxiliary phase, on the other hand, is illustrated in Fig. 14 for each of the duty cycle scenarios. It is in the opposite direction but has the same amplitude as the output current ripple; consequently, a near to zero current is produced at the load side.

Fig. 13 Experimental results waveforms for 2-phase IBC and ISC:


Fig. 14 Compensating current of the auxiliary phase (in purple) when N=2:

a) D=65%, b) D=35%

Similarly, the results for the second case, when N = 3 are depicted in Fig. 15 and Fig. 16, where it can be observed in Fig. 15 that the proposed technique produces near to zero output ripple. However, due to the limited number of channels in the oscilloscope used in the experiment (four channels), only the output current ripple is demonstrated when N=3. It is worth mentioning that while output ripples should theoretically be zero, this is constrained in the experiment by imperfections in the power-stage, component mismatches as well as the resolution of the measurement devices.

Fig. 15 Experimental results waveforms for 3-phase IBC and ISC:



Fig. 16 Compensating current of the auxiliary phase (in green) when N=3:

a) D=50%, b) D=70%

Fig. 17 shows the dynamic response of a 2-phase conventional multiphase IBC and the proposed multiphase ISC for a step-change in load current from 17A to 11 A. It appears that a significant reduction can still be attained with the multiphase ISC during a load step, confirming the dynamic performance of the proposed ripple-cancellation control technique. Additionally, it is worth noting that the converter's inductor currents are equally shared before and after the load transient, and the converter reaches nominal conditions in the shortest possible time and with minimal variation in the output voltage, confirming the effectiveness of the implemented closed current control loop.

Fig. 17 Experimental results load step from 17A to 11A: a) Conventional 2-phase IBC, b) Proposed 2-phase ISC

VI. CONCLUSION

A novel control technique was presented in this paper, which aimed at suppressing the output ripple of a multiphase ISC. A significant reduction in the output ripples was attained by adding fractionally-rated components to the conventional multiphase interleaved converters. Furthermore, unlike the conventional interleaved converters, ripple-free was accomplished for the wide range of output voltage, regardless of the duty cycle and the number of phases. In addition, the customized PWM signals of the auxiliary switches can either be produced using small external logic circuits or hardware-less by utilizing the powerful CLB tool, offering a further reduction in the cost and size of the system. The effectiveness of the proposed system was demonstrated by simulation and

experimentally verified results, where both sets of results are in good agreement.

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ripple-free multiphase interleaved stacked converter for high

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