Modeling and Control Design of the Six-Phase Interleaved Double Dual Boost Converter

F. S. Garcia*; J. A. Pomilio*; G. Spiazzi**

*University of Campinas; **University of Padova fsgarcia@gmail.com; antenor@dsce.fee.unicamp.br; spiazzi@dei.unipd.it

Abstract-This paper presents the small-signal modeling and the control design of the six-phase Interleaved Double Dual Boost, which is a non-insulated, step-up DC-DC converter that can be operated with high voltage gain and can be scaled to high-power applications. The applications of this converter include electrical vehicles and renewable energy conversion. Experimental results obtained with a prototype operating with input voltage of 60V and output voltage of 360V and with nominal output power of 2.2kW are presented.

INTRODUCTION

The growing use of renewable energy sources brings new challenges to the energy conversion technology. One of these challenges is related to the fact that some devices that store or produce electrical energy (e.g. batteries, ultracapacitors, fuel cells, and solar panels) are built using low voltage cells, usually connected in series in order to attain a reasonable voltage. The connection of a large number of cells in series increases the complexity of the system and may reduce its performance, because of the differences among cells (e.g. fabrication variations) and the different working conditions (e.g. temperature). In addition, those sources of electrical energy have a significant variation in the output voltage depending on several factors as, for example, state of charge and solar radiation.

In typical applications, such as driving electrical motors and connection with the grid, it is usually necessary or convenient to use a relatively high and stable voltage. When this is the case, a step-up converter can be used to boost the source’s voltage to the level required by the application and to produce a stable output voltage despite variations on the source’s voltage.

As an example of application, consider the power electronics in the Toyota Prius, described in [1]. According to this reference, the nominal battery voltage is 206.1 V and the inverter dc-link has a maximum voltage of 500 V. In order to step-up the battery voltage, Toyota used a classical boost converter.

This paper explores a topology proposed with the objective of creating a higher voltage gain in comparison with the classical boost converter, the Interleaved Double Dual Boost [2][3][4].

This topology was chosen among others that also have high gain properties [5][6] because of the possibility of phase interleaving that allows the converter to be scaled to high-power applications. Another interesting property is that the components of the converter can be sized to a voltage lower than the output voltage.

ANALYSIS OF THE CONVERTER

The six-phase Interleaved Double Dual Boost is shown in Fig. 1, where is the input voltage and the resistor represents the load. The resistors , … , represent the resistance of the inductor and of the switches. This version of the converter where every switch is implemented with a transistor and a diode allows bidirectional power flow.

Each of the six phases of the converter is composed by one inductor and its corresponding pair of switches. The phase 1 is comprised by the inductor and switches , and , . By analogy, the phases 2 to 6 as can be understood by the connection presented in Fig. 1.

Fig. 1: Six-phase Interleaved Double Dual Boost

Phases 1, 2 and 3 are connected to the capacitor and this combination is here called “module 1”. Phases 4, 5 and 6 are connected to the capacitor and this combination is here called “module 2”.

The output voltage (i.e. the voltage at the load ) is given by

(1)

The input current in the converter (i.e. the current at the source ) is given by

(2)

Where ⁄ is the output current of the converter. Using (1), neglecting all the losses in the converter, and

supposing that the duty cycle is the same for every phase, it can be shown that the static gain of the converter is expressed by

11 (3)

SMALL-SIGNAL MODELING

The six-phase interleaved double dual boost with ideal switches is shown in Fig. 2.

It is here defined that the duty cycle of the switch is referred to the position that connects the inductor in parallel with the source ( ). Notice that this definition implies that the duty cycle is related to the conduction of lower transistor for the switches , , and to the conduction of the upper transistor for the switches , , .

Fig. 2: Inverse Dual Double Boost with ideal switches

The state space model of the converter can be written as

(4)

Henceforth, capital letters will be used to represent the average values of the state variables.

The state vector is defined as

(5)

And the input is defined as

(6)

Using the state-space averaging method [7] [8] and using the notation 1 , the average system matrix is given by

0 0 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0

(7)

While the input matrix is given by:

(8)

Now, consider that the components of the converter are equal, that is

(9)

(10)

(11)

In addition to the symmetry of both modules, the same voltage reference is going to be used for the voltage of both capacitors (see next section), resulting in

(12)

The system can now be written as two independent systems of order four, one for each module, the first of them having the following state vector

(13)

The system matrix is then given by

0 00 00 0 (14)

Supposing that the current is the same in the phases of the module 1,

(15)

And that the duty cycle is the same in the phases of the module 1

(16)

It is also assumed that the similar expressions of (15) and (16) hold for module 2.

Then the system can be reduced for a per-phase, per-module model of order two, with the following state vector

(17)

And the following system matrix

(18)

This reduced order system represents a dynamic model for the current on one phase and the voltage on one module of the converter, with the supposition that the other module and phases are behaving symmetrically. The variable represents the duty cycle of the phase that is being modeled.

The set of attainable equilibrium points is

(19)

Using and (6), (23), (24) and (19), the set of equilibrium points can be written as

(20)

From (1) and (20), a relation between the output voltage and the input voltage, which takes into account the resistive losses and therefore is more precise than relation (3), can be derived

3 12 3 1 (21)

The converter’s parameters are presented in table I. TABLE I

CONVERTER’S NOMINAL PARAMETERS

60 V 0.15Ω 535μH 470μF 59Ω Based on equations (20) and the parameters of Table I, the

set of attainable equilibrium points of the converter is shown in Fig. 3.

Fig. 3: Equilibrium points of the module voltage and current per phase as a function of

In practice, high values of duty cycle are undesirable because of high current and low efficiency and therefore the duty cycle was limited to 0.85.

In order to compute the small signal model of the converter, a nominal equilibrium point that belongs to the set defined by (20) is selected. This point is shown in Table II and indicated in Fig. 4.

TABLE II NOMINAL EQUILIBRIUM POINT

0.73 7.86 A 217.9 V

Fig. 4: Equilibrium points the module voltage and current per phase as a function of , for 0 0.85

Using the state-space averaging method [8], the equivalent linear system near the equilibrium point is given by:

(22)

Where

0

0 (23)

And

1 1

(24)

Expression (22) can be simplified to

(25)

And the transfer functions of the linearized system around the operating point are given by

(26)

This expression can be developed into

ΔΔ

2 3 12 2 3 13 3 3 12 2 3 1

(27)

From (27) the transfer function relating the voltage to the current can be derived,

Δ Δ 3 3 3 12 3 1 (28)

DESIGN OF CONTROL LOOPS

Using the transfer functions of the current to duty cycle, presented in (27) and of the voltage to current, presented in (28), the control loops can be designed, using current mode control [9].

The duty cycle value is determined by the current controller (internal loop). The average current reference is generated by the voltage controller.

The control diagram of the control of the voltage in one module and the current in one phase is shown in Fig. 5.

Fig. 5: Per-module, per-phase model

First, the current controller is designed using the current to duty cycle transfer function of (27), whose Bode diagram is shown in Fig. 6.

Fig. 6: Bode diagram of current to duty cycle transfer function around the nominal equilibrium point.

The controller that was used as the current controller and the voltage controller is a proportional integral controller with a low pass filter, with the transfer function given by

(29)

Where is the proportional gain, is the integral gain, is the pole angular frequency and ⁄ is the zero

angular frequency. In order to calculate the parameters of the current

controller, the closed loop cut-off frequency and the phase margin are selected, as shown in Table III.

TABLE III CURRENT CONTROLLER SPECIFICATIONS

Cut-off frequency Phase margin 2 1 ⁄ 80°

The current controller is then designed according to the factor method [10] and the resulting transfer function is

10,02 663,7663,7 5947959479 (30)

After designing the current controller, the voltage controller is designed, using the voltage to current transfer function (28), whose Bode diagram is shown in Fig. 7.

Fig. 7: Bode diagram of voltage to current transfer function around the nominal equilibrium point.

The cut-off frequency of the voltage control loop must be much smaller than the cut-off frequency of the current control loop, in order to consider the latter as having unitary gain and zero phase when designing the former.

The closed loop cut-off frequency and the phase margin of the voltage control loop are shown in Table IV.

TABLE IV VOLTAGE CONTROLLER SPECIFICATIONS

Cut-off frequency Phase margin 2 100⁄ 80° The resulting voltage controller is

40,9 107,7107,7 36673667 (31)

The control loops were implemented digitally, based on digital current mode control [9]. The average current of each phase is measured by sampling the signal from the current sensor synchronized with the center of the PWM pulse.

In order to assure the conditions of equal average voltage in the capacitors (12) and of equal average currents in the phases of the same module (15), the same voltage reference is used for both capacitors and the same current reference is uses for the three phases of the same module as shown in the diagram of Fig. 8. Six current controllers (one for each phase) and two voltage controllers (one for each module) were implemented. The PWM blocks represent the PWM generators of the microcontroller.

Fig. 8: Control diagram of the implemented controllers

EXPERIMENTAL RESULTS

The six-phase Interleaved Double Dual Boost that was experimentally tested is shown in Fig. 9.

Fig. 9: Experimental set-up

The microcontroller is enclosed in the metallic box (A), for reduction of electromagnetic interference. The signals of the current and voltage sensors are received by the signal conditioning board (B) and transmitted to the microcontroller. The board (C) is an auxiliary power supply for the signal conditioning board. The microcontroller is programmed via the emulator BlackHawk USB2000 (D).

All the power circuits of the converter (power semiconductors, inductors, capacitors, and sensors) are located in the boards shown in position (E).

The control routines were implemented in a microcontroller model TMS320F28335, by Texas Instruments. This microcontroller was chosen because of its natural support for the generation of the six pairs of PWM signals with the proper phase and also because of its sufficient capacity for

processing the controllers and auxiliary routines (protection, soft-start etc).

The power switches were implemented using two parts of the integrated circuit IRAM20UP60A, manufactured by International Rectifier. Each of this integrated circuit contains six IGBTs with anti-parallel diodes, in a typical three phase inverter bridge configuration, along with driving circuits and a thermistor for thermal protection.

The switching frequency of each phase of the converter was set at 11,1 ( 90 ). The nominal operating point of the converter is 60 , 360 , 2200 , 58.82Ω. At this point, the efficiency of the converter was measured as 92.8%.

The waveforms were acquired using a Tektronix DPO 7054 Oscilloscope and plotted with Mathworks MATLAB.

The currents in the six phases are shown in Fig. 10. Because of the controller action, the current of every phase have approximately the same average value. The small variation in the peak-to-peak value and in the slope of the phases currents are mainly due to differences in the inductors.

Fig. 10: Experimental waveforms of the currents in the six phases

The ripple is significantly reduced in the input current of each module because of the proper phase displacement (of 60°), as shown in Fig. 11.

Fig. 11: Currents of the module 1

The same effect of ripple cancelation can be noticed in the voltages of each module, which are summed in expression (1) to produce the output voltage, as shown in Fig. 12.

Fig. 12: Voltages measured in the converter

A positive step load change was applied to the converter, with the load changing from 1013 to 2023 and the result is shown in Fig. 13

Fig. 13: Load changes from 1013 W to 2023 W

The opposite step load change, with the load changing from 2023 to 1013 is shown in Fig. 14.

Fig. 14: Load changes from 2023 W to 1013 W

For the load turn on, the voltage variation (undervoltage) was of approximately 4% and the settling time (95%) was of approximately 20 , while for the load turn-off the voltage variation (overvoltage) was of approximately 8.5% and the settling time (95%) was of approximately 25 .

CONCLUSIONS

This paper described the derivation of the small signal model of the six-phase Interleaved Double Dual Boost, which was used in the design of the controllers. The similarity of the components and the symmetry of the operation of the converter were explored in order to reduce the complexity of the model. Experimental results were provided to justify the theoretical analysis.

ACKNOWLEDGEMENTS

The authors thanks for Simone Buso for contributing to the digital implementation of the controllers and Edson Vendrusculo and José Claudio Geromel for useful suggestions.

The authors acknowledge the FAPESP financial contribution to this research and Texas Instruments for the donation of the microcontrollers that were used in this project.

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