lecture 3 verilog-behavioral level
TRANSCRIPT
Lecture 3
Verilog-Behavioral Level
Behavioral Level
• Highest level in the Verilog HDL
• Design specified in terms of algorithm
(functionality) without hardware details. Similar
to “c” type specification
• Most common level of description
• There are two structured procedure statements
in Verilog – Initial statement
– Always statement
Combinational Circuit
• Combinational logic circuits are memoryless
• No feedback in combinational logic circuits
Sequential Circuit
• Sequential circuits have memory (i.e., remember the
past)
• The current state is “held” in memory and the next
state is computed based the current state and the
current inputs
• In a synchronous systems, the clock signal
orchestrates the sequence of events
• Register – Represent abstract storage elements
– A register holds its value until a new value is assigned to it
– Types of reg • reg
reg1
reg2
reg3
Data type - register
Port Connection Rules
input output net/register net/register net net
module
Initial Statement
• Starts at time 0
• Executes exactly once
• Typically used for initialization, monitoring,
waveforms
• Multiple initial blocks start to execute
concurrently at time 0
• Multiple behavioral statements must be
grouped, typically using the keywords begin
and end
Always Statement
• Starts at time 0
• Executes the statements in the always block
continuously in a looping fashion
• Used to model a block of activity that is
repeated continuously in a digital circuit
• Multiple behavioral statements must be
grouped, typically using the keywords begin
and end
Always Statement
• Syntax
always @(event-expression)
begin
statements
end
• Level type
– always @(a or b or c)
– always @(clk)
• Edge type
– always @(posedge clock)
– always @(negedge clock)
Example for always
module example (a, b, x, y, z);
input x, y, z;
output a, b;
reg a, b;
always @(x or y or z)
begin
a <= x & y;
b <= x | z;
end
endmodule
Always Block
Conditional Statements
if … else…
if (condition 1)
begin
..................
end
else if (condition 2)
begin
..................
end
else
begin
..................
end
if (opcode == 2’b00)
out = a + b;
else if(opcode == 2’b01)
out = a - b;
else if(opcode == 2’b10)
begin
out = a * b;
end
else
out = a ^ b;
Conditional Statements
case
case (state)
2’b00 : .........
2’b01 : .........
2’b10 : .........
2’b11 : .........
default : .........
endcase
case (opcode)
2’b00 : out = a + b;
2’b01 : out = a – b;
2’b10 : out = a * b;
2’b11 : out = a ^ b
default :
endcase
Shift Register
• a shift register is a cascade of flip flops with the same
clock.
• Shift registers can have both parallel and serial inputs
and outputs.
• Serial-in, parallel-out (SIPO)
• Parallel-in, serial-out (PISO)
Serial-in, parallel-out
• Convert data from serial format on a single wire to
parallel format on multiple wires.
• Each flip-flop is edge triggered.
Parallel-in, serial-out
• Convert data from multiple format on multiples wire to
serial format on a single wire.
• Each flip-flop is edge triggered.
Blocking vs. Nonblocking
a = in;
b = a;
c = b;
//in=a=b=c
in a b c
a <= in;
b <= a;
c <= b;
a
b
c
in
Blocking :
Nonblocking :