An Input Stage for the Implementation of Low-Voltage Rail to Rail Offset Compensated CMOS Comparators

Jaime Ramirez-Angulo, Lalitha Mohana Kalyani-Garimella, Annajirao Garimella, Sri Raga Sudha Garimella, Antonio Lopez-Martin and Ramon Gonzalez Carvajal

New Mexico State University, Las Cruces, NM 88003 USA jramirez@nmsu.edu, lalitha.garimella@intel.com, garimella@ieee.org, sudha@nmsu.edu,

antonio.lopez@unavarra.es, carvajal@gte.esi.us.es

Abstract

A rail-to-rail differential input stage with

programmable threshold levels and offset compensation is introduced. Applications for the implementation of differential and double differential comparators are discussed. Experimental results obtained from a MOSIS 0.5µm CMOS technology test chip are shown that validate rail-to-rail operation with a 1.5V supply voltage. 1. Introduction

The comparator is the basic analog to digital interface element [1]-[2]. It generates digital output signals as a result of the comparison of two analog voltages Vin and Vref respectively. It generates a high output voltage (close to VDD) if Vin > Vref + ∆V–Vos and a low output voltage (close to ground or VSS) for Vin < Vref–∆V+Vos, where Vos is the offset voltage, ∆V =VDD/A is the minimum overdrive voltage or comparator resolution (if offset compensation is used) and A is the gain of the comparator. Technological and power dissipation constraints require modern deep submicron VLSI circuits to operate with continuously decreasing supply voltages VDD, which will take sub-volt (<1V) values within the next few years. Many applications require comparators where both Vin and Vref can take rail-to-rail (R2R) values. A typical example is in flash A/D converters that require a large number of very compact R2R comparators with low power consumption. Double differential R2R comparators with two signal inputs (VinP and VinN) and two reference inputs (VrefP and VrefN) are also commonly required in two-step A/D flash converters. These generate a high output voltage if VinP–VrefP > VinN–VrefN+ ∆V–Vos and a low output voltage otherwise.

2. Traditional approaches to implement rail to rail comparators 2.1. Switched capacitor approach

R2R comparators have been implemented using switched capacitor (SC) techniques by means of what some authors denote “common mode jump circuits” (Fig. 1a) [3]. These use an input differential stage with two capacitors C that have one of their terminal connected to the gate of the differential pair (DP). During a pre-charge phase (ф1) the gate terminal of each capacitor is connected to a common mode biasing voltage VCMbias (with a value close to the upper rail for NMOS DPs) while the other capacitor’s terminal is connected to a common mode input voltage VCMinp. This causes both capacitors to charge to a voltage Vbat=VCMinp–VCMbias. During the evaluation phase (ф2) both capacitors are first disconnected from VCMbias (on the gate terminal) which leaves the gate terminals floating. The other terminal of each capacitor is then connected to Vin and Vref respectively. Given that the capacitors retain their charge (and voltage), they act as floating batteries with value Vbat and transfer to the gate terminal changes on the other (control) terminal. During ф1 the gate terminals have voltages Vg1=Vg2=VCMbias. During ф2 they take values Vg1=VCMbias+Vin–VCMinp and Vg2=VCMbias+Vref–VCMinp. During ф2 their difference takes a value Vd=Vin-Vref. Selection of values VCMbias=VDD and midsupply VCMinp=VDD/2 leads to gate voltages Vg1,Vg2>VDD/2 for Vin and Vref taking R2R values when VDD/2 > VGS + VDSsat. The DP transistors remain ON with R2R voltages Vin, Vref. This technique allows R2R operation if VDD>2(VGS+VDSsat). A disadvantage of this approach besides the inherent speed limitation of discrete time operation is that for Vin,Vref=VDD the gate voltages can take during ф2 values higher than the supply rail

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VinNVinP

VrefN VrefPC C

1φ

1φ1φ

2φ2φ1φ

Vin Vref

VCMinp VCMinpVg1

( a )

Vg2C C

1φ

1φ1φ

2φ2φ1φ

VCMbias

Vin

Vref Vref

A B

CurrentMirror

Ib

A

A

B

B

VCMbias

VCMbias VCMbias

Vg2Vg1

Ib

Ib

( b )

A

CurrentMirror

B

Ib

( c ) Figure 1. Traditional R2R comparator input stages: (a) Switched capacitor single ended input stage (b) SC double differential input

stage (c) Complementary input stage. Vg1

MAX= Vg2MAX =3VDD/2 . This can lead to reliability

problems (like oxide breakdown) in deep submicron technologies. 2.2. Complementary differential pairs approach

Another common approach to implement R2R input stages makes use of a complementary differential pair (CDP) input stage consisting of a PMOS and an NMOS DP (Fig. 1c) [4]-[5]. This requires a current folding circuit to add the currents from the two DPs and a bias control circuit (see Fig. 1c). This technique has been used to implement R2R op-amps [6]. Complementary input stages have following disadvantages: 1) they are relatively complex and have increased power consumption, noise and offset. 2) they can also be subject to severe CMRR and PSRR degradation over some regions of the input range where the tail biasing transistors operate in triode mode. Both approaches described above require a relatively large minimum supply voltage VDD=2(VGS+VDSsat). Some authors have

combined the two techniques discussed above in order to achieve R2R low-voltage operation.

2.3. Contributions of the present work

In this paper, application of a simple R2R differential input stage to implement comparators that operate in continuous time with a single supply voltage that can be as low as VDD=VGS+VDSsat is discussed. It is based on the floating gate (FG) technique reported in [7],[8]. Offset compensation and implementation of double and multiple differential comparators is also discussed. The rest of the paper is organized as follows. The proposed R2R input stage is described in Section 3. The architecture and stability of the comparator are discussed in Section 4. Simulation and experimental results are disclosed in Section 5 with conclusions in Section 6.

3. Proposed rail to rail input stage The proposed R2R input stage is shown in Fig. 2a. As mentioned before, it operates in continuous time and is based on the low- voltage FG basing technique reported in [7],[8]. 3.1. Analysis of rail to rail operation

By using charge conservation and assuming zero charge on the floating gates of M1 and M2 (a condition easily achieved by utilization of the layout technique reported in [9]) it can be shown that the FG voltages are given by

Vfg1=Vbias(Cbias/Ctotal)+Vin(C/Ctotal) (1) Vfg2=Vbias(Cbias/Ctotal)+Vref(C/Ctotal) (2)

where Ctotal=C+Cbias. By selection of Cbias=C=Ctotal/2 and Vbias=VDD the

FG voltages Vfg1, Vfg2 take values ranging from VDD/2 to VDD for Vin and Vref taking R2R voltages (from 0V to VDD). The differential input voltage of the differential pair is given by Vd = Vfg1–Vfg2= k(Vin-Vref). The effective gain of the input stage is reduced by the attenuation factor k=(C/Ctotal)=0.5. This selection for Cbias and Vbias allows operation with a minimum supply voltage VDD

MIN=2(VGS+VDSsat) but in this case the gate voltages do not go over the supply rail and unlike in the CDP approach both the DP transistors and the tail biasing source remain ON in saturation mode over the complete R2R common mode input range. For this reason no CMRR or PSRR degradation takes place and no additional power dissipation or complex circuitry is required as in the CDP technique. Selection of a value Cbias>>C leads to voltages Vfg1 and Vfg2 that remain close to VDD with R2R signals Vin and Vref. In this case it is possible to operate the circuit of Fig. 2a with a

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Ib

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C

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Vi n

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V

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C/2

C/4

C/2n

b1

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Vfine

VinP

VrefP

Vfg1

M2M1

M2

VinN

M1b2

bn

M2

( a )

( b )

( c )

Ib

bias bias

biasbias

bias bias

biasbias

bias bias

biasbias

Figure 2. FG approach for R2R operation. (a) Differential input stage (b) Double differential

input stage (c) Differential input stage with R2R programmable reference voltage.

single supply voltage VDDMIN≈VGS+VDSsat. The tradeoff

is a larger attenuation factor k=C/Ctotal that leads to a smaller effective comparator gain and increased effective input offset and noise (by the factor 1/k). 3.2. Implementation of double and multiple differential pairs

Fig. 1b shows the implementation of a double differential input using the SC approach and Fig. 2b using FG biasing technique. In Fig. 2b two capacitors with value C are connected to the FG of each DP transistor. The control terminal of the two capacitors on the side of M1 is connected to voltages VinP, VrefN and on the side of M2 to VinN, VrefP respectively. In this case FG voltages are given by

Vfg1=Vbias(Cbias/Ctotal) + VinP(C/Ctotal) + VrefN(C/Ctotal) Vfg2=Vbias(Cbias/Ctotal)+VinN(C/Ctotal)+VrefP(C/Ctotal)

(3), (4) with Ctotal=2C+Cbias. The differential voltage is given by

Vd=k((VinP –VrefP) – (VinN–VrefN)) (5)

Selection of biasing capacitors with values Cbias=2C lead to an attenuation factor k=0.5 and similar conditions as discussed above for VDD

MIN with R2R input voltages VinN,VinP,VrefN and VrefP. This technique can be easily extended to triple, quadruple or more differential pairs with larger number of differential inputs which might be required for some applications. 3.3. Coarse and fine adjustment of threshold voltage using the floating gate technique

Fig. 2c shows a scheme to achieve digital coarse adjustment and analog fine adjustment of the reference voltage Vref. In this case a binary weighted capacitor array (BWCA) is connected to the floating gate of M2. Binary control voltages b1,b2,..bn (with values VDD or ground) are applied to the control terminal of the capacitors in the BWCA and if desired an analog voltage is applied to a termination capacitor with value C/2n. Another BWCA with all control terminals in parallel connected to Vin is used on the side of M1. BWCAs have a total capacitance with value C. This leads to a differential voltage Vd=k(Vin–Vref) with a reference voltage given by

Vref=VDD(b1/2+b2/4+..+bn/2n) +Vfine/2n (6) It can be seen that Vref can take R2R values. Coarse adjustment can take place with the digital control word b1,b2,..bn, while fine adjustment (if required) can take place can take place with voltage Vfine.

3.4. Offset compensation scheme

The resolution of the comparator is limited by the offset voltage Vos which is random in nature. For this reason high accuracy applications require offset compensation [10]. This is done in the proposed input stage by including two small valued capacitors Cos<<C connected to M1 and M2 as shown in Fig. 3a. Assuming the total capacitance (excluding Cbias) connected to the gate of each transistor has a value Cos~C/10. During the offset measurement phase ф1 (Fig. 3b) Cos is connected to the comparator output terminal while the remaining capacitance C–Cos is connected to VCMinp. This leads to an output voltage Vosamp=Vos(1+(C–Cos)/Cos) which is an amplified version of the input offset voltage by the factor Aos=(1+(C–Cos)/Cos) (~10). This voltage is stored in a capacitor Chold that serves also as load capacitor (and as compensation capacitor as discussed later) during this phase. This voltage is applied to the negative input during the evaluation phase ф2 though a voltage divider formed by Cos and C-Cos (Fig. 3c). This leads to a voltage on the negative input terminal with value: Vi–=Vos that compensates the offset Vos on the positive input terminal. Given that this scheme uses an amplified version of Vos for offset compensation

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Figure 3. Offset compensation scheme (a)

Scheme showing both phases and switches (b) Circuit connections in ф1 c) circuit

connections in ф2. it is highly insensitive to charge injection, clock feedthrough and leakage. Utilization of the comparator as an amplifier with gain Aos has the added advantage that no frequency compensation elements are required to prevent possible instability during ф1 in which the comparator is used with negative feedback. This is discussed in detail in section 4.2. Offset can be compensated on a periodic basis [10]. 4. Comparator architecture and stability considerations 4.1. Comparator architecture

In order to test the proposed R2R input stage a two (three) stage comparator was designed and fabricated in 0.5µm CMOS technology with nominal NMOS and

PMOS threshold voltages VTN=0.73V and VTP=–0.95V respectively as shown Fig. 4. It consists of a cascade of a R2R differential input stage (without hysteresis) and two CMOS inverters Following transistor dimensions were used M1,M2: W/L=6/0.6; M3,M4,MB: W/L=12/0.6; M5: W/L=4.5/0.6; M6: W/L=3/0.6. Outputs Vout and Vout’ from the two CMOS inverter output stages were available externally for testing purposes. The circuit was tested with load capacitance CL=75pF, VDD=1.5V and Ibias=30µA. The total area of the fabricated circuit was only 140x52µm2. Eight unit capacitors with value Cu=50fF (area~25µm2) and a biasing capacitor Cbias=400fF were connected to the floating gate of M1 and M2. A unit capacitor on each side was used for offset compensation (Cos=Cu). The terminals of the remaining unit capacitors were available as individual input terminals that could be grouped (if desired) in a binary weighted array with values Cu, 2Cu and 4Cu, in parallel or in any other test arrangement. 4.2. Stability considerations

An advantage of the proposed offset compensation scheme, together with the fact that minimum length L values were used for all transistors, is that no Miller compensation capacitor is required when the comparator is used with negative feedback during the offset measurement phase. This is due to the fact that the output pole is the dominant pole and the load capacitor serves as a hold and compensation element at the same time and that the loop gain is reduced by the feedback factor as explained next:

1) In the offset compensation phase the open loop gain is reduced by the feedback factor β=Cos/(C-Cos)

2) Utilization of minimum L values leads to relatively low output resistance r0 and very small parasitic capacitances Cx at the internal node X. For this reason this node has a high frequency pole of approximately fpx=40MHz.

3) For typical load capacitances CL=Chold>1pF at Vout the output pole fpout (or fpout’ if output Vout’ is used instead) is a dominant pole that satisfies easily the stability condition on the unity gain frequency funity of the negative feedfback loop: funity=Aβfpout<fpx/2. This requires approximately CL>40Cx for values A=200, β=0.1 with fpout=1/(2πr0CL) and fpx=1/(2πr0Cx). This results in values CL>0.4pF for the estimated value Cx=0.01pF. In this case the comparator has the capability to resolve signals of approximately ∆V =1.5/200=7.5mV. If the high gain output Vout’ is used there are two internal high frequency poles with approximately equal values fpx=fpy=40MHz at nodes x and y (also labeled Vout). In this case the stability

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M5

M6

biasI

1M M2

biasbiasC biasC

1fg

V 2fg

V

biasVV

Vi3-

MB

M3 M4

X

CuCu

Cu

Cu

CuCu

Cu

Cu

M7

M8osBVosAV

Vi1-

Vi2-

cV

1V2V

osBV

+

−

inV

fgV 1

fgV 2

biasV

biasVosAV

nV

Vout'

Vi1+

Vi3+

Vi2+

Vout

Vout'

Vout

Y

−

( a )

( b ) Figure 4 (a) Scheme of two (three) stage R2R comparator (b) Symbol.

condition is given by A’βfpout<fpx /4 (equivalently

CL>1600Cx or CL>16pF) and the resolution with offset compensation is ∆V=1.5/4000=0.375mV. These considerations determine the minimum value of Chold which operates both as hold and compensation capacitance during the offset measurement phase in which negative feedback is applied to the comparator. Besides providing stable behavior a relatively large value of Chold is of advantage to minimize charge injection errors in offset compensation. Chold determines the rise and fall time in phase 1. This is given by trise=2.2(2π/(Aβfpout)) and has an approximate value trise=650ns. This value is in good agreement with simulations and determines the maximum operating speed of the comparator when offset compensation is used.

5. Simulation and experimental results 5.1. Simulation results

As stated above given that minimum L was used for all transistors their output resistance r0 is relatively low. This causes the gain of each stage to be also relatively low. From simulations in Cadence DFII design environment the first stage was determined to have a gain of 10 (due to a factor 2 attenuation of the capacitive divider formed by C and Cbias), the second and third stages have gains of approximately 20. The internal pole had a frequency fpx=40MHz. The

comparator’s gain at output Vout was A=200. This gain was in very good agreement with experimental results. With the comparator connected in unity gain voltage follower configuration the gain bandwidth was GB=62MHz with CL=1pF and 63o phase margin. The gain for output Vout

’ is A’=4000V/V. The supply voltage used to test the comparator was VDD=1.5V. The bias current was Ib=30µA.

5.2. Experimental results

Given that both outputs were available externally and loaded with relatively large breadboard capacitances the comparator could be only characterized experimentally at relatively low frequency on the first (low gain) output Vout. The load capacitance (breadboard, test probes and wiring) was approximately CL=75pF. Fig. 5a, 5b and 5c show experimental input and output waveforms Vin, Vout (and Vref) upon application of a 10kHz R2R (1.5Vpp) triangular input signal for Vref=100mV, 500mV and 1.4V. This validates R2R operation of the comparator. Rise and fall times are in this case limited by slew rate which is given by SR=Io

MAX /CL. Positive and negative slew rates have values SR+=1.5V/µs and SR–=1.9V/µs which are determined by the maximum positive and a negative output currents Io

pos=110µA, Ioneg=190µA and

the CL=75pF. The micrograph of the circuit is shown in Fig. 6.

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6. Conclusions A low-voltage R2R differential input stage with

offset compensation was introduced. Its application for the implementation of single differential and double differential comparators was discussed. An offset compensation technique with reduced sensitivity to

(a)

(b)

(c)

Figure 5. Experimental R2R pulse output (bottom trace) and triangular input, reference

(top trace) waveforms (a) Vref=500mV (b) Vref=1400mV, (c) Vref=100mV.

Figure 6. Micrograph of the comparator circuitry. (Area 140µm x 52µm).

gain errors was used in the proposed stage. Experimental results of a test chip fabricated in 0.5µm CMOS technology validated R2R operation of the comparator with a single supply VDD=1.5V and with close to R2R reference voltages. 10. References [1] R. Gregorian, Introduction to CMOS Op-amps and Comparators, John Wiley and Sons, Inc., ISBN: 0-471-31778-0, 1999. [2] B. Razavi and B.A. Wooley, “Design Techniques for High-speed, High-Resolution Comparators”, IEEE J. of Solid State Circuits, vol. 27, no. 12, Dec. 1992, pp. 1916-1926. [3] C. Toumazou, G. Moschytz and B. Gilbert (Ed), Trade-Offs in Analog Circuit Design, The designers Companion, Kluwer Academic Publishers, Boston, Chapter 14 pp. 407-439, 2002. [4] Y. Hung and B. Liu, “1V CMOS Comparator for Programmable Analog Rank-Order Extractor, IEEE Trans. on Cir. and Sys. I, vol. 50, no.5, May 2003, pp. 673-677. [5] W. Redman-White, “A High Bandwidth Constant gm and Slew-Rate Rail-to-Rail CMOS Input Circuit and its Application to Analog Cells for Low Voltage VLSI Systems,” IEEE J. of Solid State Circuits, vol. 32, no. 5, May 1997, pp. 701-712. [6] S. Yan, J. Hu, T. Song and E. Sánchez-Sinencio, “Constant-gm techniques for rail-to-rail CMOS input stages: A comparative study”, in Proc. IEEE International Symp. on Circuits and Systems, pp. 2571-2574, May 23-26, 2005. [7] J. Ramírez-Angulo, S.C. Choi and G. Gonzalez-Altamirano, “Low-voltage circuits building blocks using multiple input floating gate transistors”, IEEE Trans. on Circuits and Systems I, vol. 42, no. 11, Nov. 1995, pp.971-974. [8] J. Ramírez-Angulo, R.G. Carvajal, J. Tombs and A. Torralba, “Low-voltage CMOS Op-amp with rail-to-rail input and output signal swing for continuous-time signal processing using multiple-input floating-gate transistors”, IEEE Trans. on Circuits and Systems II, vol. 48, no. 1, Jan. 2001, pp. 111-116. [9] E. Rodriguez-Villegas and H. Barnes, “Solution to trapped charge in FGMOS transistors”, Electronics Letters, vol. 39, no. 19, 18 Sep. 2003, pp.1416-1417. [10] C.C. Enz and G.C. Temes, “Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: Autozeroing, correlated double sampling, and Chopper Stabilization,” Proceedings of the IEEE, vol. 84, no. 11, Nov. 1996 pp. 1584-1614.

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