IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 2, FEBRUARY 2010 369

A Multiple-Input Digitally Controlled BuckConverter for Envelope Tracking Applications in

Radiofrequency Power AmplifiersMiguel Rodrıguez, Student Member, IEEE, Pablo Fernandez-Miaja, Student Member, IEEE,

Alberto Rodrıguez, Student Member, IEEE, and Javier Sebastian, Member, IEEE

Abstract—Wireless communication transmitters have very lowefficiencies due to the use of linear radiofrequency power ampli-fiers. Several techniques have been proposed over the years toimprove the efficiency of these systems. One of the most promisingis called the envelope tracking technique, which is based on usinga fast switching mode power supply to provide a varying voltage tothe power amplifier that tracks the envelope of the transmitted sig-nal. The amplifier can, thus, operate continuously near its theoret-ical maximum efficiency, greatly improving the overall efficiencyof the communication system. This paper proposes a multileveldigitally controlled power supply suitable for this application. It isshown to perform very well, achieving very high efficiency, high-output power capability and tracking bandwidths above 50 kHz.This paper also shows that the proposed system is able to produce a15% overall increase in efficiency in a complete envelope trackingsystem.

Index Terms—DC–DC power conversion, energy management,HF amplifiers, switched mode power supplies.

I. INTRODUCTION

ENERGY efficient systems are currently one of the majorconcerns of power engineers. In wireless radiofrequency

communication systems, the efficiency is usually very low dueto the use of linear radio frequency power amplifiers (RFPA).Class-A RFPA have a theoretical maximum efficiency of 50%,but in real transmitters in which signals with time-varying am-plitudes are transmitted, the average efficiency drops to 20% oreven less. In class-B amplifiers, which are widely used in thehigh frequency region (<30 MHz), the maximum efficiency is78%, but again in actual designs the average efficiency is usuallyaround 40%. This fact dramatically increases transmitter powerconsumption, not only due to the power wasted in the RFPA butalso to the required cooling system for the amplifier.

In modern transmitters, the RFPA needs to be highly lin-ear because the most common transmitting schemes, such asenhanced data rates for global systems for mobile commu-nications (EDGE), wideband code division multiplex access

Manuscript received April 22, 2009; revised July 15, 2009. Current versionpublished February 12, 2010. This work was supported by the Spanish Min-istry of Science and Education under Formacion de Profesorado UniversitarioProgram AP2006-04777 and AP2008-03380, and by Project TEC-2007-66917.Recommended for publication by Associate Editor J. A. Pomilio.

The authors are with the Power Supply Systems Group, Department ofElectrical and Electronic Engineering, University of Oviedo, Gijon 33204,Spain (e-mail: rodriguezmiguel.uo@uniovi.es; fernandezpablo.uo@uniovi.es;rodriguezalberto@uniovi.es; sebas@uniovi.es).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2009.2028732

(WCDMA), ortogonal frequency division multiplex (OFDM),etc., produce a time-varying signal whose amplitude varies overa wide range of voltage values [1]. Unfortunately, classicalamplifier theory [2] demonstrates that there is a tradeoff be-tween linearity and efficiency. Linear amplifiers (Classes A,AB, and B) are less efficient than nonlinear amplifiers (ClassesC, D, E, etc.). Several techniques have been proposed overthe years to combine linearity and high efficiency in RFPA.One of the most important is called the envelope tracking (ET)technique. This technique is based on varying the supply volt-age of the amplifier according to the envelope of the signalbeing transmitted, thus maintaining the amplifier always veryclose to its theoretical maximum efficiency operating condi-tions. Fig. 1 shows a transmitter without and with ET and itstypical waveforms.

This paper proposes a switched mode power supply to beused as an envelope tracker in medium to high-power ET sys-tems (20–200 W). It has to provide a rapidly varying outputvoltage with low ripple to avoid spectral regrowth [3], [4].It should also have high efficiency and high output powercapability. Several converter topologies have been proposedin this context: Høyerby and Andersen [4] proposed a syn-chronous buck converter with a fourth-pole output filter, twofeedback loops and a hysteretic controller that achieved 50kHz tracking bandwidth and was able to provide a peakpower above 400 W. Anderson and Cantrell [5] proposed asingle-ended primary inductor converter (SEPIC) that achieved1.25 MHz bandwidth and delivered nearly 125 W to a load with80% efficiency. Yousefzadeh et al. [6] presented a three-levelbuck converter that achieved advantages in terms of output volt-age ripple and efficiency. It was tested with 10 kHz two-tonesignals and it targeted low-power battery operated systems us-ing envelope elimination and restoration (EER) techniques. Sotoet al. [7] described a high power-low bandwidth system basedon a multiphase buck converter for an aircraft communicationsystem. Wang et al. [8] described a complete envelope track-ing converter for a very high bandwidth application that takesadvantage of a complementary linear amplifier to raise the band-width. Cantrell and Davis [9] also proposed a Class-E converterwhich was used to generate 500 kHz triangle waveforms.

The present paper proposes a novel multilevel topology thathas several advantages over other proposed alternatives for thisapplication. It has:

1) low voltage stresses in the semiconductors;2) low-output voltage ripple and low output filter values;

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Fig. 1. (a) Diagram of a conventional transmitter without ET. (b) Characteristic waveforms: as the RFPA work a considerable amount of time far from itsmaximum efficiency operating conditions, the average efficiency can be as low as 15–20%; (a) Diagram of a transmitter with ET; (b) Characteristic waveforms:RFPA always work close to its maximum efficiency operating conditions, which makes the overall efficiency increase towards the theoretical maximum. The dc–dcconverter in fact acts as an envelope amplifier.

3) low switching losses, which allow high frequency switch-ing;

4) high efficiency and high-output power capability.The proposed topology achieves higher efficiency and lower

output voltage ripple than conventional buck converters andthan other topologies like SEPIC or Class-E converters. Themultilevel structure is based on several different input voltagesources rather than in floating capacitors, thus avoiding the needof maintaining their voltages fixed and allowing the use of amore flexible control scheme.

The quasi-static behavior of the proposed topology and theoverall system operation are explained in this paper. The majorimplementation issues are clarified and simple design guide-lines are given. Finally, experimental results that validate theproposed system are presented and the conclusions are stated.

II. SYSTEM OVERVIEW

Fig. 2 shows a block diagram of the proposed system. Theconverter generates a multilevel square waveform that is fil-tered to obtain the desired output voltage. As in a conventionalpulsewidth modulation (PWM) system, the width of the squarewaveform pulses determines the voltage that is obtained at theoutput; the approach is very similar to that in conventional PWMinverters [10] or Class-D audio amplifiers [11]. The proposedpower topology is shown in Fig. 3. It is a generalization on thetwo-input buck converter proposed in [12], but has several inputdc voltage sources to generate a square multilevel waveform.Several series diodes are needed to avoid current flow fromhigher to lower voltage sources through the parasitic diodes ofthe MOSFETs. RFPA are considered to behave as a resistiveload in a quasi-steady state (represented by resistor R in Fig. 3),

Fig. 2. Block diagram of the proposed envelope tracking system (voltagelevels were arbitrarily selected).

which is certainly true under Class B operation. A digital systemacquires the envelope signal and generates the appropriate pulsepattern to allow the output voltage to track the input envelope.

The system operates without any feedback loop because thesupply voltage does not need to track the input envelope ex-actly. In RFPA with ET, there is an optimum supply voltagethat maximizes the efficiency of the RFPA. When the supplyvoltage is above this optimum value, the efficiency decreasesbut the output signal of the RFPA is not distorted. Therefore,even though it is desirable to track the envelope as accurately aspossible, the complexity and the bandwidth decrease that a feed-back loop will add to the converter do not seem to be justified inthis application, as is demonstrated in Section VI-D. Thus, thedigital control system includes an appropriate PWM generatoradapted to the multilevel topology, but there is no need for acompensator.

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RODRIGUEZ et al.: MULTIPLE-INPUT DIGITALLY CONTROLLED BUCK CONVERTER FOR ENVELOPE TRACKING APPLICATIONS 371

Fig. 3. Proposed multi-input buck topology. The higher voltage sources cor-respond to higher values of the index i (V0 can be considered to be 0 V).

Fig. 4. Equivalent circuit used for the quasi-static analysis.

III. QUASI-STATIC ANALYSIS OF THE TOPOLOGY

As the output voltage of the converter is continuously vary-ing, an absolute steady-state situation is never reached. However,provided that the switching frequency is sufficiently higher thanthe input signal bandwidth (a value of 10 is usually consideredhigh enough for the switching frequency—input signal band-width ratio [4]–[7], [11]), the output voltage will not changesignificantly during one switching cycle. For the sake of clarity,the forthcoming analysis assumes that the output voltage re-mains approximately constant within one switching cycle, thusallowing us to deduce several important relationships that de-termine the converter operation in a simple manner: conversionratio, discontinuous conduction mode limits, etc. This approachalso enables us to appreciate the major advantages that this solu-tion has in comparison with the previously proposed topologies.In the following analysis, two legs (for instance, i and j) are con-sidered to be switching alternatively to obtain a certain outputvoltage, Vout .

In several sections of the following analysis, the input dcvoltages are assumed to be equally spaced, i.e.

Vi =V

ni , i = 1, . . . , n (1)

n being the number of input levels (excluding the ground volt-age, V0). However, it is worth noting that the separation of theinput voltages is not a straightforward decision, as it dependson the probability density function of the envelope signal [13].

A. Conversion Ratio in Continuous Conduction Mode (CCM)

The equivalent circuit used to calculate the conversion ratioin CCM is shown in Fig. 4. During an interval Ton , the upperswitch (Mi) is closed and the lower switch (Mj ) is opened [see

Fig. 5. (a) Equivalent circuit during Ton = dij T . (b) Equivalent circuit duringToff = (1 − dij ) T . (c) Voltage square waveform applied to the lowpass filterto obtain the output voltage.

Fig. 5(a)]. The voltage applied to the inductor is

VL,To n = Vi − Vout . (2)

During an interval, Toff , switch Mi is opened and switch Mj

is closed [see Fig. 5(b)], Therefore, the voltage applied to theinductor is

VL,To f f = Vj − Vout . (3)

From the volts-second balance in L, and defining as usual

Ton = dijT (4)

Toff = (1 − dij ) T (5)

T being the switching period and dij the corresponding dutycycle between voltages Vi and Vj , the conversion ratio in CCMis easily obtained

Vout = dijVi + (1 − dij ) Vj . (6)

In the case of equally spaced input voltages, (6) becomes

Vout =V

n(dij i + (1 − dij ) j) . (7)

Equation (6) shows that the output voltage varies between Vj

(dij = 0) and Vi (dij = 1). Thus, a certain output voltage, Vout ,fulfilling Vj < Vout < Vi can be obtained by setting the appro-priate duty cycle.

B. Calculation of the Inductance Value that Ensures CCMOperation

The linear relationship between dij and Vout that exists inCCM facilitates the tracking of a certain envelope signal. Toensure that (6) remains valid over the entire operating range ofthe converter, CCM operation must be guaranteed. The proce-dure to calculate the minimum inductance value that guaranteesCCM operation is very similar to the one followed in [12]. Fig. 6shows the equivalent circuits in discontinuous conduction mode(DCM) and the corresponding waveforms. The volts-secondbalance can be applied as in Section III-A to obtain

(Vi − Vout) dij = (Vout − Vj ) d′ij (8)

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372 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 2, FEBRUARY 2010

Fig. 6. (a) Equivalent circuit during dij T . (b) Equivalent circuit during d′ij T .(c) Equivalent circuit during (1 − (dij + d′ij ))T . (d) Voltage square waveformapplied to the lowpass filter and current through the inductance.

d′ij being the duty cycle corresponding to transistor Mj . Theaverage current that circulates through the inductor (output cur-rent) is

iL,avg = iout =12

(dij + d′ij

)iL,max =

Vout

R(9)

iL,max being the maximum inductance current

iL,max =Vi − Vout

LdT. (10)

Equations (8)–(10) can be used to obtain the conversion ratio inDCM

Vout =12

(

Vj −d2

ij (Vi − Vj )K

+

√√√√

(

Vj −d2

ij (Vi − Vj )K

)2

+4d2

ij

KVi (Vi − Vj )

(11)

K being

K =2L

RT. (12)

At the boundary between DCM and CCM, dij and d′ij fulfill

d′ij = 1 − dij (13)

and (6) and (11) become the same. The value of K at the bound-ary, Kboundary , can be expressed from (6) and (11) as

Kboundary =dij (1 − dij ) (Vi − Vj )

dij (Vi − Vj ) + Vj. (14)

Defining λij =Vi

Vj, 1 < λij < ∞, (14) can be expressed as

Kboundary =dij (1 − dij ) (λij − 1)

dij (λij − 1) + 1. (15)

Fig. 7 shows Kboundary as a function of dij for several valuesof λij : for a certain value of K and λij , there is a duty cycle

Fig. 7. Kboundary as a function of the duty cycle for different values of λij .

value that will lead the converter to the limit between CCMand DCM, and lower duty cycles will certainly cause DCMoperation. Fig. 7 also shows that there is a maximum valueof Kboundary , Kboundary ,max , for each case. To ensure CCMoperation, it is only necessary to select a value of K higher thanKboundary ,max . Kboundary ,max can be easily found by derivation

dKboundary

dλij= 0. (16)

Equations (15) and (16) yield

Kboundary ,max =

(√λij − 1

)2

λij − 1. (17)

Setting

K > Kboundary ,max (18)

yields

Lmin =R

2fsw

(√λij − 1

)2

λij − 1(19)

fsw being the switching frequency (fsw = 1/T ). Equation (17)shows that higher values of λij require higher inductance valuesto ensure CCM operation. The worst case occurs when outputvoltages below V1 are needed, because in this situation Vj =0 and λij reaches ∞. Equation (19) then becomes that of aconventional buck converter

Lmin =R

2fsw. (20)

C. Output Voltage Ripple

The current that circulates through the filter inductor is madeup of two components: the average output current and a cer-tain current ripple. Assuming that the average current circulatesthrough the load, the remainder charges and discharges the out-put filter capacitor, causing a ripple in the output voltage. Fig. 8shows the current through the inductor.

The voltage change in the capacitance due to the chargingcurrent of Fig. 8 is

∆Vout =1C

∫iC dt =

1C

12

∆iL2

T

2(21)

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RODRIGUEZ et al.: MULTIPLE-INPUT DIGITALLY CONTROLLED BUCK CONVERTER FOR ENVELOPE TRACKING APPLICATIONS 373

Fig. 8. Current circulating through the output filter inductor. The shaded areasrepresent the charge injected into the capacitor (it is charged while iout < iL )or removed from it (it is discharged while iout > iL ).

and ∆iL can be expressed as

∆iL =(Vi − Vout) dijT

L. (22)

Therefore, using (21), (22), and (6), the output voltage ripplecan be obtained

∆Vout =dij (1 − dij ) (Vi − Vj )

8LCf 2sw

. (23)

Equation (23) shows that the closer Vi and Vj are, the lowerthe ripple. As different legs can be selected to obtain a certainVout [see (6)], (23) suggests that the two closest voltages tothe desired Vout must be chosen to minimize ∆Vout . This factmeans that Vi and Vj must fulfill

Vi > Vout > Vi−1 . (24)

In the case of equally spaced input voltages and taking intoaccount (24), the output voltage ripple becomes

∆Vout =dij (1 − dij ) V

8LCf 2swn

. (25)

Equation (25) is valid for a conventional buck topology by sim-ply making n = 1. It then becomes apparent that the outputvoltage ripple is divided by the number of input voltages (n)in comparison with the ripple in a conventional buck topology.Thus, the proposed topology achieves low output voltage ripple.

D. Semiconductor Stresses

Table I shows the maximum voltages and currents that thesemiconductors have to withstand. The maximum currents inTable I are calculated assuming that the minimum ripple switch-ing strategy is used, i.e., that (24) is fulfilled. This implies thata certain semiconductor (e.g., Mi−1) has to withstand the max-imum current that can circulate through Mi . Fig. 9 clarifies thisexplanation. For the sake of simplicity, these currents are calcu-lated assuming zero current ripple in the output filter inductance(a more accurate calculation would use the maximum induc-tance current, iL,max ). It is also worth noting that, as the outputcurrent depends on the input voltages applied to the filter (be-cause the load works as a constant value resistor), the higher thevoltages applied, the higher the output current. This is clearlyseen in Table I.

It can be seen that transistors corresponding to lower valuesof i (M1 ,M2 , . . .) have to withstand less voltage than tran-sistors corresponding to higher values of i (Mn,Mn−1 , . . .).Conversely, diodes D1 ,D2 , . . . have to withstand higher volt-

TABLE IMAXIMUM STRESSES OF SEMICONDUCTORS IN THE PROPOSED TOPOLOGY

Fig. 9. Current through the output filter inductance and through semicon-ductors of legs i and i − 1. Both semiconductors have to withstand thesame maximum current, i.e., the maximum current that circulates through theinductance.

ages than diodes Dn−1 ,Dn−2 , . . .. In conclusion, semiconduc-tors withstand different voltages and currents, a fact which canlead to the use of different semiconductors for each leg (i.e.,lower voltage diodes can be used in legs corresponding to highervalues of i).

E. Switching Losses

As regards the switching losses, a simple comparison witha conventional buck topology can be made using the classicalpiecewise-linear losses model. Fig. 10 shows the equivalent cir-cuit of the proposed converter during a switching transition.During dijT , Mi is on, and it approximately carries the out-put current iout . During (1 − dij ) T , Mi is off and withstandsVi − Vj . Following [14], switching losses in leg i can simply beexpressed as

Ploss,i =(Vi − Vj ) iout

2fsw (tsw ,L−H + tsw ,H−L) (26)

tsw ,L−H , tsw ,H−L being the times it takes the gate drive circuitto charge and discharge the gate capacitance, respectively. Asusing Schottky diodes minimizes reverse recovery losses, theseare not taken into account in the calculations. Conversely, duringdijT , Mj is off and Dj withstands Vi − Vj . During (1 − dij ) T ,Mj is on and it carries the output current, iout . Whereas Mj

operates under zero voltage switching conditions, Dj does not,and switching losses are not eliminated, but only transferredfrom Mj to Dj . Again, switching losses in leg j can be expressedas

Ploss,j =(Vi − Vj ) iout

2fsw (tsw ,L−H + tsw ,H−L) . (27)

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374 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 2, FEBRUARY 2010

Fig. 10. Equivalent circuits during switching transitions: (a) Equivalent circuitduring dij T . (b) Equivalent circuit during (1 − dij ) T .

Equations (26) and (27) yield a total switching losses equal to

Ploss,sw = (Vi − Vj ) ioutfsw (tsw ,L−H + tsw ,H−L) . (28)

Using the minimum ripple strategy (24) and equally spacedvoltages (1), (28) becomes

Ploss,sw =V iout

nfsw (tsw ,L−H + tsw ,H−L) . (29)

As iout depends on the switching legs, power losses aresmaller in legs corresponding to smaller i values. Provided thatswitching times do not change from one topology to another,switching losses in a conventional buck converter can be ap-proximated as

Ploss,buck =V iout

2fsw (tsw ,L−H + tsw ,H−L) . (30)

Equations (29) and (30) show that, for the same operating con-ditions (same iout and V ), switching losses in the proposedtopology are n/2 times smaller than in a conventional bucktopology. Thus, the proposed topology achieves low switchinglosses.

IV. DESIGN PROCEDURE

A simple design procedure is presented in this section. Theobjective is to suitably select the output filter components andthe switching frequency in order to fulfill bandwidth and outputvoltage ripple requirements. As there is no feedback loop in theproposed system, the bandwidth is mainly determined by theoutput filter cutoff frequency

fcutoff =1

2π√

LC. (31)

The output ripple in the case of equally spaced input voltagesis given by (23), which can be rewritten as

∆Vout =4V π2dij (1 − dij )

8n

(fsw

fcutoff

)2 . (32)

As the desired filter response is the fastest possible withoutovershoot, classical control theory [15] yields

12R

√L

C=

1√2

=⇒ C =1

2√

2πfcutoff 2R. (33)

The previous statements suggest the following design proce-dure.

Fig. 11. High-frequency floating driver scheme.

1) Select the cutoff frequency and the output voltage rippledepending on the application.

2) Find the minimum value of fsw using (32).3) Find L and C using (33) and (31).It becomes apparent from (32) and (33) that, for a fixed

switching frequency, there exists a tradeoff between the filtercutoff frequency (i.e., the tracking bandwidth) and the outputvoltage ripple that has to be taken into account in the design.

V. IMPLEMENTATION OF THE SYSTEM

Two major difficulties arise when implementing the proposedsystem. The first one is related to the MOSFET driving circuitry:as the transistors are not in a common source configuration, ahigh-frequency floating driver must be used. The second onerefers to the digital control system that generates the appropriateMOSFET control signals, allowing the output voltage to trackthe input envelope.

A. MOSFET Driving System

The floating driving system that has been designed is shownin Fig. 11. A very fast digital isolation integrated circuit (IL610)transmits the control pulses to the isolated side. There, a highfrequency driver integrated circuit (El7156) provides the gatecurrent to the MOSFET. The isolated side of the driving cir-cuitry is powered by a small isolated power supply, built usingUC3525 controller from Texas Instruments. As very low powerwas required, an unregulated full-bridge was implemented usingthe complimentary outputs of the controller to directly drive asmall transformer built in an E12 core, using 3F3 material. Thetransformer was designed to have low primary-to-secondarycapacitance, in order to guarantee good isolation between theisolated-side ground (MOSFET source terminal), which suf-fers high frequency voltage variations, and the digital systemground. In the secondary side, a four-diode rectifier and a fil-tering capacitor were used to obtain a constant output voltage.

B. Digital Control System

Fig. 12 shows the digital control system designed to gener-ate the adequate MOSFET control signals. It was implementedusing a low cost Spartan 3E FPGA. The analog envelope signalis first converted into an N bit digital signal, v env(N-1:0), by

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RODRIGUEZ et al.: MULTIPLE-INPUT DIGITALLY CONTROLLED BUCK CONVERTER FOR ENVELOPE TRACKING APPLICATIONS 375

Fig. 12. General block diagram of the digital pulse generation system.

an analog-to-digital converter (ADC). The relationship betweenthe envelope signal and the desired output voltage is given by

Vout =V

2N − 1v env. (34)

Therefore, the minimum ripple strategy expressed in (24) be-comes:

Vi

V

(2N − 1

)> v env ≥ Vi−1

V

(2N − 1

). (35)

The appropriate switching legs can then be found by carryingout a maximum of n − 1 comparisons, n being the number ofinput levels as usual. The number of bits needed to select theswitching legs LS is

LS = log2 n . (36)

Using (6) and (34), the duty cycle that generates the requiredoutput voltage can be obtained

di,i−1 =v env − Vi−1

V

(2N − 1

)

Vi

V(2N − 1) − Vi−1

V(2N − 1)

=

v env · V2N − 1

− Vi−1

Vi − Vi−1.

(37)As (37) yields a value ranging between 0 and 1, duty(M-1:0) isobtained by:

duty(M-1:0) = di,i−1(2M − 1

). (38)

Finally, a digital pulsewidth modulator (DPWM) generates theactual PWM control signal, which is applied to the appropriateMOSFETs by a level selection logic block using ls_control. TheDPWM is described in detail in Subsection V-C.

The system can be greatly simplified if equally spaced in-put voltages are chosen and log2 n is an integer. In that case,ls_control is directly obtained as

ls control (LS − 1 : 0) = v env (N − 1 : N − LS) . (39)

Furthermore, if M is chosen as

M = N − LS (40)

then duty(M-1:0) becomes

duty(N-LS-1:0) = v env (N − LS − 1 : 0) . (41)

Fig. 13 clearly shows the meaning of (40) and (41).

Fig. 13. Direct assignment of v_env(N-1:0) represented by (40) and (41).

Fig. 14. Classical hybrid DPWM architecture: M ′ bits are used to select thedelayed clock.

C. DPWM Architecture

As switching frequencies above the Megahertz will probablybe required and in order to allow a reasonable duty cycle resolu-tion without dramatically increasing the system clock frequency,a hybrid DPWM was used [16], [17]. Fig. 14 shows the classicalhybrid DPWM architecture; it is based on a tapped delay lineand a multiplexer that work in combination with the classicalcounter-based DPWM. The multiplexer uses M′ bits to selectthe appropriate delayed clock. The hybrid DPWM allows theduty cycle resolution to be increased by a factor of 2M ′

withoutincreasing the system clock frequency.

Although several implementations of hybrid DPWMs are pos-sible, a very simple one that uses the internal digital clockmanager of the FPGA was chosen. It is based on the archi-tecture proposed in [18]. The main idea is shown in Fig. 15(a):the digital clock manager acts as a tapped delay line and gen-erates four phase–shifted clocks, so M′= 2. The appropriatephase is selected by duty(1:0) using a 4-to-1 multiplexer, whileduty(M-1:2) is used as the input to the counter-based DPWM.The final design includes several modifications to the one shownin Fig. 15(a) and is shown in Fig. 15(b). In order to avoidproblems caused by the delay between asynchronous and syn-chronous parts, a pseudo-synchronous approach was designed.Four D-latches were used to synchronize the output of thecounter-based DPWM (which is in turn synchronized with sig-nal clk270) with each of the four delayed clock signals. Thisapproach avoided the use of logic gates and minimized delayproblems.

VI. EXPERIMENTAL RESULTS

The performance of the proposed system was tested via sev-eral experiments that are described in the following sections.As the switching frequencies were expected to be high, two

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TABLE IIMAIN CHARACTERISTICS OF TRANSISTORS USED IN PROTOTYPES 1 AND 2

Fig. 15. (a) Hybrid DPWM architecture proposed in [7]. (b) Final pseudo-synchronous hybrid DPWM architecture implemented.

prototypes were built with different approaches. Prototype 1[Fig. 16(a)] was built using conventional low-cost transistors(IPD135N03), while Prototype 2 [Fig. 16(b)] was built us-ing expensive low-parasitic RF transistors more suitable forhigh-frequency switching (MRF373) [19]. The main character-istics of the aforementioned transistors are shown in Table II.MBR340T Schottky diodes were used in both prototypes. Thedigital control system was also common to both prototypes anda 12 bit THS1230 ADC was used to sample the envelope signal.A value of M = 8 was selected for the duty cycle resolution.Three input levels (5, 10, and 15 V) were employed.

Table III shows the output filter values used in both proto-types, calculated by applying the design procedure in Section IVusing the nominal switching frequency and load values.

In Sections VI-A and VI-B, both prototypes are comparedin terms of envelope tracking capability and efficiency. In theremaining Subsections, only Prototype 1 is used.

Fig. 16. (a) Prototype 1: low cost IPD135N03 transistors. (b) Prototype 2: RFMRF373 transistors.

TABLE IIIFILTER VALUES AND MAIN CHARACTERISTICS OF PROTOTYPES 1 AND 2

A. Signal Tracking Performance

In this section, a 5 Ω resistive load is used to simulate the be-havior of the amplifier. Fig. 17 shows the results obtained withPrototype 1. It can be seen that the system is able to track dif-ferent envelope signals with different shapes and bandwidths.Figs. 17(a) and (b) show two sinusoidal envelopes of 20 and50 kHz, respectively. Fig. 17(c) shows a 100 kHz two-tone sig-nal, a common envelope signal used to test the linearity of RFPAin communication signals. The output voltage is distorted nearthe zero crossing due to the infinite bandwidth of the two-tonesignal. Fig. 17(d) shows an EDGE envelope signal, typicallyused in second generation mobile communications networks.The ET system was able to track the signal quite precisely,losing accuracy near the fast variation regions that correspondto the highest frequency components of the signal. However,as already mentioned, this phenomenon only causes a slightreduction in overall system efficiency.

Fig. 18 shows the results obtained with Prototype 2. Thewaveforms obtained are very similar to those in Fig. 17.However, there were certain differences. The board layout ofPrototype 2 could not be optimized due to the size of the RFtransistors. As a consequence, noise levels in the circuit and par-asitic resonances limited the achievable tracking bandwidth; themaximum achievable output voltage was also reduced, mainlyby the noise that affected the acquisition system and by the highRds,on of the MRF373. This reduction is clearly observed inFig. 18, where the output voltage was not able to exceed 12 V.

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RODRIGUEZ et al.: MULTIPLE-INPUT DIGITALLY CONTROLLED BUCK CONVERTER FOR ENVELOPE TRACKING APPLICATIONS 377

Fig. 17. Experimental results obtained with Prototype 1. (a) Tracking of a20 kHz sinusoid. (b) Tracking of a 50 kHz sinusoid. (c) Tracking of the 100 kHzenvelope of a two-tone signal. (d) Tracking of the envelope of an EDGE signal.

B. Efficiency Comparison

The efficiency of the power stage was measured while track-ing the 10 kHz envelope of a two-tone signal, which turns outto be a 10 kHz rectified sinusoid. The digital system powerconsumption was not included in the measurements. The volt-age and the current provided by each of the three input volt-age sources was measured to calculate the total average inputpower. The average output power was found by measuring theoutput voltage and the load value. A non-inductive load that was

Fig. 18. Experimental results obtained with Prototype 2. (a) Tracking of the40 kHz envelope of a two-tone signal. (b) Tracking of the envelope of an EDGEsignal.

Fig. 19. Efficiency obtained with Prototype 1.

characterized both in dc and at higher frequencies using a preci-sion impedance analyzer (Agilent 4294A) was used. It was alsoappropriately cooled to avoid thermal drift.

Fig. 19 shows Prototype 1 results for different load condi-tions and switching frequencies. The x-axis indicates the av-erage output power. Note that the peak power levels are muchhigher: for instance, with the two-tone waveform a mean powerof 35 W corresponds to a peak power of around 90 W. It can beseen that the efficiency was very high, above 92% at full load(20 W average output power) and switching at 4.6 MHz, andaround 95% at lower switching frequencies. This notable effi-ciency was obtained for several reasons: first, the low switchinglosses provided by the proposed multilevel topology; second, thegood switching behavior of the transistors, along with the highfrequency driver performance; and third, the low conductionlosses of these transistors due to their low Rds,on . No heatsinkor forced cooling system were used during the measurements,which demonstrates the high power capabilities of the topology.

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378 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 2, FEBRUARY 2010

Fig. 20. Efficiency obtained with Prototype 2.

Fig. 21. Output voltage ripple measured using the proposed topology and aconventional buck converter.

Fig. 20 shows the results obtained with Prototype 2. Theefficiency is clearly around 4–5% below the efficiency ofPrototype 1. This result demonstrates that, in spite of their goodhigh frequency behavior, the conduction losses in the RF tran-sistors are too high and reduce the efficiency. Furthermore, thesetransistors reached very high temperatures, which in fact lim-ited the output power that could be obtained. It can be noticedthat the output power values obtained in Fig. 20 are substan-tially lower than those shown in Fig. 19. As the results obtaineddemonstrated that Prototype 1 is clearly superior to Prototype 2,the former was used to obtain the results presented in SectionsVI-C and VI-D.

C. Output Voltage Ripple

One of the advantages of the proposed topology is the lowoutput voltage ripple that can be achieved. Fig. 21 shows acomparison between the output voltage ripple obtained using aconventional buck topology and Prototype 1; the same prototypewas used as the conventional buck, but with only one activelevel. Therefore, the output filter values, load and output voltagewere kept constant during the experiment. The results were alsocompared with the theoretical ripple provided by (23). It canbe seen that the results match the theoretical predictions veryaccurately in both cases. The output voltage ripple improvementalso becomes apparent when using the proposed topology.

D. Complete Envelope Tracking System Performance

Fig. 22(a) shows a block diagram of the setup used to measurethe performance of the proposed system while performing ETwith a real RF amplifier. An Agilent 33210A function generatorwas used to generate the information (modulating) signal. Thissignal was split in two parts: one went to the digital controlsystem, while the other went to a modulator which generated theRF input for the RFPA. The amplifier (model KL200) operatedin Class B at 27 MHz, with 100 W peak envelope power incontinuous wave mode [20]. As its rated supply voltage was12 V, the input voltage levels were set to 12, 8, and 4 V duringthis experiment. Fig. 22(b) shows the actual experimental setup.

To simplify the operation of the system, amplitude modu-lation was used with sinusoids as the modulating signals. Asthe system was not focusing on a specific communication sys-tem, the use of sinusoidal signals allowed testing the system interms of bandwidth and efficiency from a general perspective.As the modulator limited the bandwidth of the setup in practice,tracking bandwidths above 100 kHz could not be obtained. It isworth noting that several modifications were carefully made tothe amplifier, especially the removal of several bypass capaci-tances (see [20]) that might otherwise greatly limit the trackingbandwidth. However, they were added again for the fixed supplymeasurements to ensure the correct operation of the amplifier.

Fig. 23 shows a few sample waveforms. Fig. 23(a) and (b)shows the output RF signal and the supply voltage without andwith ET respectively, with a 50 kHz sinusoid as the modulat-ing signal. Fig. 23(c) and (d) shows the output RF signal andthe supply voltage without and with ET with a 100 kHz sinu-soid. It can be seen that the proposed converter is able to trackboth signals accurately, with no significant distortion at the out-put. The mean output power delivered to the load was around15 W, whereas the maximum instantaneous power was 80 Wand the peak envelope power around 40 W. Again, no heatsinksor forced cooling system were necessary for the proposed powersupply.

The efficiency of the system without ET and with ET wasmeasured. In the first case, the efficiency of the RFPA was mea-sured while it was being supplied by a constant voltage source.In the second case, the efficiency of the power stage and theRFPA was also measured while the ET technique was beingcarried out, with sinusoids of different frequencies as envelopesignals. The digital system was excluded again from the mea-surements. The average output RF power was carefully mea-sured: the output voltage on the 50 Ω load (4×RFP-50-50RCG)was measured directly using a high bandwidth oscilloscope andalso using a peak detector, which provided only the envelopeamplitude. Both results were very similar. Again, the load wascharacterized by a precision impedance analyzer and appropri-ately cooled to avoid thermal drift. Equations (42) and (43) showhow the efficiency was calculated in each case

ηwithoutET =Poutput

Psupply(42)

ηwithET =Poutput

Psupply ,1 + Psupply ,2 + Psupply ,3(43)

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RODRIGUEZ et al.: MULTIPLE-INPUT DIGITALLY CONTROLLED BUCK CONVERTER FOR ENVELOPE TRACKING APPLICATIONS 379

Fig. 22. (a) Block diagram of the experimental setup used to test the complete envelope tracking system. (b) Picture of the experimental setup that includes thelinear 100 W RFPA, the modulating system and the RF load (the power supply is not shown).

Fig. 23. Experimental results obtained with the setup shown in Fig. 22(a). The output RF signal and the supply voltage are shown: (a) 50 kHz sinusoid withoutET. (b) 50 kHz sinusoid with ET. (c) 100 kHz sinusoid without ET. (d) 100 kHz sinusoid with ET. Note that the output RF voltage is higher than the supply voltagedue to the presence of an output impedance matching filter in the amplifier [20].

Poutput being the output average power provided to the load,Psupply being the average power provided by the single powersupply (without ET) and Psupply ,i being the power provided byeach of the input sources of the multilevel topology; ηwithoutETand ηwithET are the efficiency with constant voltage supply andwith the envelope tracking system, respectively. The measure-ments were taken under the same experimental conditions (sameaverage output RF power and modulating signal) to ensure a faircomparison. As the power consumption of the modulator wasalmost the same in both cases, it was consequently not includedin the calculations.

TABLE IVOVERALL SYSTEM EFFICIENCY WITHOUT AND WITH ET

Table IV shows the results. The first row shows the ef-ficiency of the RFPA with constant supply, while the sec-ond shows the efficiency while ET was being carried out. A

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380 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 2, FEBRUARY 2010

Fig. 24. Output RF signal frequency spectrum: (a) 50 kHz modulating sinu-soid with fixed supply; (b) 50 kHz modulating sinusoid with ET. (c) 100 kHzmodulating sinusoid with fixed supply. (b) 100 kHz modulating sinusoid withET.

noteworthy improvement is observed in the results, with an in-crease in efficiency of nearly 20%.

As the spectral purity of the RF signal is always a majorconcern in communication systems, the influence that the ETsystem had over the output RF signal spectrum was measured.The frequency spectrum of the output RF signal was acquired

Fig. 25. Comparison of the frequency spectrum of the output RF signal whendifferent switching frequencies are used in the converter; the output voltageripple is divided by 9 when the switching frequency changes from 1.5 to4.5 MHz.

using an Agilent 3589E Spectrum Analyzer. Fig. 24 shows theresults.

Whereas the ideal frequency spectrum of the transmitted AMsignal is composed of the carrier and two side bands [indicatedin Fig. 24(a)], the actual spectrum includes several peaks, calledintermodulation products. These components appear due to non-linearities in the amplifier and the modulator and are quantifiedby the information to intermodulation quotient (IIMD), definedas

IIMD =upper band power

1st intermodulation product power(dB) . (44)

As Fig. 24 shows, the IIMD is around 20 dB both in the fixedvoltage supply case and with ET. This value does not changefrom one case to another, which demonstrates that the ET systemdid not decrease the linearity of the system.

Fig. 24 clearly shows the spectral regrowth effect, caused bythe output voltage ripple. In this case, as the regrowth is farbelow the transmitted power levels, it does not cause noticeableeffects in the transmitted signal. However, in certain applicationswith very stringent spectral specifications, this effect may playa major role. Fig. 25 shows the effect that the output voltageripple (modified by changing the switching frequency) had onthe output signal spectrum. The ripple was divided by a factor of9, while the spectral regrowth decreased around 5 dB. Thus, thelow output voltage ripple achievable with the proposed topologymakes it especially suitable for applications in which spectralregrowth must be minimized.

VII. CONCLUSION

This paper has proposed a complete envelope tracking sys-tem to improve the efficiency of communication systems thatuse linear RFPAs. The proposed power topology is based ona multiple-input buck converter. It has been demonstrated thatit achieves low switching losses, low stresses in the semicon-ductor, low output voltage ripple, very high efficiency and highoutput power capability. As in the multiple-input topology thelosses are distributed among several semiconductors, it is es-pecially suitable to handle high output powers and to be easilyadapted to different output power levels. Moreover, high switch-

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RODRIGUEZ et al.: MULTIPLE-INPUT DIGITALLY CONTROLLED BUCK CONVERTER FOR ENVELOPE TRACKING APPLICATIONS 381

ing frequencies can easily be reached, thus allowing a high track-ing bandwidth. A suitable digital system has also been proposedto appropriately control the switches to track an arbitrary wave-form, regardless of its exact characteristics. Its main part wasthe hybrid DPWM core, which along with the designed float-ing high frequency drivers, allowed high frequency switchingand precise control of pulsewidth in such a way that arbitraryenvelope signals could be reproduced.

However, the proposed system also has certain drawbacks: ithas more switches than other topologies, and several input dcvoltages have to be generated by means of a previous stage (e.g.,a simple multioutput flyback converter or single independentconverters), which will cause a slight decrease in the efficiencyimprovements shown in Table IV. The proposed digital system isalso relatively complex. Nevertheless, a very good performancecan be obtained in spite of the increased complexity. Further-more, the proposed system is designed to be integrated withRF transmitters operating in the range of 50–200 W; as thesetransmitters are quite complex and thereby quite expensive, thecontribution of the proposed system to the total cost is small.Even the digital control system could be implemented using thedigital signal processing units present in such equipment.

The experimental results demonstrate that the proposed sys-tem is able to notably improve the efficiency of linear RFPAswithout any major change in the RF output signal, which makesit suitable for performing envelope tracking in RF transmitters.

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[6] V. Yousefzadeh, E. Alarcon, and D. Maksimovic, “Three-level buck con-verter for envelope tracking applications,” IEEE Trans. Power Electron.,vol. 21, no. 2, pp. 549–552, Mar. 2006.

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[8] F. Wang, A. Yang, D. Y. C. Lie, D. Kimball, L. Larson, and P. Asbeck,“Design of wide bandwidth envelope tracking power amplifiers for OFDMapplications,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 4, pp. 1244–1255, Apr. 2005.

[9] W. H. Cantrell and W. A. Davis, “Amplitude modulator utilizing a high-Qclass-E DC-DC converter,” in Proc. IEEE MTT-S Int. Microw. Symp., Jun.2003, vol. 3, pp. 1721–1724.

[10] D. G. Holmes and T. A. Lipo, Pulse Width Modulation for Power Convert-ers. Piscataway, NJ: IEEE Press Series on Power Engineering, 2003,ch. 3, pp. 95–154.

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[20] KL200 schematic diagram. (2005). [Online]. Available: http://www.rmitaly.com

Miguel Rodrıguez (S’06) was born in Gijon, Spain,in 1982. He received the M.S. degree in telecommu-nication engineering from the University of Oviedo,Gijon, in 2006. He is currently working toward thePh.D. degree at the Department of Electrical andElectronic Engineering, University of Oviedo.

His current research interests include dc–dcconversion, high-frequency power conversion, andpower-supply systems for RF amplifiers.

Pablo Fernandez-Miaja (S’08) was born in Oviedo,Spain, in 1984. He received the M.S. degree intelecommunications engineering from the Universityof Oviedo, Gijon, Spain, in 2007. He is currentlyworking toward the Ph.D. degree at the Departmentof Electrical and Electronic Engineering, Universityof Oviedo, on dc–dc converters to feed RF power am-plifiers.

His current research interest include dc–dc con-verters, digital control of switching power supplies,and techniques to increase the efficiency of RF power

amplifiers like envelope tracking.

Alberto Rodrıguez (S’07) was born in Oviedo,Spain, in 1981. He received the M.S. degree intelecommunications engineering from the Universityof Oviedo, Gijon, in 2006. He is currently working to-ward the Ph.D. degree at the Department of Electricaland Electronic Engineering, University of Oviedo.

He was a Telecommunications Engineer with theGovernment of the Principality of Asturias and anAssistant Professor with the Department of ElectricalEngineering, University of Oviedo during 2006. Hehas been with the University of Oviedo on full time

since 2007. His current research interests include bidirectional dc–dc powerconverters.

Javier Sebastian (M’86) was born in Madrid, Spain,in 1958. He received the M.Sc. degree from the Poly-technic University of Madrid, Madrid, and the Ph.D.degree from the University of Oviedo, Gijon, Spain,in 1981 and 1985, respectively.

He was an Assistant Professor and an Asso-ciate Professor at both the Polytechnic University ofMadrid and at the University of Oviedo, in Spain.He has been with the Department of Electrical andElectronic Engineering, University of Oviedo, since1992, where he is currently a Professor. His current

research interests include switching-mode power supplies, modeling of dc–dcconverters, low output voltage dc–dc converters and high-power factor rectifiers.

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