device characterization ece/che 4752: microelectronics processing laboratory gary s. may april 1,...
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Device Characterization
ECE/ChE 4752: Microelectronics ECE/ChE 4752: Microelectronics Processing LaboratoryProcessing Laboratory
Gary S. May
April 1, 2004
Outline
NMOS Device PhysicsNMOS Device Physics PMOS Device PhysicsPMOS Device Physics CMOS InverterCMOS Inverter
MOSFET MOSFET = “Metal-Oxide-Semiconductor
Field-Effect Transistor”
Terminals: G = gate D = drain S = source B = body (substrate)
D
G B
S
IDn
VGS
VDS+
-
VBS
+
-
+
-
n-channel device
MOSFET Key Quantities Currents:
IG = 0 (due to insulating oxide layer) ID
IS
=> since IG = 0, ID = IS (Kirchhoff’s Current Law) Voltages:
VG
VD
VS = 0 (usually) VB = 0 (usually)
Most important quantities: ID, VGS, VDS
MOSFET Cross-Section
S VG
oxide
VD > 0
n+ n+ID
ID
L
p-type Si
cross-sectional view (not to scale)
G
D S
top view (not to scale)
Biasing1) Source and substrate grounded (zero voltage)
2) (+) voltage on the gate Attracts e-s to Si/SiO2 interface
When threshold voltage (VGS = VTn) is reached, an inversion layer is formed
3) (+) voltage on the drain e-s in the channel drift from source to drain current flows from drain to source
I-V Characteristics IIDnDn vs. V vs. VGSGS::
VVTnTn = “threshold voltage” = “threshold voltage” Voltage where Si/SiOVoltage where Si/SiO22 interface becomes strongly interface becomes strongly
inverted with electronsinverted with electrons Voltage were NMOS transistor “turns on”Voltage were NMOS transistor “turns on”
VGSVTn
IDn
I-V Characteristics (cont.) IIDnDn vs. V vs. VDSDS::
VGS increasing
VGS = 0V
VDS
IDn (2)
(1)
Linear Region Labeled “(1)” on previous plotLabeled “(1)” on previous plot IIDnDn = f(V = f(VGSGS, V, VDSDS) and V) and VDSDS < V < VGSGS – V – VTnTn, V, VGSGS ≥ V≥ VTnTn
Equation:Equation:
where: n = electron mobility in the channel, Cox = ox/tox, tox = oxide thickness, ox = oxide
permittivity (3.90 for SiO2)
2)(
2DS
DSTnGSoxn
Dn
VVVV
L
CWI
Saturation Region
Labeled “(2)” on the previous plotLabeled “(2)” on the previous plot IIDnsatDnsat = f(V = f(VGSGS) and V) and VDSDS ≥≥ V VGSGS – V – VTnTn, V, VGSGS ≥ V≥ VTnTn
Equation:Equation:
2
2 TnGSoxn
Dnsat VVL
CWI
Transconductance
In the saturation region:In the saturation region:
where: “Q” represents the quiescent operating point (i.e., fixed DC values of VGS, VDS)
DnoxnTnGSoxn
QGS
Dmn IC
L
WVVC
L
W
v
ig
2)(
Outline
NMOS Device PhysicsNMOS Device Physics PMOS Device PhysicsPMOS Device Physics CMOS InverterCMOS Inverter
Circuit Symbol
S
G B
D
-IDp
VSD
+
-
VSG
+
-
VSB
+
-
p-channel device
Cross-Section
Appropriate I-V equations found by:
1) reversing the direction of ID
2) reversing the polarity of all bias voltages (VBS => VSB, VGS => VSG, VDS => VSD)
S VSG
oxide
VSD > 0
p+ p+IDp
ID
L
n-type Si
Biasing1) Source and substrate grounded (zero voltage)
2) (-) voltage on the gate Attracts h+s to Si/SiO2 interface
When threshold voltage (VSG = -VTp) is reached, an inversion layer is formed
3) (-) voltage on the drain h+s in the channel drift from source to drain current flows from source to drain
Currents
Linear: VLinear: VSDSD ≤≤ V VSGSG + V + VTpTp, V, VSGSG ≥ -V≥ -VTpTp
2)(
2SD
SDTpSGoxp
Dp
VVVV
L
CWI
Saturation: VVSDSD ≥ V ≥ VSGSG + V + VTpTp, V, VSGSG ≥ -V ≥ -VTpTp
22 TpSG
oxpDpsat VV
L
CWI
Transconductance
In the saturation region:In the saturation region:
)(2)( DpoxpTpSGoxp
QSG
Dmp IC
L
WVVC
L
W
v
ig
Outline
NMOS Device PhysicsNMOS Device Physics PMOS Device PhysicsPMOS Device Physics CMOS InverterCMOS Inverter
Inverter Logic
Logic symbol:
Function:
Truth table: AA YY
00 11
11 00
A Y
AY
Ideal Voltage Transfer Characteristic
V+ = supply voltageVM = V+/2 = switching point of inverter (where input
voltage = output voltage)
Actual Transfer Characteristic
Voltage Definitions VIL = input voltage where slope of transfer characteristic is
-1 VIH = larger input voltage where slope of transfer
characteristic is -1 VOH = output voltage at input voltage of VIL
VOL = output voltage at input voltage of VIH
VM = voltage where output voltage equals input voltage VMAX = output voltage when input voltage is zero (usually
VMAX = V+) VMIN = output voltage when input voltage is V+ (usually
VMIN ~ 0)
Voltage Definitions (cont.)
VOH = minimum output voltage for valid logic 1
VOL = maximum output voltage for valid logic 0
VIH = minimum input voltage for valid logic 0
VIL = maximum input voltage for valid logic 1
Noise Margins Noise = unwanted variations in voltage which, if too
great, can cause logic errors Noise margin high (NMH): tolerable voltage range for
which we interpret the inverter output as a logic 1
NMH = VOH – VIH
Noise margin low (NML): tolerable voltage range for which we interpret the inverter output as a logic 0
NML = VIL - VOL
Switch Representation
Switching Dynamics
Input high: turn on bottom switch and discharge capacitive loadPMOS offNMOS on (linear)
Input low: turn on the top switch and charge capacitive loadPMOS on (linear)NMOS off
VTC: Another Look
(1) Input voltage = 0 V, output voltage = VDD
(2) NMOS saturated, PMOS linear
(3) Both transistors saturated
(4) NMOS linear, PMOS saturated
(5) Input voltage = VDD, output voltage = 0 V
Approximate VTC
VOH = VMAX; VOL = VMIN
VM is input voltage where VOUT =VIN = VM
Currents
NMOS current at VIN = VM is:
PMOS current at VIN = VM is:
2
2
1TnMoxn
nDn VVC
L
WI
22
1TpMDDoxp
pDp VVVC
L
WI
Deriving VM
Define: Define:
and and
Setting ISetting IDnDn = -I = -IDpDp gives: gives:
oxnn
n CL
Wk
oxpp
p CL
Wk
n
p
TpDDn
pTn
M
k
k
VVk
kV
V
1
)(
Computing Noise Margins
To compute noise margins, the next step is to calculate VIL and VIH
Do so by determining the slope of the transfer characteristic at VIN = VM (i.e., voltage gain)
Then: Project a line to intersect at VOUT = VMIN = 0 V
to find VIH
Project a line to intersect at VOUT = VMAX = VDD to find VIL
Voltage Gain Voltage gain can be shown to be:
where: ron and rop are output resistances of the NMOS and PMOS transistors, respectively
In general: and
We can find ro by inverting the slope of the ID vs. VDS characteristic
)||)(( oponmpmnin
outv rrgg
v
vA
oo g
r1
QDS
Do v
ig
Noise Margins We can find VIL and VIH using the slope (Av) of
the VTC:
Noise margins:
v
MDDMIL A
VVVV
)(
vMMIH AVVV /
vMDDMOLILL AVVVVVNM /)(
vMMDDIHOHH AVVVVVNM /