microelectronics notes

7/23/2019 Microelectronics notes

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The electronics industry has achieved aphenomenal growth over the last two decades,mainly due to the rapid advances in integrationtechnologies, large-scale systems design - inshort, due to the advent of VLSI. The number ofapplications of integrated circuits in high-performance computing, telecommunications, andconsumer electronics has been rising steadily,and at a very fast pace. Typically, the required

computational power (or, in other words, theintelligence) of these applications is the drivingforce for the fast development of this field.

The current leading-edge technologies (such aslow bit-rate video and cellular communications)already provide the end-users a certain amount ofprocessing power and portability. This trend isexpected to continue, with very importantimplications on VLSI and systems design. One ofthe most important characteristics of informationservices is their increasing need for very high

processing power and bandwidth (in order tohandle real-time video, for example). The otherimportant characteristic is that the informationservices tend to become more and morepersonalized (as opposed to collective servicessuch as broadcasting), which means that thedevices must be more intelligent to answerindividual demands, and at the same time theymust be portable to allow more flexibility/mobility.

As more and more complex functions are requiredin various data processing and

telecommunications devices, the need to integratethese functions in a small system/packageis alsoincreasing. The levels of integration, as measuredby the number of logic gates in a monolithic chip,has been steadily rising for almost three decades,mainly due to the rapid progress in processingtechnology and interconnecttechnology.

The graph shown below depicts the growth in thetransistor count in various microprocessors overthe last few decades.

The logic complexity per chip has been (and stilis) increasing exponentially. This is referred to asthe Moores law. In 1965, Gordon Moore notedthat the number of transistors on a chip doubledevery 18 to 24 months. He made a prediction thatsemiconductor technology will double itseffectiveness every 18 months.

When comparing the integration density ointegrated circuits, a clear distinction must bemade between the memorychips and logicchips.

In terms of transistor count, logic chips containsignificantly fewer transistors in any given yearmainly due to large consumption of chip area forcomplex interconnects. Memory circuits are highlyregular and thus more cells can be integrated withmuch less area for interconnects.

Generally speaking, logic chips such as

microprocessor chips and digital signaprocessing (DSP) chips contain not only largearrays of memory (SRAM) cells, but also manydifferent functional units. As a result, their designcomplexity is considered much higher than that ofmemory chips, although advanced memory chipscontain some sophisticated logic functions.

The design complexity of logic chips increasesalmost exponentially with the number oftransistors to be integrated. This is translated intothe increase in the design cycle time, which is the

time period from the start of the chip developmentuntil the mask-tape delivery time. However, inorder to make the best use of the currenttechnology, the chip development time has to beshort enough to allow the maturing of chipmanufacturing and timely delivery to customers.

As a result, the level of actual logic integrationtends to fall short of the integration leveachievable with the current processingtechnology. Sophisticated computer-aided design(CAD) tools and methodologies are developed

and applied in order to manage the rapidlyincreasing design complexity.

Another defining criterion for integrated circuits isthe operating frequency. The plot shown on thenext page gives the frequency of signals that areused in most signal processing applications today

EL - 313 (Microelectronics) UNIT - 1

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To address any particular application area, atechnology that can support the required signalbandwidth must be used. Bandwidth requirementsand speed are not the only considerations whendeciding which technology to use for anIntegrated Circuit addressing a particularapplication area. Other considerations are costand integration density.

The frequencies that can be processed bymodern day technologies are given in a separateplot below.

The two most prevalent integrate-circuittechnologies are bipolar and MOS. Within thesefamilies are various subgroups as illustrated in the

chart shown.

For many years the dominant silicon ICtechnology was bipolar, as evidenced by theubiquitous monolithic operational amplifier and theTTL family. In the early 1970s MOS technologywas demonstrated to be viable in the area ofdynamic random access memoriesmicroprocessors and the series-4000 logic family.

The clear trend today is to use CMOS digitacombined with CMOS analog (as needed)whenever possible because significant integrationcan be achieved, thus providing highly reliablecompact system solutions.

Advan tages of ICs

The monolithic integration of a large number offunctions on a single chip usually provides:

Less area/volume and therefore

compactness Less power consumption Less testing requirements at system level Higher reliability, mainly due to improved

on-chip interconnects Higher speed, due to significantly reduced

interconnection length Significant cost savings

Disadvantages (are there any?!)

Non-repairable

The support chips that are needed fomaking up a complete system need to befrom the same logic family, otherwise amismatch of operating voltage and currentlevels occurs.

Cost of Integrated Circuits

NRE (non-recurrent engineering) costs design time and effort, mask

generation one-timefabsetup factor

Recurrent costs silicon processing, packaging, testing

proportional to volume

proportional to chip area

Sources:

o www.vlsi.wpi.edu/webcourse

o Digital Integrated Circuits: A DesignPerspective (II Ed.) by Rabaey

o CMOS Analog Circuit Design by Allen &Holberg


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http://www.vlsi.wpi.edu/webcoursehttp://www.vlsi.wpi.edu/webcourse


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In this part of the lecture, the fundamentals ofMOSchip fabrication will be discussed and themajor steps of the process flow will beexamined. The aim is NOT to present adetailed discussion of silicon fabricationtechnology. Rather, the emphasis will be onthe general outline of the process flow and onthe interaction of various processing steps,which ultimately determine the device and thecircuit performance characteristics.

1. A large scale drawing of the entire circuitryfor a single chip is produced. From this, aseries of glass photo-masks is made. Eachone defines the minute areas for the type ofdoping required and also the interconnection.

An insulating film of silicon dioxide is formedon the wafer, which is then covered by a light-sensitive material called photo-resist.

2. A photo-mask is placed over the photo-

resist and subjected to ultra-violet light whichexposes the areas not shielded by the mask.The wafer is developedand selected areas ofthe silicon oxide are removed.

3. The wafer is then placed into an oxidationfurnace and a thin oxide (the gate oxide) isgrown to cover the etched region.

4. A layer of poly-crystalline silicon isdeposited all over the wafer. This layer is then

patterned and etched to form, in this example,the gate of the transistor.

5. A n-type dopant is introduced into theopened regions and diffusedinto the wafers.

6. A layer of LPCVD (low pressure chemicalvapor deposition) oxide is deposited over thewafer and contact windows opened to thetransistor.

7. A layer of aluminum is deposited all over thewafer and patterned and etched to form theinterconnecting layers and the connections tothe transistor. This step is referred to asMetallization.

This forms a simple n-channel Metal OxideSemiconductor Transistor which is one of thebasic functional elements of a modernelectronic circuit.

Source: www.microlab.ch/courses/cbt/cbt-vlsi


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Like anything else in this world, crystalsinherently possess imperfections, or what we

often refer to as 'crystalline defects'

. The

presence of most of these crystalline defects isundesirable in silicon wafers, although certaintypes of 'defects' are essential insemiconductor manufacturing. Crystallinedefects may be classified into four categories

according to their geometry. These categoriesare: 1) zero-dimensional or 'point' defects; 2)one-dimensional or 'line' defects; 3) two-dimensional or 'area' defects; and 4) three-dimensional or 'volume' defects. Table 1presents the commonly encountered defectsunder each of these categories.

More on Crystal Defects in the

Assignments Section

Crystalline Defects

Defect Type Examples

Point or Zero-Dimensional Defects

Vacancy Defects

InterstitialDefects

Frenkel Defects

Extrinsic Defects

Line or One-Dimensional Defects

StraightDislocations(edge or screw)

DislocationLoops

Area or Two-Dimensional Defects

Stacking Faults

Twins

GrainBoundaries

Volume or Three-Dimensional Defects

Precipitates

Voids

A defect wherein a silicon atom is missing fromone of these sites is known as a 'vacancy'defect. If an atom is located in a non-lattice sitewithin the crystal, then it is said to be an

'interstitial' defect. If the interstitial defectinvolves a silicon atom at an interstitial site withina silicon crystal, then it is referred to as a 'self-interstitial' defect. Vacancies and self-interstitialdefects are classified as intrinsic point defects.

If an atom leaves its site in the lattice(thereby creating a vacancy) and then moves tothe surface of the crystal, then it becomes a'Schottky' defect. On the other hand, an atomthat vacates its position in the lattice andtransfers to an interstitial position in the crystal is

known as a 'Frenkel' defect. The formation of aFrenkel defect therefore produces two defectswithin the lattice - a vacancy and the interstitialdefect, while the formation of a Schottky defectleaves only one defect within the lattice, i.e., avacancy.

Extrinsic point defects, which are point defectsinvolving foreign atoms, are even more critical

than intrinsic point defects. When a non-siliconatom moves into a lattice site normally occupiedby a silicon atom, then it becomes a'substitutional impurity.' If a non-silicon atomoccupies a non-lattice site, then it is referred toas an 'interstitial impurity.' Foreign atomsinvolved in the formation of extrinsic defectsusually come from dopants, oxygen, carbon, andmetals. The presence of point defects isimportant in the kinetics of diffusion andoxidation. The rate at which diffusion of dopantsoccurs is dependent on the concentration of

vacancies. This is also true for oxidation ofsilicon.

Crystal line defects are also known as'dislocations', which can be classified as one ofthe following: 1) edge dislocation; 2) screwdislocation; or 3) mixed dislocation, whichcontains both edge and screw dislocationcomponents.

An edge dislocation may be described as anextra plane of atoms squeezed into a part of thecrystal lattice, resulting in that part of the lattice

containing extra atoms and the rest of the latticecontaining the correct number of atoms. The partwith extra atoms would therefore be undercompressive stresses, while the part with thecorrect number of atoms would be under tensilestresses. The dislocation line of an edgedislocation is the line connecting all the atoms atthe endof the extra plane.

Fig.1 Fig.2

Fig. 1 shows an edge dislocation; note theinsertion of atoms in the upper part of thelattice. Figure 2 shows screw dislocation; notethe screw-like 'slip' of atoms in the upper partof the lattice.


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If the dislocation is such that a step or ramp isformed by the displacement of atoms in aplane in the crystal, then it is referred to as a'screw dislocation.' The screw basically formsthe boundary between the slipped andunslipped atoms in the crystal. If thedislocation consists of an extra plane of atoms(or a missing plane of atoms) lying entirelywithin the crystal, then the dislocation is known

as a 'dislocation loop.' The dislocation line of adislocation loop forms a closed curve that isusually circular in shape, since this shaperesults in the lowest dislocation energy. Thedislocation line of a screw dislocation is theaxis of the screw.

Dislocations are generally undesirable insilicon wafers because they serve as sinks formetallic impurities as well as disrupt diffusionprofiles. However, the ability of dislocations tosink impurities may be engineered into a wafer

fabrication advantage. i.e., it may be used inthe removal of impurities from the wafer, atechnique known as 'gettering.'

Area defects in crystals consist of stackingfaults, grain boundaries, and twin boundaries.

A 'stacking fault' pertains to a disturbance inthe regularity of the stacking of planes ofatoms in a crystal lattice. This usually occurswhen a plane is inserted into or removed fromthe lattice. The insertion of an extra plane inthe stacking is known as an 'extrinsic' stacking

fault, while the removal of a plane is referred toas an 'intrinsic' stacking fault. Stacking faultscan become electrically active when decoratedby impurity atoms. Electrically active stackingfaults can cause device degradation, examplesof which are higher reverse bias currents in p-n

junctions and storage time reduction in MOScircuits.

A 'twin' is an area defect wherein a mirrorimage of the regular lattice is formed during thegrowth of the silicon ingot, usually caused by a

perturbation. The'twin boundary' is the mirrorplane of the twin formation.

A grain boundary' refers to the transition orinterface between crystals whose atomicarrangements are different in orientation withrespect to each other.

Volume defects in a crystal are also known as'bulk' defects, which include voids and

precipitates of extrinsic and intrinsic pointdefects.

Every impurity introduced into a crystal has acertain level of solubility, which defines theconcentration of that impurity that the solidsolution of the host crystal can accommodate.Impurity solubility usually decreases withdecreasing temperature. If an impurity is

introduced into a crystal at the maximumconcentration allowed by its solubility at a hightemperature, the crystal will becomesupersaturatedwith that impurity once it is cooleddown. A crystal under such supersaturatedconditions seeks and achieves equilibrium byprecipitating the excess impurity atoms intoanother phase of different composition orstructure.

Precipitatesare considered undesirable becausethey have been known to act as sites for the

generation of dislocations. Dislocations arise asa means of relieving stress generated by thestrain exerted by precipitates on the lattice.Precipitates induced during silicon waferprocessing come from oxygen, metallicimpurities, and dopants like boron.

Single Crystal Growing for Wafer Production

Integrated circuits are built on single-crystalsilicon substrates that possess a high level of

purity and perfection. Single-crystal silicon isused in VLSI fabrication instead of polycrystallinesilicon since the former does not have defectsassociated with grain boundaries found inpolysilicon. Such defects have been known tolimit the lifetimes of minority carriers. Asidefrom the need to be single-crystalline in nature,silicon substrates must also have a high degreeof chemical purity, a high degree of crystallineperfection, and high structure uniformity.

The acquisition of such high-grade starting silicon

material involves two major steps:

1) Refinement of raw material (such as quartzite,a type of sand) into electronic gradepolycrystalline silicon (EGS) using a complexmulti-stage process;

and

2) Growing of single-crystal silicon from this EGSeither by Czochralski or Float Zone process.


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Czochralski Crystal Growth

Named in honor of its inventor, it involves thecrystalline solidification of atoms from a liquidphase at an interface. The basic CZ crystalgrowing process is more or less still the sameas what has been developed in the 1950's.

CZ crystal growing consists of the followingsteps:

1) A fused silica crucible is loaded with acharge of undoped EGS together with aprecise amount of diluted silicon alloy.2) The gases inside the growth chamber arethen evacuated.3) The growth chamber is then back-filledwithan inert gas to inhibit the entrance ofatmospheric gases into the melt during crystalgrowing.4) The silicon charge inside the chamber isthen melted(Si melting point = 1421 deg C).

5) A slim seed of crystal silicon (5 mm dia. and100-300 mm long) with precise orientationtolerances is introduced into the molten silicon.6) The seed crystal is then withdrawn at a verycontrolled rate. The seed crystal and thecrucible are rotated in opposite directions whilethis withdrawal process occurs.

More on the Czochralski Crystal Growth

Process in the Assignments Section

Float Zone Crystal Growth

It involves the passing of a molten zonethrough a polysilicon rod that approximatelyhas the same dimensions as the final ingot.The purity of an ingot produced by the FZprocess is higher than that of an ingotproduced by the CZ process. As such, devicesthat require ultra pure starting silicon

substrates should use wafers produced usingthe FZ method.

This process consists of the following steps:.1. A polysilicon rod is mounted verticallyinside a chamber, which may be undervacuum or filled with an inert gas.2. A needle-eye coil that can run through therod is activated to provide RF power to the rod,melting a 2-cm long zone in the rod. Thismolten zone can be maintained in stable liquid

form by the coil.3. The coil is then moved through the rod, andthe molten zonemoves along with it.4. The movement of the molten zone throughthe entire length of the rod purifies the rod andforms the near-perfect single crystal.

After the single-crystal silicon ingot hasbeen manufactured, it undergoes a routineevaluation of its resistivity, impurity content,crystal perfection, size and weight. It is thenground using diamond wheels to make it aperfect cylinder. It then undergoes an etching

process to remove the mechanicalimperfections left by the grindingprocess.The cylindrical ingot is then given one or more'flats' by another round of grinding. The largestflat, called the primary flat, is used byautomated wafer handling systems foralignment. Flats (primary and secondary) arealso used to identify the crystallographicorientationand conductivityof the wafer.

The ingot is then sawn into thin waferslices, each of which will be subjected to

further etchingand polishinguntil it is ready foruse as substrates for VLSI fabrication. Theabove process of silicon growing, grinding,shaping, sawing, etching, and polishing toproduce input wafers is known as wafering.

Source: www.semiconfareast.com


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Single crystalline silicon wafers are manufactured from rawpolysilicon for use as substrates for the varioussemiconductor devices. The integrated circuits are thenmanufactured by repeatedly processing the substratesthrough a cycle of three basic operations: film deposition,lithography, and etch. This cycle builds up the patternedlayers (semiconductors, conductors, and insulators) requiredto make a final device. The manufacture of semiconductorproducts requires the ability to work selectively on small,well-defined areas of the semiconductor substrate. Theprocess by which these well-defined areas are patterned is

again known as the microlithographic process. The basicsteps in the lithographic process are shown in the figurebelow.

The first step in the process is the preparation of thesubstrate. This step usually involves cleaning the surface

through various solvent and plasma cleaning procedures.The surface may also be treated using a prime step, in whichit is exposed to a reagent, such as hexamethyldisilizane(HMDS), that modifies the surface chemistry of the substrateto improve the adhesion of the photoresist to the surface.

In the next step, a material known as a photoresistis applied.The photoresist is a material that undergoes a change in itsphysical and/or chemical properties upon exposure toradiation that allows for the formation of a relief pattern in thematerial. The resist, in the form of a solution in an organicsolvent, is spin coated onto the substrate and then soft baked(SB) on a hot plate or in an oven to remove residual castingsolvent. The desired product from this step is a uniform,glassy, polymeric thin film that is generally on the order of 1

mm thick. The resist coated substrate is then exposedpattern-wise to radiation, typically ultraviolet light. Theexposuretool uses a mask to selectively expose the desiredpattern into photoresist. The resist is then treated with adeveloping solvent which selectively dissolves either theexposed or unexposed areas depending on the nature of theresist.

During development, the unwanted areas in the PR aredissolved by the developer. In the case wherein the exposedareas become soluble in the developer, a positive image ofthe mask pattern is produced on the resist. Such a resist istherefore called a positivephotoresist. Negativephotoresist

layers result in negative images of the mask pattern, whereinthe exposed areas are made soluble in the developer. Wafefabrication may employ both positive and negativephotoresists, although positive resists are preferred becausethey offer higher resolution capabilities.

Photoresist materials consist of three components: 1) amatrix material (also known as resin), which provides bodyfor the photoresist; 2) the inhibitor (also referred to assensitizer), which is the photoactive ingredient; and 3) the

solvent, which keeps the resist liquid until it is applied to thesubstrate.

The areas of the substrate that are no longer covered byphotoresist can then subjected to further processing such asplasma etching or ion implantation. The remaining resispatterns serve as a barrier that protects the underlyingsubstrate from these processes. Once the substrate isprocessed, the photoresist layer is stripped and the entireprocess is repeated for each layer of the device.

Etchingis the process of removing regions of the underlyingmaterial that are no longer protected by photoresist afterdevelopment. The etching process is said to be isotropicif iproceeds in all directions at the same rate. If it proceeds inonly one direction, then it is completely anisotropic. Sinceetching processes generally fall between being completelyisotropic and completely anisotropic, an etching processneeds to be described in terms of its level of isotropy. Weetching, or etching with the use of chemicals, is generallyisotropic. On the other hand, dry etching processes thaemploy reactive plasmas are generally anisotropic.

Reactive plasma etching involves the removal of surfacematerial not protected by lithographic masks using chemicallyactive species. These species are usually oxidizing andreducing agents produced from process gases that havebeen ionized and fragmentized by a glow discharge. Thespecies react with the exposed surface material, removing

them from the substrate while forming volatile byproducts inthe process.

The reduction in the minimum feature sizesin semiconductodevices has been made possible over the years by acontinuous progression of advancements in the lithographictechnologies used to pattern the devices. One of the mainways to reduce the device critical dimensions has been tocontinually reduce the wavelength of the radiation used toexpose the photoresist. The resolutionof a diffraction limitedlithographic process is given by the Raleigh criterion.

Resolution = (*k) / NAwhere is the wavelength of radiation used, NA is thenumerical aperture of the lens in the exposure system, and

k is a process dependent adjustment factor. The k factor iscontrolled by a variety of things including the photoresisperformance and tool issues such as lens aberrations.

Source: http://dot.che.gatech.edu/henderson &www.semiconfareast.com


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OpticalLithographyrefers to a lithographic process thatuses visible or ultraviolet light to form patterns on thephotoresist through printing. Printing is the process ofprojecting the image of the patterns onto the wafersurface using a light source and a photo mask. Thereare three types of printing - contact, proximity, andprojection printing, each of which will be describedbelow. Equipments used for printing are known asprintersor aligners.

Patterned masks, usually composed of glass or

chromium, are used during printing to cover areas of thephotoresist layer that shouldn't get exposed to light.Development of the photoresist in a developer solutionafter its exposure to light produces a resist pattern on thewafer, which defines which areas of the wafer areexposed for material deposition or removal.

As discussed in the last lecture, there are two types ofphotoresist material, namely, negative and positivephotoresist. Commercial negative photoresists normallyconsist of two parts: 1) a chemically inert polyisoprenerubber; and 2) a photoactive agent. When exposed tolight, the photoactive agent reacts with the rubber,promoting cross-linking between the rubber moleculesthat make them less soluble in the developer. Suchcross-linking is inhibited by oxygen, so this light exposureprocess is usually done in a nitrogen atmosphere.

Positive resists also have two major components: 1) aresin; and 2) a photoactive compound dissolved in asolvent. The photoactive compound in its initial state isan inhibitor of dissolution. Once this photoactivedissolution inhibitor is destroyed by light, however, theresin becomes soluble in the developer.

A disadvantage of negative resists is the fact that theirexposed portions swell as their unexposed areas aredissolved by the developer. This swelling, which issimply volume increase due to the penetration of the

developer solution into the resist material, results indistortions in the pattern features. This swellingphenomenon limits the resolution of negative resistprocesses. The unexposed regions of positive resists donot exhibit swelling and distortions to the same extent asthe exposed regions of negative resists. This allowspositive resists to attain better image resolution.

Contact printing refers to the light exposure processwherein the photomask is pressed against the resist-covered wafer with a certain degree of pressure. Thispressure is typically in the range of 0.05-0.3atmospheres. Light with a wavelength of about 400 nm isused in contact printing. Contact printing is capable ofattaining resolutions of less than 1 micron. However, the

presence of contact between the mask and the resistsomewhat diminishes the uniformity of attainableresolution across the wafer. To alleviate this problem,masks used in contact printing must be thinand flexibleto allow better contact over the whole wafer.

Contact printing also results in defects in both the masksused and the wafers, necessitating the regular disposal ofmasks (whether thick or thin) after a certain level of use.Mask defectsinclude pinholes, scratches, intrusions, andstar fractures. Good contact printing processes canachieve resolutions of 0.25 micron or better.

Proximity printing is another optical lithographytechnique. As its name implies, it involves no contactbetween the mask and the wafer, which is why masksused with this technique have longer useful lives thanthose used in contact printing. During proximity printing,the mask is usually only 20-50 microns away from thewafer. The resolution achieved by proximity printing is notas good as that of contact printing. This is due to thediffraction of light caused by its passing through slits thatmake up the pattern in the mask, and traversal across thegap between the mask and the wafer. This type of

diffraction is known as Fresnel diffraction, or near-fielddiffraction, since it results from a small gapbetween themask and the wafer. Proximity printing resolution may beimproved by diminishing the gap between the mask andthe wafer and by using light of shorter wavelengths.

Projection printingis the third technique used in opticallithography. It also involves no contact between themask and the wafer. In fact, this technique employs alarge gap between the mask and the wafer, such thatFresnel diffraction is no longer involved. Instead, far-fielddiffraction is in effect under this technique, which is alsoknown as Fraunhoferdiffraction.

The projection printing system most used today is step-and-repeat. This method is applied in two ways:reduction and non-reduction. Reduction projectionprinting uses a scaled image typically 5x on thephotomask. One benefit of this method is that defects arereduced by the scale amount. Non-reduction systems donot have this benefit and thus greater burden for lowdefect densities is placed on the manufacture of thephotomask itself.

Projection printers use a well-designed objective lensbetween the mask and the wafer, which collectsdiffracted light from the mask and projects it onto thewafer. The capability of a lens to collect diffracted lightand project this onto the wafer is measured by its

numerical aperture (NA). The NA values of lenses usedin projection printers typically range from 0.16 to 0.40.

Using a lens with a higher NA will result in betterresolution of the image, but this advantage has a price.The depth of focus of a lens is inversely proportional tothe square of the NA, so improving the resolution byincreasing the NA reduces the depth of focus of thesystem. Poor depth of focus will cause some points ofthe wafer to be out of focus, since no wafer surface isperfectly flat. Thus, proper design of any aligner used inprojection printing considers the compromise betweenresolution and depth of focus.

Source: www.semiconfareast.com


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Electron Beam Lithography (EBL) refers to alithographic process that uses a focused beam ofelectrons to form the circuit patterns needed for materialdeposition on (or removal from) the wafer, in contrast withoptical lithography which uses light for the samepurpose. Electron lithography offers higher patterningresolution than optical lithography because of the shorterwavelength possessed by the 10-50 keV electrons that itemploys.

Given the availability of technology that allows a small-

diameter focused beam of electrons to be scanned over asurface, an EBL system doesn't need masks anymore toperform its task (unlike optical lithography, which usesphotomasks to project the patterns). An EBL systemsimply 'draws' the pattern over the resist wafer using theelectron beam as its drawing pen. Thus, EBL systemsproduce the resist pattern in a 'serial' manner, making itslow compared to optical systems.

Direct write EBL systems are the most common EBLsystems. Most direct write systems use a small electronbeam spot that is moved with respect to the wafer toexpose the wafer one pixel at a time. Direct write systemscan be classified as raster scan or vector scan, witheither fixed or variable beam geometry.

A typical EBL system (shown above) consists of thefollowing parts: 1) an electron gun or electron source thatsupplies the electrons; 2) an electron column that'shapes' and focuses the electron beam; 3) a mechanicalstage that positions the wafer under the electron beam;4) a wafer handling system that automatically feeds

wafers to the system and unloads them after processing;and 5) a computer system that controls the equipment.

The resolution of optical lithography is limited bydiffraction, but this is not a problem for electronlithography. The reason for this is the short wavelengths(0.2-0.5 ) exhibited by the electrons in the energy rangethat they are being used by EBL systems. However, theresolution of an electron lithography system may beconstrained by other factors, such as electron scatteringin the resist and by various aberrations in its electron

optics.

Just like optical lithography, electron lithography alsousespositive and negative resists, which in this case arereferred to as electron beam resists (or e-beam resists).Positive electron resists produce an image that is thesame as the pattern drawn by the e-beam (positiveimage), while negative ones produce the reverse imageof the pattern drawn (negative image). Positive resistsundergo bond breaking when exposed to electronbombardment, while negative resists form bonds orcross-links between polymer chains under the samesituation.

As a result, areas of the positive resist that are exposedto electrons become more soluble in the developersolution, while the exposed areas of the negative resistbecome less soluble. This is the reason why positiveresists form positive images - because its electron-exposed areas will result in exposed areas on the waferafter they've dissolved in the developer. In the case ofnegative resists, the electron-exposed areas will becomethe unexposed areas on the wafer, forming a negativeimage.

The resolution achievable with any resist is limited by twomajor factors: 1) the tendency of the resist to swell in thedeveloper solution and 2) electron scattering within theresist.

Resist swelling occurs as the developer penetrates theresist material. The resulting increase in volume candistort the pattern, to the point that some adjacent linesthat are not supposed to touch become in contact witheach other.

When electrons strike a material, they penetrate thematerial and lose energy from atomic collisions. Thesecollisions can cause the striking electrons to 'scatter'. Thescattering of electrons may be backward (or back-scattering, wherein electrons 'bounce' back), but it isoften forward through small angles with respect to theoriginal path. During electron beam lithography,scattering occurs as the electron beam interacts with theresist and substrate atoms. This electron scattering has

two major effects: 1) it broadens the diameter of theincident electron beam as it penetrates the resist andsubstrate (and thus closely-spaced adjacent lines can'add' electron exposure to each other, a phenomenonknown as 'proximity effect); and 2) it gives the resistunintended extra doses of electron exposure as back-scattered electrons from the substrate bounce back to theresist.

Source: www.semiconfareast.com &http://dot.che.gatech.edu/henderson


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The X-rays were discovered exactly 111 years ago, in1895 by W.C. Roentgen, while experimenting on thenature of cathodic rays. The applications of X-rays tomedicine and industrial inspection are well known, butwhy is this radiation of interest in lithography? In short,because of its ability to define very high resolutionimages in thick materials. The resolution comes fromthe extremely short wavelength, of the order of 0.01-1.0 nm, and the high penetration ability, arising fromthe transparency of most materials in this region of thespectrum. Large scale integrated circuits exposed withX-ray Lithography have been demonstrated repeatedly,and masks with resolution approaching 0.14 moverthe field and with adequate placement accuracy arebeginning to be available.

In X-ray Lithography (XRL), and more generally inprojection lithography, we may distinguish fourelements. The light source, the mask or reticle, whichcarries the pattern to be transferred, the imagingsystem and a storage medium, typically a thin film ofresist deposited over the surface of the wafer. Thefigure illustrates a general X-ray Lithography layout.

A shadow of the mask pattern is cast onto the resistsurface by the source radiation. A well establishedsource for XRL is synchrotron radiation.

X-ray mask: A device for delineating the areas of awafer which should be exposed to x-rays during theexposure stage of x-ray lithography. The x-rayabsorber is usually gold (Au). There is not yet astandard substrate material for x-ray masks, though

the most promising is a combination of boron nitrideand polyimide.

Advantages:

Fastprocess

High resolutionsof ~ .5 m

Not affected by organic defectsin mask

Reduction in diffraction, reflection, andscattering effects

Solves depth of focusproblem

High aspect ratio

Disadvantages:

Shadow printing: A geometric effect whichoccurs in lithography methods involving amask. If the exposing radiation cannot betightly focused, then a small zone of "shadow"is created at the edges of surface featureswhich are only partially exposed. This effectcalled the penumbral effect reduces the

attainable resolution of such lithographysystems. As shown in the figure below, thepenumbral blur, , on the edge of the resisimage is given by:

= a*g / L

where a is the diameter of the x-ray source, gis the gap spacing, and L is the distance fromthe source to the x-ray mask. If a = 3 mm, g =40 m, and L = 50 cm, is on the order of 0.2m.

Lateral magnification error: As the radiationsource is concentrated in a single point, andthe mask is separated from the substrate, theangle at which the radiation passes throughthe mask differs. In the center of the wafer, theradiation is perpendicular to the wafer, but outowards the edges of the wafer the angle isacute. Therefore, a general enlargementof thefeatures takes place, with features further ou

from the center being enlarged more thanfeatures closer in.

Brighter x-ray sourcesneeded

More sensitiveresistsneeded

Difficult fabricationof x-ray mask

Sources: www.ee.pdx.edu/~jeske/litho& www.xraylith.wisc.edu


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Ion Beam Lithography

This is a variation of the electron beamlithography technique, using a focused ionbeam(FIB) instead of an electron beam. . TheFIB system consists of an ion source, a beamdefining aperture, and electrostatic lens forfocusing the beam. Higher resolution limitsshould be obtainable because resists are more

sensitive to the higher mass of ions overelectrons, and the higher mass of ions are lessprone to backscattering which is one of thelimitations in e-beam lithography. The FIBsystem is characterized by the spot size (thediameter of the beam), current, field size (thearea that can be patterned at a time), andwriting speed.

Coulombic interaction (Ions of the samecharge repel each other when brought tooclose to one another and thus, a limit exists as

to how dense an ion beam can be) betweenions limits the current and throughput.

A parallel system can be pursued to ensurethat the lithography process can be maskless.Elimination of the mask allows finer geometriesto be patterned. All the defects and shadowingfrom the mask are eliminated.

In a similar setup to scanning electronmicroscopes, an ion beam scans across thesubstrate surface and exposes electron

sensitive coating. A grid of pixels issuperimposed on the substrate surface, eachpixel having a unique address. The patterndata (data describing the circuit layout) istransferred to the controlling computer, whichthen directs the electron beam as to realize thepattern on the substrate pixel by pixel.

The ion beam used is either a Gaussian roundbeam (a circular beam that normally has adiameter equal to one-fourth of the smallestpattern dimension) or Variable Shaped Beam

(VSB- Two square apertures are used to sizea rectangle appropriate for the current feature).

There are two methods of scanning the beamover the substrate surface to write the patterndata. With raster scan, the electron beam isscanned across lines of pixels and the wafer isshifted to the next line. With vector scan, anarea of an individual chip is selected, and thebeam draws out the features in that area one-by-one.

The most important application of ionlithography is the repair of masksfor optical orx-ray lithography, a task for which commercialsystems are available.

Advan tages:

Computer-controlledbeam

No mask is needed

Can produce sub-1 m features(Of all thetypes of particles -- photons, electrons,ions -- which are employed in lithography,ions have the shortest effectivewavelength, and hence, in principle theyachieve the smallest features.)

Resists are more sensitive than electronbeam resists

Diffraction effectsare minimized

Less backscattering occurs

Higher resolution Ion beam can detect surface features for

very accurate registration

Disadvantages:

Reliable ionsourcesneeded

Swellingoccurs when developing negativeion beam resists, limiting resolution

Expensiveas compared to light lithographysystems

Slower as compared to light lithographysystems

Sources: www.xraylith.wisc.eduhttp://enews.lbl.gov &

www.eecs.berkeley.edu/~tking/ibl.htm


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Etching removes layers of SiO , metals, andpolysilicon, according to the desired patternsdelineated by the resist.

2

The objective of etching is to remove just the sectionof the exposed film. To achieve this, the etchingprocess must have two important properties:selectivity & anisotropy.

Selectivityis the characteristic of the etch whereby

only the desired layer is etched with no effect oneither the protective layer (masking layer) or theunderlying layer. Selectivity can be quantified as theratio of the desired layer etch rate to the undesiredlayer etch rate as given below:

Anisotropy is the property of the etch to manifestitself in one direction; that is a perfectly anisotropicetchant will etch in one direction ONLY. The degree ofanisotropy can be quantified as:

Reality is such that neither perfect selectivity norperfect anisotropy can be achieved in practice,resulting in undercutting effects and partial removalof the underlying layer as shown in the figure below.As illustrated, the lack of selectivity with respect tothe mask is given by dimension a. Lack of selectivitywith respect to the underlying layer is given bydimension b. Dimension c shows the degree ofanisotropy.

There are preferential etching techniques thatachieve high degree of anisotropy and thus minimizeundercutting effects, as well as maintain highselectivity. Materials that are normally etched includepolysilicon, silicon dioxide, silicon nitride andaluminum.

The two major methods of etching are wetchemicaetching and drychemical etching. In general:

1. Wet etching is one where the material isdissolved when immersed in a chemicasolution.

2. Dry etching occurs when the material issputtered or dissolved using reactive ions ora vapor phase etchant.

Wet etching

This is the simplest etching technology. All it requiresis a container with a liquid solution that will dissolvethe material in question. Unfortunately, there arecomplications since usually a mask is desired toselectively etch the material. One must find a maskthat will not dissolve or at least etches much slowerthan the material to be patterned.

Secondly, some single crystal materials, suchas silicon, exhibit anisotropic etching in certainchemicals. Anisotropic etching in contrast to

isotropic etching means different etch-rates indifferent directions in the material.

Isotropic etchantsattack the material being etchedat the same rate in all directions. Anisotropic

etchants attack the silicon wafer at different rates indifferent directions, and so there is more control ofthe shapes produced. Isotropic etchants

are availablefor oxide, nitride, aluminium, polysilicon, gold, andsilicon. Since isotropic etchants attack the material atthe same rate in all directions, they remove materiahorizontally under the etch mask (undercutting) atthe same rate as they etch through the material. Thisis illustrated for a thin film of oxide on a silicon waferin the figure below, using an etchant that etches theoxide faster than the underlying silicon (e.g.hydrofluoric acid).

Mask

Anisotropic etchants are available which etchdifferent crystal planes in silicon at different ratesThe most popular anisotropic etchant is potassiumhydroxide (KOH), since it is the safest to use.

The simplest structures that can be formed usingKOH to etch a silicon wafer with the most commoncrystal orientation (100) are shown in the nextfigure. These are V shaped groves, or pits with rightangled corners and sloping side walls. Using waferswith different crystal orientations can producegrooves or pits with vertical walls.


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When should I use wet etching?

Wet etching will give good results if you can find thecombination of etchant and mask material to suityour application. It works very well for etching thinfilms on substrates, and can also be used to etch thesubstrate itself. The problem with substrate etchingis that isotropic processes will cause undercutting ofthe mask layer by the same distance as the etchdepth.If very small features in thin films (comparable to thefilm thickness) are desired, one may also encounterproblems with isotropic wet etching, since theundercutting will be at least equal to the filmthickness. With dry etching it is possible to etchalmost straight down without undercutting, whichprovides much higher resolution.

Dry etching

The dry etching technology can be divided into threeseparate classes called reactive ionetching (RIE),sputteretching, and vaporphaseetching.

In RIE, the substrate is placed inside a reactor inwhich several gases are introduced. A plasma isstruck in the gas mixture using an RF power source,breaking the gas molecules into ions. The ions areaccelerated towards, and react at, the surface of thematerial being etched, forming another gaseousmaterial. This is known as the chemical part ofreactive ion etching. There is a physical part too,which is similar in nature to the sputteringdeposition process. If the ions have high enoughenergy, they can knock atoms out of the material tobe etched without a chemical reaction. It is a verycomplex task to develop dry etch processes thatbalance chemical and physical etching, since thereare many parameters to adjust.By changing the balance it is possible to influence thedirection of the etching. Since the chemical part isisotropic and the physical part highly anisotropic, thecombination can form sidewalls that have shapesfrom rounded to vertical.

Sputter etching is essentially RIE without reactiveions. In this method, the substrate is subjected to ionbombardment i.e. we physically bombard the films tobe etched with energized chemically inert ions oatoms. Glow discharge is usually used to energizechemically inert ions or atoms (e.g., Ar)This process is most often used to pre-cleansubstrates prior to deposition.This type of etching is highly anisotropic and causesdamage to the underlying material and may result in

changes in device properties. It is used very rarely inVLSI.

Vapor phase etching is another dry etchingmethod, which can be done with simpler equipmenthan what RIE requires. In this process the wafer tobe etched is placed inside a chamber, in which one omore gases are introduced. The material to be etchedis dissolved at the surface in a chemical reaction withthe gas molecules. The two most common vaporphase etching technologies are silicon dioxideetching using hydrogen fluoride (HF) and siliconetchingusing xenon diflouride (XeF2), both of whichare isotropic in nature. Usually, care must be taken in

the design of a vapor phase process to not have bi-products form in the chemical reaction that condenseon the surface and interfere with the etching process.

Another recent etching technique is the Ion BeamMilling. It is a process where ions are driven into thepart being etched at a high speed. When the ionsmake contact, metal particles are then knocked offIon Beam Milling is not selective - it etcheseverything, but at different rates. Gold is one of the

fastest metals to etch (1000/sec).

Ion Beam Milling provides a cleaner etching processthan conventional chemical etching. Some materials

such as Quartz and Platinum cannot be chemicallyetched without affecting other metal layers. Chemicaetching can also introduce cross contaminationwhich degrades overall circuit performance.

Dry etching offers increased yield and reliabilitykeeping rework down. The greatest benefit of dryetching is we can precisely duplicate the photo-resistimage with no under-cut. This allows engineers todesign much tighter lines and spaces for higherfrequency circuits.

When should I use dry etching?

It should be noted that dry etching is expensive ascompared to wet etching. If you are concerned withfeature resolution in thin film structures or you needvertical sidewalls for deep etchings in the substrateyou have to consider dry etching. If you areconcerned about the price of your process anddevice, you may want to minimize the use of dryetching. The IC industry has long since adopted dryetching to achieve small features, but in many casesfeature size is not as critical in MEMS.

Sources: http://www.memsnet.org/memswww.sarnoff.com & www.dbanks.demon.co.uk/ueng


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