design of cmos analog integrated circuitsims.unipv.it/courses/download/dic/presentation03.pdf ·...

F. Maloberti : Design of CMOS Analog Integrated Circuits - “Basic Building Block”

Design of CMOS AnalogIntegrated Circuits

Franco Maloberti

Basic Building Block

F. Maloberti : Design of CMOS Analog Integrated Circuits - “Basic Building Block” 23/

INVERTER WITH ACTIVE LOAD

• The simplest form of gain stage, the DC gain is given by the slope of the curve


Small signal analysis:

C1 = Cgs1 + Cgs1,ov

C2 = Cgd1 + Cgd1,ov

C3 = Cdb1 + Cdb2 + Cgd2 + Cgd2,ov + CL

At low frequency:

Since:

2ds1ds

1m

in

outv gg

gVV

A+

−==

DdsDoxm IgILW

C2g λ=µ=


It results:

• The DC gain increases as the square root of the bias current is decreased. This holds

until the devices enter the subthreshold region.

( )pnD

1ox1

v I

LWC2

Aλ+λ

µ

−=


At high frequency:

• Miller’s theorem is applied to C2

• The output total capacitance is C2 + C3

• The output resistance is 1/(gds1 + gds2)

• The transfer function has one pole

The unity gain frequency is:

It increases as the square root of the bias current increases

• Due to Miller’s theorem the input capacitance becomes: Cin = C1 + C2(1 - Av)

if |Av| >> 1 it can become significant to the stage driving it.

( )32

Dpn

32

2ds1dsp CC

I

CCgg

+

λ+λ=

++

=ω

( ) D32

ox1

32

1mvpT I

CCLWC2

21

CCg

21

0A21

f+

µ

π=

+π=ω

π=


Example

Simulate an inverter with active load (VDD = 5 V) as the following figure with BSIM3 V2

Models. Find the DC gain and unity gain frequency.

Observe that the achieved gain is about 47 dB; the unity gain frequency is fairly good, being

around 500 MHz and the phase margin is about 87 degrees.


CASCODE

The cascode gain stage is used to attenuate the Miller effect on node 1.

Bias voltage such to keep M1 in the

saturation region

2oxn

1

1oxn

1n,Th

LWC2

I

LWC2

IV""

µ

+

µ

+=

=++=+> 2,satn,Th1,sat2GS1,satB VVVVVV



C1 = Cgs1 + Cgs1,ov

C2 = Cgd1 + Cgd1,ov

C4 = Cgs2 + Cgs2,ov + Cdb1 + Csb2

C3 = Cgd2 + Cgd2,ov + Cgd3 + Cgd3,ov + Cdb2 + Cdb3 + CL

For low frequency, neglecting gds1 and gds2:

gm1vin = -gm2v1 = -gds3v0

Hence:

The Miller effect is significantly reduced if gm1 ≈ gm2

2m

1m

in

11

3ds

1m

in

0v g

gvvA

gg

vv

A −==−==


At high frequency:

The circuit has two nodes: the output and node 1.

• The capacitance at the output is C3

• The output impedance is 1/gds3 (neglecting the impedance at the drain of M2)

• The capacitance at the node 1 is (C2 + C4)

• The impedance at the node 1 is 1/gm2

• The pole associated to the output node is:

• The pole associated to the node 1 is:

Where ζ = (1 + rds3/rds2)

3

3ds

outout,p C

g211

21f

π=

τπ=

( ) 21m422m

22m

11,p CgCCg

/g211

21f

++ζ

π=

τπ=


Since gm >> gds, fp,out is dominant.

• The gain-bandwidth product is:

If a good phase margin is needed, it must be:

This conditiin can be fulfilled

by increasing CL.

3

1mvdom,pT C

g21Affπ

==

( ) 21m42

2m

3

1m

CgCC/g

Cg

++ζ<


Impedance at the drain of M2:

1ds

x2s

2ds

2s2mx

1ds

xx g

ivg

vgigiv =

++=

2ds2m1ds1ds

2m2ds1ds

x

x2D rgr

gg1rr

ivr ≅

++==


Impedance at the node 1,r1:

( )xmx2dsx1ax vgiriRv −+=

2m2ds

3ds

2m2s gr

r1

g1r ζ=

+=


CASCODE WITH CASCODE LOAD

• Transconductance gain stage

The gain is increased by increasing gm or rout.


• In the improved version the transconductance of M1 is increased by the factor

• VB1 and VB2 must keep M1

and M4 out the triode region

VB1 > Vsat,1 + VGS2

VB2 < VDD - Vsat,4 - VGS3

The figure plots the folded

structure useful if we need to

raise the voltage source of M1

( )4

54

M

MM

I

II +



The output impedance is (conventional version):

[for the improved and folded version rds1 must be replaced with (rds1//rds5)]

The DC gain is:

The circuit has three nodes:

• The output node

• The source of M2

• The source of M3

( )( )3ds3m4ds2ds2m1ds

3ds3m4ds2ds2m1dsout rgrrgr

rgrrgrr

+=

( )( ) ( )2dsm

3ds3m4ds2ds2m1ds

3ds3m4ds2ds2m1ds1mv rg

21

rgrrgrrgrrgr

gA ≅+

−=


The transfer function will have three poles. The dominant one is the output pole

Cout, C2, C3 capacitances incident on nodes 1, 2, 3.

At low frequency:

333

222

outoutout,p Cr

121f

Cr1

21f

Cr1

21f

π=

π=

π=

( )( )3ds3m4ds2ds2m1ds

3ds3m4ds2ds2m1dsout rgrrgr

rgrrgrr

+=

1ds2ds

4ds3ds3m

2m2 r

rrrg

1g

1r

+=

4ds3ds

2ds1ds2m

3m3 r

rrrg

1g

1r

+=

32out r,rr >>


At high frequency:

• Output swing:

The output swing is limited by the conditions for which one of the transistors of the stage is

brought out of saturation

VB1 and VB2 must keep M1, M4, and M5 out of the triode region.

3m3

2m2 g

1rg

1r →→

3sat3GS2Bmaxout VVVV −+=−

2sat2GS1Bminout VVVV −+=−


Example

Simulate the folded cascode amplifier, shown in the following figure, with VDD = 3.5V. Use

the models BSIM3V2 to find the gain and the phase from input to output and from input to

node 2.

We observe that the gain and the phase plots of the output show a 20 dB roll-off with a good

phase margin (60 degrees). The low frequency gain is 77 dB and the unity gain frequency

is around 80 MHz. The behavior of the gain from the input to node 2 is interesting: above

the dominant pole, it holds 14 dB, just 2 dB more than the expected value gm1/gm2. At low

frequency climbs to 34 dB.


DIFFERENTIAL STAGE

M1, M2 in saturation with (W/L)1 = (W/L)2

assume:

( )2Th1GS

1

ox1 VV

LW

2C

I −

µ

=

( )2Th2GS

2

ox2 VV

LW

2C

I −

µ

=

2vVV;

2vVV in

0GS2GSin

0GS1GS −=+=


The output variable is the differential current:

since the bias current can be expressed as:

it results: at small signal:

with a common mode signal:

( )Th0GSin1

ox21 VVvLWCIII −

µ=−=∆

( )2Th0GS

1ox21SS VV

LWCIII −

µ=+=

SS1

oxin ILW

CvI

µ=∆ mingvi =∆

i

in

im

CMmCM r2

vrg21

vgi ≈

+=

imCM

d rg2ii

CMMR ≅=


Example

Verify equation Consider an n-channel differential pair using

(W/L) = 100 µm and Iss = 100 µA.

The transconductance transfer function is fairly linear over a wide range of input signal. It starts to saturate only when the input signal approaches the overdrive voltage of the differential pair (75 mV).

.ILWCvI SS

1oxin

µ=∆


SOURCE FOLLOWER

Used as buffer or as DC-level shifter

at low frequency:

hence:

( ) 0vgvgvgg 1gs1mout1dsout2ds1ds =−++

1mb2ds1ds1m

1m

in

outv gggg

gvv

A+++

==


If

at high frequency:

where:

The output impedance is obtained by applying a test source Vx at the output node.

Hence:

The output is not symmetrical. For n-channel input device

( )out1

1v CC

CSA

+≅

ov1gs1gs11sb2dbov2gd2gdL CCCCCCCCC +=++++=

1Athengggg v1mb2ds1ds1m ≈++>>

( ) x1m1mb2ds1dsx vggggi +++=

1m1mmb2ds1dsout g

1gggg

1R ≅+++

=

2satminout1GSDDmaxout VVVVV =−= −−


Example

Simulate the large signal behavior and derive the dc small signal voltage gain. IB = 0.1 mA

and VDD = 3.3 V.

The output voltage, practically, follows the input shifted by VGS. However, due to the body

effect, the value of VGS is not constant; it rises from 713 mV to 1.13 V. Therefore, the input-

output characteristic is not 1 but 0.81. The figure shows also the dc gain: its value ranges

from 0.74 to 0.86 quite well match as theoretical results.


IMPROVED OUTPUT STAGES

Performances improved by the use of negative feedback.

( ) x3ds1m224mx2ds1mx vrgvvgvggi =++=

( ) 2ds3ds4m1mout grg1g

1R++

=


Class AB push-pull:

let:

With Rout = 0:

The output conductance is:

With resistive load, the drop voltage across the output resistance determines (going out

current):

µ+

µ++=+=

ox4p

4

ox3n

35p,Thn,Th4GS3GS12 CW

L2CW

L2IVVVVV

4231 LWk

LW

LWk

LW

=

=

;kIII;VV;VV 5214GS2GS3GS1GS ==≈≈

2m1mout ggg +=

out124GS2GS3GS1GS III;VV;VV −=<>


For a given load I2 --> 0; the output conductance becomes gout = gm1

In general an output stage has the following equivalent circuit:

It determines harmonic distortion

( )...II1RR 2out2out10outout +α+α+=


Class AB push-pull with gain stage

if it is verified the condition:

2g1g VV ≈

6ds5m4m

rg

1g

1 <<+


Voltage divider

• Analog circuits normally have only two dc voltage supplies

• In order to obtain dc bias voltages, voltage dividers can be used

• Resistive or capacitive dividers can be used, however they are

complex or silicon area consuming

• MOS in the diode configuration can be used

The transistors are in saturation

( ) ( )22Th2DS

2

21Th1DS

1VV

LW

2k

VVLW

2k

−

=−

DD2DS1DS VVV =+


It results a voltage division of VDD plus

an offset.

If a signal (usually undesired) is

superposed to VDD, the small signal

equivalent circuit must be considered.

At low frequency (assuming gm2>>gds2 and gm1>>gds1)

2gs22sb1db1gs1 CC;CCCC =++=

21

2Th21DS1DD

21

21DS1

VVVVV

α+αα−α

+α+α

α==

22

11 L

W;

LW

=α

=α


At high frequency

It results an injectin of the noise from the power supply (VDD)

2m1m

mb

2m1m

2m1m

mb

1mdd1

ggg

g1

g1

ggg

g1

VV++

+⋅=

21

2DD1 CC

CVV+

⋅=


Level Shifter

Essential for NMOS circuits, useful for CMOS circuits

• High-impedance level shift

• Low-impedance, or “battery”, level shift

High Input Impedances:


• Body effect neglected

• Threshold voltage variation effect (∆VTh ≈ +150 mV)

• Input and output swing limitation

Level shift threshold-independent:

(assuming M1 in saturation and neglecting λ)

usually ∆V < VTh

ThovThGS VVVIkW

L2VV +=+==∆

( )

−−−

=∆ 2

221

1I

WLII

WL

k2V


Low Impedances:

• It behaves like a voltage source

a)

b)

a) Simple level shifter b) Shunt feedback level shifter

a) rout = 1/gm

b) affected by twice voltage

threshold variation

ThDS VIkW

L2VV +==∆

22

11

2Th1Th2GS1GS IkW

L2IkW

L2VVVVV

+

++=+=∆

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