Claas Cornelius, May 2006Institute of Applied Microelectronics and Computer Engineering, University of Rostock

Deep Submicron Technology: Opportunity or Dead End for Dynamic Circuit Techniques

Claas Cornelius1, Frank Grassert1, Siegmar Köppe2, Dirk Timmermann1

1University of Rostock, Germany2Infineon Technologies AG

20th International Conference on VLSI DesignBangalore, India, January 2007

In cooperation with

Claas Cornelius, January 2007Institute of Applied Microelectronics and Computer Engineering, University of Rostock1

Outline

IntroductionFundamentalsTechnology developmentMotivation

Actual workDynamic logic stylesImplementationResults

Conclusions & Outlook

Claas Cornelius, January 2007Institute of Applied Microelectronics and Computer Engineering, University of Rostock2

Fundamentals

Static CMOS

ReliableScalableAutomated design toolsavailableGood compromise of speed, size, power consumption

Static CMOS is and has beenthe dominating circuit technique

Claas Cornelius, January 2007Institute of Applied Microelectronics and Computer Engineering, University of Rostock3

Fundamentals

Dynamic logic

Phases of operation:

Prechargeclk = 0X 1

Evaluationclk = 1X 0X = 1

Dependingon the input

Claas Cornelius, January 2007Institute of Applied Microelectronics and Computer Engineering, University of Rostock4

Fundamentals

Dynamic logic

FastPower hungrySusceptible to noiseDifficult to implement

Continuously used to boost performanceE.g. Intel Pentium 4 [Deleganes, 2004]

IBM Power4 [Warnock, 2002]Sun Sparc V9 [Heald, 2000]

clk

Input

X

PDN

clk

p1

n1

That is past and present, how about the future ?

Claas Cornelius, January 2007Institute of Applied Microelectronics and Computer Engineering, University of Rostock5

Technology development

[Sery, 2002]

0.010.1

110

1001000

10000100000

1000000

1970 1980 1990 2000 2010 2020

MIPS

1 TIPS

8080

8086

386 Pentium®

Pentium® 4

Performance

Claas Cornelius, January 2007Institute of Applied Microelectronics and Computer Engineering, University of Rostock6

Technology development

0.1

1

10

100

1000

1970 1980 1990 2000 2010 2020

Pow

er d

issi

patio

n(W

)

1000's of Watts ?

8080

8086 386

Pentium®

Pentium® 4

Power dissipation

[Sery, 2002]

Claas Cornelius, January 2007Institute of Applied Microelectronics and Computer Engineering, University of Rostock7

Leakage currents

Technology development

Sub-threshold currentsReverse-biased currentsDrain-Induced Barrier LoweringGate-Induced Drain LeakagePunch-through EffectNarrow-Width EffectGate-Oxide TunnelingHot-Carrier Injection

SiO

Source Drain

GateIgate

Isub

L

SiO2

L

n+ n+

[Sery, 2002]

0,1

1

10

100

1000

0.25u 0.18u 0.13u 90nm 65nm 45nm

Technology

SD L

eaka

ge (W

) 30M Tr15mm Die

Claas Cornelius, January 2007Institute of Applied Microelectronics and Computer Engineering, University of Rostock8

Technology development

Interconnects

[Tenhunen, 2005]

Example (very optimistic):6–10 clock cycles in 50nm technology

[Benini, 2002]

Propagation delays of global wires will be a multiple of the clock cycle.

Claas Cornelius, January 2007Institute of Applied Microelectronics and Computer Engineering, University of Rostock9

Technology development

130nm~1000 samples

30%

5X0.9

1.0

1.1

1.2

1.3

1.4

1 2 3 4 5Normalized Leakage

Nor

mal

ized

Fre

quen

cyPower4 Server Chip

[Devgan, 2003]

[Borkar, 2005]

Parameter variability dramatically increasing

[ITRS, 2003]

Parameter variability

Claas Cornelius, January 2007Institute of Applied Microelectronics and Computer Engineering, University of Rostock10

Technology development

[Tredennick, 2003]

Costs

Fixed costs per wafer aregrowing exponentially.

Only high volume chipsreasonableNumber of ASIC designstarts declining

Year 3 year design staff Staff cost ($150k/Staffyear)

1997 210 90 M

1999 360 160 M

2002 800 360 M

Claas Cornelius, January 2007Institute of Applied Microelectronics and Computer Engineering, University of Rostock11

Motivation

Consequence of the problems:

„Power outperforms Performance.”

Chip-Area Power consumption Performance

General Purpose Processors (GPP) 2X 2-3X ~1.4X

Growth rate when new technology is introduced:

Requirements:More MIPS/mm²More MIPS/Watt

Claas Cornelius, January 2007Institute of Applied Microelectronics and Computer Engineering, University of Rostock12

Motivation

Large number of challengesWell-known, but intensified issuesNew issues

Examination and determination ofperformance parametersassociated limitations/conditionspossible applications

Deep Submicron Technology: Opportunity or Dead End for Dynamic Circuit Techniques?

Claas Cornelius, January 2007Institute of Applied Microelectronics and Computer Engineering, University of Rostock13

Motivation

Related work

Comparison of circuit techniques:[Chu, 1987][Ng, 1996]...

Domino logic won‘t work past 70 nm[Anders, 2001]

Demonstration of modified Domino in 45 nm[Yang, 2004]

Claas Cornelius, January 2007Institute of Applied Microelectronics and Computer Engineering, University of Rostock14

Dynamic logic styles

clk

Input

X

PDN

clk

p1

Y

n1

k1

Single-rail Domino

[Heller, 1984][Krambeck, 1982]

DCVS-Domino(Differential Cascode Voltage Switch)

Claas Cornelius, January 2007Institute of Applied Microelectronics and Computer Engineering, University of Rostock15

Dynamic logic styles

High-Speed Domino

[Ng, 1996][Allam, 2000]

XC-Domino / XC-Differential(Cross Coupled)

clk clk

YY

I1

I2

I1 I2

XX

k1 k2

clk

Claas Cornelius, January 2007Institute of Applied Microelectronics and Computer Engineering, University of Rostock16

Dynamic logic styles

DCSL(Differential Current

Switch Logic)

[Gayles, 1997][Somasekhar, 1996]

SPSD(Sympathetic Precharged

Static Domino)

Y

clk Input Input clk

clk clk

Y

p2p1

PDN PDN

Claas Cornelius, January 2007Institute of Applied Microelectronics and Computer Engineering, University of Rostock17

Implementation

Test designsWorst-case scenarioWallace multiplierSeveral logic specificInfluence of sizing

Test chipPrototype (90 nm)Modular64 designs for testMeasurement of

FunctionalityDelayFrequencyPower

Clock generation

Clock generation

ControlControl

Registers(Stimuli)

Registers(Stimuli) Test designsTest designs

Test selectionTest selection

Claas Cornelius, January 2007Institute of Applied Microelectronics and Computer Engineering, University of Rostock18

0

100

200

300

400

500

0 1 2 3 4 5

1/Delay (GHz)

Pow

er-D

elay

-Pro

duct

(fJ)

SCMOS SR-DominoXC-Differential DCVS-DominoDCSL HS-DominoSPSD XC-Domino

Results for the worst-case scenario:90 nm TechnologyPipelined design (5 stages)All gates with maximum wire load and maximum fan-out

Results

Claas Cornelius, January 2007Institute of Applied Microelectronics and Computer Engineering, University of Rostock19

0.0

0.2

0.4

0.6

0.8

1.0

1.2

0 1 2 3 4

Capacity Ratio

Volta

ge (V

) Internal node XOutput Y

Large number of causesendangers reliability:

Charge leakageCharge sharingPower supply noiseCrosstalkClock skewSubstrate charge injectionSoft errorsand more …

Results

Reliability

PDN‘s internal capacitanceCapacitance of the dynamic node

Capacity Ratio =

Claas Cornelius, January 2007Institute of Applied Microelectronics and Computer Engineering, University of Rostock20

Results

Results for the worst-case scenario:90 nm TechnologyPipelined design (5 stages)All gates with maximum wire load and maximum fan-out

400

410

420

430

440

3.0 3.1 3.2 3.3 3.4 3.5 3.61/Delay (GHz)

Pow

er-D

elay

-Pro

duct

(fJ)

DCVS-Domino (no Keeper)DCVS-DominoHS-DominoXC-Domino

0

Larger keeper (5x)

Minimum keeper

Claas Cornelius, January 2007Institute of Applied Microelectronics and Computer Engineering, University of Rostock21

Results

Automated design flowDerived from standard CMOS flowLogic compression for target libraryInsertion of registersClock tree implementation

Design flow

[Flügel, 2001]

Claas Cornelius, January 2007Institute of Applied Microelectronics and Computer Engineering, University of Rostock22

Conclusions & Outlook

Dynamic logic is functional in 90 nm technologyClearly outperforms static CMOS

in terms of delay and area @ high speed

Reliability endangers signal integrity and has to be monitored

Various dynamic logic styles applicable

Several techniques to cope with problems have become standard and ease the use of dynamic logic?

Shadow latches, razor techniquesClock- and data-gatingDynamic Voltage/Frequency Scaling…