Fault Tuples in Diagnosis of Deep-Submicron Circuits”

R. D. (Shawn) Blanton J. T. Chen R. Desineni K. N. Dwarakanath W. Maly T. J. Vogels

Center for Silicon System Implementation, Dept. of Electrical and Computer Engineering,

Carnegie Mellon University, Pinsburgh, PA 15213 hlanton@ece.cmu.edu

Abstract Diagnosis of malfunctioning deep-submicron (DSM) ICs is becoming more dificult due to the increasing sophistication of the manufacturing process and the structural complexity of the IC itself: At the same time, key diagnostic tusks that include defect localization are still solved using primitive models of the IC’s defects. This paper explores the use of “jault tuples” in diagnosis. Fault tuples can accurately mimic the complex misbehavior of DSM ICs at the logic level, enabling practical diagnosis of large circuits. Initial assessment of the use of fault tuples in diagnosis is per- formed based on a case study involving one specific category of polysilicon spot defects. Obtained results indicate that fault tuples may enhance diagnosis significantly.

Keywords: failure analysis, diagnosis, fault model and char- acterization.

1 Introduction Spectacular advances in the IC industry stem from come-

sponding increases in the complexity of IC manufacturing. In other words, advanced IC fabrication enables more com- plex and powerful device structures, which unfortunately leads to intricate and unexpected forms of IC misbehavior. There is another side of the deep submicron (DSM) reality. Today, the test of DSM devices still relies heavily on the sin- gle stuck-line (SSL) fault concept. Stuck-at faults were cre- ated decades ago to mimic or model the misbehavior of defective vacuum tubes [l]. Is the stuck-at fault model there- fore still relevant today? The answer appears to be “Yes”. However, this paper is not intended to discuss the validity of the above “opinion”. Instead, it reveals that the stuck-at fault model and other models are not sufficient for covering all the needs of the DSM era.

A survey of current test literature reveals that we are not alone in the search for a fault modeling methodology that can provide better accuracy in capturing the (non-SSL) mis- behavior of manufacturing-induced defects of DSM ICs. Actually, there have been many meaningful contributions

guided by this objective [2]-[16]. Techniques to diagnose multiple stuck-at faults were presented in [21 and [31. Bridg- ing faults of various types (e.g. wired-logic, biased-voting, dominant-driver, etc.) have been used to create dictionaries for cause-effect analysis, and to perform effect-cause analy- sis via fault simulation [4]-[9]. Other approaches have con- sidered transistor stuck-open [IO], interconnect open [I I], and path delay [12][13] faults. There is yet other work that has expanded its misbehavior models to include multiple fault types. In [14], both multiple stuck-at and transition fault models are utilized while [I51 uses different types of hridg- ing faults, and [I61 considers stuck-at, stuck-open and delay faults.

Although past work has considered fault types that more accurately reflect defect behavior, they are still limited to the types of misbehavior selected a priori by their choice of fault model(s). Our diagnosis approach based on fault tuples attempts to remove this limitation. A fault tuple based diag- nosis is inherently more general in that arbitrary misbehav- iors can be directly and effectively dealt with. In this paper, we illustrate the potential diagnosis capability of fault tuples by examining a defect that cannot be directly analyzed using existing techniques.

Fault tuples were introduced in [17][18] where it was shown that they can he used to represent complex logic mis- behaviors in both function and time. Fault tuples seem to he the most general representation of faults for covering the widest range of misbehaviors [19]. The purpose of this paper is to describe a case study that was conducted in order to substantiate the above claim in the domain of diagnosis. The specific goal of this study was to determine if fault tuples can he used to model complex misbehavior, and if so, how they are applicable in DSM defect diagnosis.

The rest of the paper is organized as follows: Section 2 defines terminology and briefly introduces fault tuples. Section 3 describes the experimental setup for our case study where we used fault tuples to represent a complex manufac- turing defect. The results from our experiments are presented in Section 4, and finally key observations and conclusions are drawn in Sections 5 and 6, respectively.

*This work was supponed by the Gigscale Silicon ReSearch Center, Mcnior Graphics, Pinsburgh Digital Greenhouse and the Senuconduclor Research Corpomtiun

ITC INTERNATIONAL TEST CONFERENCE

0-7803-7542-4/02 $17.00 0 2002 IEEE

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an error is activated at signal line a2. Therefore, a product can be used to represent the activation conditions for a faulty behavior.

A macrofault M=(PI+P2+ ...+ P,) is a disjunction of n products and is therefore, an AND-OR combination of fault tuples. A macrofault is said to be detected if and only if at least one Pi E M is satisfied and one or more errors (if any) are observed, that is, one or more of the errurs activated due to the satisfaction of one or more products must be propa- gated to an observable point. Therefore, a macrofault can be used to represent multiple and alternative activation and observation requirements for the logic misbehavior of one or more defects. The complete, formal specification of fault tuples can he found in [19].

2 Terminology In this section we define the terminology used in the rest

of the paper.

2.1 Defects, faults and test sets A defect is a permanent deformation of the die structure.

It can be localized to a spot of extra or missing material in one or more IC layers. The term bridging defect is used to describe a spot defect that spans the space between two con- ducting regions. The term fault refers to the logical misbe- havior of a circuit. A fault model represents the logical misbehavior caused by some of the defects in the die. The single-stuck line (SSL) fault model assumes that only one logic signal line can be permanently stuck-at either logical 0 or 1. The term bridging fault refers to the situation where two signal lines always have the same logic value.

A test pattern is a completely-specified input vector that is applied to the primary inputs of the circuit under test (CUT). A lest set is a set of test patterns for the CUT. The test set is usually created with a particular fault (not defect) model in mind. A test response is the output vector observed at the primary outputs when a test pattern is applied and a fester response is the set of responses produced by the CUT after applying a given test set.

2.2 Fault tuples A fault tuple is a three tuple (1, v, r), where l is any signal

line in the circuit, v is one of (0, 1, D, 5, etc.)’ and f is an inter-clock cycle constraint range that describes when l must equal v.

A fault tuple ( I , v, t ) is satisfed if and only if the signal line I is controlled to the value v in the clock cycle range described by f . For example, tbe fault tuple fl=(ll, 0, i ) is sat- isfied if logic value 0 is applied to signal line I , in any clock cycle i . Similarly, the fault tuple f2=(12, D, i ) is satisfied if logic value I is applied on I , in any clock cycle i .

A product P=fjr.f2. ...?pm is a conjunction of m fault tuples and is satisfied if and only if each fault tuplef, of P is satis- fied. For example, consider product P1 consisting of two fault tuples P1=(al , 1, $.(a,, D, i). If logic 1 is established at signal lines a, and a2 during the same clock cycle i , both fault tuples are satisfied, implying that the product PI is sat- isfied. Product satisfaction also indicates that fault tuples with v=D or v=B establish errors at the corresponding signal lines. For example, satisfaction of PI in clock cycle i means

1 . D and Dare the well-known error discrepancy values describing the good (g) and enontous (e) values on a signal line, repre- sented as de. D is defined as 1/0 and as 0/1.

3 Simulation Experiment A complete and accurate assessment of the applicability

of fault tuples in the diagnosis of complex misbehaviors of DSM circuits can perhaps only he accomplished after many years of actual usage in analyzing real-life problems. How- ever, we intend to initiate the assessment of fault tuples in the diagnosis of complex misbehaviors by analyzing a small circuit and a particular defect type that cannot he represented using traditional fault models but can be modeled using fault tuples.

3.1 Experimental approach The strategy for the experiment described in this paper is

quite simple and was guided by a single question: Can defect diagnosis based on fault tuples produce results that are unachievable ofhenvise? To answer this question, we SPICE simulated a small circuit that was altered to include a model of complex defect misbehavior. SPICE simulation was used to emulate the “TESTER, i.e., to compute tester responses of the CUT affected by “real defects”. Such a simulation was repeated for each altered circuit element (gate) to reflect each “real defect” instance under consideration. FATSIM [17], a logic fault simulator based on fault tuples, was used in the diagnostic procedure. Specifically, macrofaults repre- senting defects were simulated using FATSIM to produce a list of “predicted misbehaviors”. Finally, the predicted mis- behaviors were compared to the tester (SPICE) responses. If a tester response was included in the set of predicted misbe- haviors then it was assumed that the corresponding macro- fault(s) represents the “real defect”. Since we knew exactly what defect caused what tester response, we can accurately gauge the correctness of the diagnosis. More specifically, we can determine whether or not the defect location and its type indicated by the diagnosis matches the defect used in the SPICE simulation. If there was no match, it was assumed that diagnosis failed. Further details of our approach are described next.

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3.2 Modeling misbehavior In practice, the large variety of realistic defects that can

occur in each standard cell should be modeled as a macro- fault. If implemented manually, the mapping of defects to macrofaults is a tedious task. On the other hand, tools such as the Contamination-Defect-Fault Simulator (CODEF) [20] can he used to automate the mapping process. Given a manu- facturing technology description and a layout, CODEF simu- lates the fabrication process as a “virtual fab” and produces a SPICE netlist which represents the fabricated IC. During CODEF simulation, a defect may be established by introduc- ing a contamination during one of the fabrication steps. CODEF also has a Monte Carlo mode of operation where contaminations can be introduced into random process steps and random locations in the design layout. Using the Monte Carlo mode of CODEF, a set of SPICE netlists representing the possible defects for each standard cell can be generated. The resulting SPICE netlists can then be simulated to obtain the logical misbehaviors which then can be mapped into macrofaults.

In this paper, for the purpose of exploring how fault tuples may be used for, diagnosis, we selected a realistic, yet simple defect of the IC structure; one that could not he directly modeled on the logic level as a stuck-at or bridging fault. The selected defect was then manually mapped to the logic level using macrofaults.

3.2.1 The “Nasty Poly Spot Defect” (NPSD) In reality, there exist many deformations that meet the cri-

teria described [21][22], all of which are well understood and discussed extensively in the literature. A deformation suitable for our purposes is illustrated in Figure 1, where the layout and cross-section of a defect-free and defective NMOS transistor (of a typical CMOS technology) are shown. The defect is depicted as a circular spot of extra (unwanted) polysilicon (see Figure l(b)). Note that the loca- tion and the size of the extra polysilicon prevents the metal terminal connection of the drain and source in the silicon bulk. (It is easy to understand how this deformation can occur if one recalls that polysilicon deposited within the active region always occurs on top of the gate oxide.) In addition, the same spot of polysilicon forms an unwanted connection between the metal terminal of the source (or drain) to the gate of the transistor. Hence, this spot of extra poly causes an open and a short at the same time. making it inherently “nasty”. Thus, we refer to this defect as the nasty poly spot defect (NPSD).

For an inverter, NPSDs may occur at four different loca- tions indicated by the arrows shown in Figure 2(a). They may occur at both the source and drain of the PMOS and NMOS transistors. For the 2-input NAND gate layout shown in Figure 2(b), NPSDs may occur at six different locations.

(a) (b)

Figure 1. Top and cross-section views of an NMOS transistor (a) without and (b) with an NPSD.

(A larger spot of extra polysilicon might cause yet more defect sites; however, these other potential sites are not con- sidered here.)

(a) (b) Figure 2. Possible locations for NPSDs for (a) an invelter and (b) a 2-input NAND gate.

Of course, the NPSD is just one of many complex defects that may occur in a semiconductor product. We have decided to focus upon it since it sufficiently satisfies our criteria for the objectives of this case study.

3.2.2 Modeling NPSDs with fault tuples

We now describe how fault tuples are used to model the misbehavior induced by NPSDs. Figure 3(a) shows an exan- ple layout of a defect-free inverter and its corresponding transistor schematic. In Figure 3(b), the defect D1, caused by the NPSD at the source of the PMOS, shorts signal line a to VDD. The behavior of D, mimics the behavior of the SSL fault a stuck-at I and thus, can be represented using fault tuples as M,={(a, 0, i)).

Although the misbehavior of this defect can be described using the SSL model, the misbehaviors of other NPSDs are more complicated and cannot be captured using SSL faults. Consider for instance defect D, caused by an NPSD at the drain of the PMOS transistor as shown in Figure 3(c). An NPSD at this location disconnects the output b from the

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Scenario I Output b (defective circuit)

a and b pulled-low to logic 0 a pull-up strong 1 b pulled-up to logic 1 a pull-up weak Table 2. Misbehavior possibilities for output b when

1

T

's (C)

Figure 3. (a) Defect-free inverter. Inverter affected by an NPSD located at (b) the source and (c) the drain of the PMOS transistor.

drain of the PMOS and simultaneously shorts it to the input a. causing a feedback bridge defect between a and 6. The misbehavior of the inverter in the presence of defect D2 is given in Table 1.

As indicated in Table 1, signal b is driven to a logic 0 when a logic value 0 is applied on signal line a due to the short between the lines. Specifically, for GO, the absence of the PMOS transistor due to D, means that signal line b is driven solely by signal line a. Therefore, the misbehavior caused by D2 when a=O can be modeled using the product PI=(b, D, i).

Output b Input a Defect-free circuit/ Defective circuit

n I 1 I n

input a is equal to logic 1 for defect D2.

turned on. Therefore, the misbehavior caused by defect D2 when a=l for this scenario can be modeled using the product Pz=(6, B, i).

For the second scenario, the driver strength of signal line a is assumed to be weaker than that of signal line 6. Conse- quently, signal line 6 is assumed to be driven to logic 0 and also drives signal line a to logic 0. Therefore, an error dis- crepancy D appears on signal line a and its fanout lines. Therefore, the misbehavior caused by defect D2 when a=l for this second scenario can be modeled using the product P,=(b,OlO,i).(a,D,i). Note that the error on signal line a can- not propagate through the defective inverter since b is driven to logic 0. Hence, if signal line a does not fanout as shown in Figure 4(a), the error on a cannot be propagated and observed at the circuit outputs. On the other hand, if signal line a fans out, as shown in Figure '4(b), the error on a may possibly propagate to an observable point from the fanout lines of a.

Gate with NPSD (no error propagation)

b=010

(a)

Gate with NPSD (no error propagation)

b 4 l O q . ~...

I,=O

I*=O

error propagation 'D ,.~ ....! ....

(b)

Figure 4. Error propagation in the case of a weak driver for signal line a (a) without fanout and (b) with fanout.

The products P I , Pz and P3 described above, represent the exact conditions of all possible misbehaviors exhibited by defect D2. Therefore, defect D2 can be represented as macrofaults that are combinations of the products P I , P2 and P3 depending on the misbehavior exhibited. The nusbehav- ior of defect D, under the condition that the driving strength of a is stronger can therefore be represented as M2=( P1+P2). On the other hand, the misbehavior of Dz under the condi-

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tion that the driving strength of a is weaker can be repre- sented as M3=(P1+P3].

3.3 Circuit under test The design used in OUI experiment is the ‘181 4-bit ALU

circuit 1231. The ‘181 has 14 primary inputs and eight pri- mary outputs. The netlist of this circuit was synthesized using a 0.18pm CMOS standard cell library from which only inverters (INV), NAND and NOR gates with two or three inputs were used. Synthesis under these constraints resulted in a circuit of 95 gates consisting of 348 transistors. The pri- mary inputs and outputs of the ALU were buffered within the “TESTER. The layout of the ALU was generated using Cadence Silicon Ensemble.

3.4 TESTER simulation setup As already mentioned, the tester responses were com-

puted using the circuit level simulator SPICE by conducting voltage tests of a “die” with the flow depicted in Figure 5. The input to the “TESTER’ was a netlist for the 4-bit ALU, a test set that exercises the circuit, and a list of the defects to he considered. The netlist consisted of subcircuits for the CMOS gates and the interconnect.

. I - - - -

Figure 5.

I

Tester parser

, Flow for creating tester responses.

In OUT experiment, a subcircuit containing an inverter or NAND gate was replaced by a modified subcircuit to reflect the impact of a defect on the physical structure of the circuit. Performing this replacement for each defect in the list resulted in a new SPICE netlist for each defective gate. For example, defect D2 of Figure 3(c) was inserted into an inverter macro by adding a low-resistance connection from the input to the output, and removing the PMOS transistor while retaining its dominant parasitic capacitances. The sub- circuits representing the gates with defects were manually created but validated using CODEE From the experience

gained in this experiment, we believe that the mapping of defects to logic misbehaviors is automatable.

So not to be test-set limited in this experiment, we used two different test sets. The first test set, called the locally exhaustive fesf set, contained 31 test patterns. This test set is locally exhaustive in that each gate is exhaustively tested. The locally exhaustive test set was generated using FATGEN [18], our deterministic test generator based on fault tuples. The second test set, called the rudimentary fesf sef, generated by the academic, SSL-based ATPG tool Atalanta [24], con- tained only 20 patterns. The rudimentary test set gives 100% SSL fault coverage.

There are 21 inverters in our ALU netlist, each of which can be defective in four places (see Figure 2). The 47 2-input NAND gates considered can be defective in six ways, mean- ing that the total number of defects inserted into the netlist was (27 x 4) + (47 x 6) = 390 . Since the netlist contains a total of 95 gates, more than 77% of the gates were consid- ered. (To minimize the manual macrofault generation effort, we chose not to consider any of the NOR gates nor the larger 3-input NAND gates.) All 390 NPSDs were detected by the TESTER by both test sets, that is, at least one test pattern from each set both activated the NPSD and propagated the resulting error to a primary output.

To investigate the robustness of our diagnosis approach, a set of bridging defects between circuit nodes was used as well. For each metal layer, bridging defects were extracted from the layout by identifying minimally-spaced intercon- nect pairs that have length of at least 0.75pm. This resulted in a list of 39 bridges between signal nodes and coinciden- tally, another 39 shorts between signal nodes and VDD or GND. Each bridge was SPICE simulated by inserting a 10R resistive connection into the ‘181 ALU netlist.

Our SPICE simulations therefore resulted in 468 = 390 (NPSDs) + 78 (bridges) defect tester responses and one defect-free tester response for each test set (i.e. locally exhaustive and rudimentary) used in our case study.

3.5 Diagnosis procedure The fault tuple based diagnosis of Figure 6 was per-

formed by executing: (a) macrofault generation, (b) macro- fault simulation, and (c) response comparison and analysis.

First, NPSDs for an inverter and a 2-input NAND gate were mapped to one or more macrofaults as described in Section 3.2.2. (Note that mapping a targeted defect type has to be only performed once for a given cell library, indepen- dent of the circuit under test.) A fault list containing 711 macrofaults was automatically generated for the 27 inverters and 47 2-input NAND gates considered. The maximum number of macrofaults for an inverter and a 2-input NAND gate is six and 15, respectively. Our fault list size of 711 is not equal to (27 x 6 ) + (47 x 15) = 867 since some of the

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LlSt Of

ALU4 Macrofault Test netlist Simulation patterns

I t Simulator responses

Defect diagnosed

L NO Defect not diagnosed

Figure 6. Flow diagram of diagnosis procedure.

macrofaults are redundant due to the lack of fanout as described in Section 3.2.2.

In the second step, the fault tuple based fault simulator FATSIM [I71 was used to simulate the 711 macrofaults using both the locally exhaustive and rudimentary test set to create what we call the expected or anticipated defect signatures.

In the third step, tester responses for each defect Di (obtained via SPICE simulations as described in Section 3.4) were compared to the anticipated defect signatures. For each tester response, we constructed afault class ( F C ] , where a fault class contains each macrofault whose anticipated defect signature exactly matches the tester response. The size of a fault class is equal to the number of macrofaults in the class.

We say that a defect Di is currectly diagnosed if the fault class for D;s tester response contains a macrofault represent- ing defect Di (i.e., the NPSD location of DJ. A correct diag- nosis is exact if the fault class contains only one macrofault representing Di, otherwise it is called partial diagnosis. (Note that an exact diagnosis implies that both the defect location and defect type are recognized correctly while a par- tial diagnosis implies macrofault equivalence under the test

set utilized.) On the other hand, Di is incorrectly diagnosed if the fault class for D;s tester response does not contain any macrofault representing Di. Therefore, an incorrect diagnosis for a fault class with sizefO is misleading.

In the first phase of our experiments, NPSDs were repre- sented using fault tuples, and the fault tuple based diagnosis procedure of Figure 6 was used to diagnose the defects. In the second phase, the robustness of the diagnosis procedure was explored by introducing bridging defects in the design and applying the same procedure to diagnose NPSDs in the presence of the newly-introduced bridging defects. In the third phase, an SSL-based diagnosis was perfomled to diag- nose the NPSDs. This phase of the D;s tester response experiment was performed to determine if an SSL-based diagnosis could he used to diagnose complex defects like the NPSDs considered in this study.

4 Results of the Experiment For better assessment of the results presented in this sec-

tion, it is useful to begin with a somewhat trivial hut impor- tant observation: In reality (and in our simulation of the tester), there are defects that produce identical tester responses. Of course, defects producing indistinguishable tester responses cannot he distinguished from each other by diagnosis. (In such cases, the resolution of diagnosis is lim- ited by the structure of the circuit and the applied test set.) In our experiment, defects that resulted in the same tester response for a given test set were grouped into the same defect class { D C ) . Figure 7 shows the distribution of the sizes of the resulting defect classes. (It should be noted that both the locally exhaustive and rudimentary test set coinci- dentally resulted in the same distribution.) For the ALU cir- cuit and test set, Figure 7 indicates that defect class size is relatively small with no class having size greater than five. However, more than two-thirds of the defects have at least one indistinguishable counterpart.

4.1 Diagnosis of NPSDs First, we wanted to determine how well a fault tuple

based diagnosis could identify both the locarion and type of

Table 3. Diagnosis results for NPSDs.

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512s

Figure 7. Histogram of defect class sizes.

the 390 NPSDs considered in this paper. Two separate test sets (locally exhaustive and rudimentary) were used. The results are summarized in Table 3, where each column repre- sents one specific outcome of diagnosis. The concepts of fault class ( F C ) and defect class ( D C ] are used in Table 3 to describe the various diagnostic outcomes and the numerical entries in Table 3 indicate the number of defects for each outcome. .

Firstly, the data in Table 3 reveals that fault tuple based diagnosis was correct for a vast majority of the NPSDs con- sidered. Specifically, 381 of the 390 NPSDs were correctly diagnosed. The diagnosis procedure failed to diagnose nine of the 390 NPSDs. This means that these nine NPSDs behaved in way not predicted by the macrofaults. However, analyzing the results further, one can see that the column under (FC)#{DC} is empty for both test sets meaning that our diagnosis procedure never produced a misleading diag- nosis. Finally, note that diagnostic resolution is increased by the use of the locally exhaustive test set in that the number of exact matches and equivalent partial matches ((FCJ=(DCJ) increases by three and five, respectively.

The bubble diagram shown in Figure 8 allows us to determine if optimal diagnostic resolution has been achieved. Optimal resolution for a defect Di is defined to he achieved when the fault class and defect class are the same (FCi]=(DCiJ. Along the diagonal, the area of a "bubble" is proportional tu the number of defects that were optimally diagnosed for a given class size. For example, consider the case when the defect class size is equal to 1 for the locally exhaustive test set. (See Figure 8(a).) For 80 defects, fault tuple based diagnosis produces an optimal diagnosis. But in 15 cases represented by the three off-diagonal bubbles, our diagnosis procedure is non-optimal; twice it returned a par- tial diagnosis where (FC=3]3(DC=1} (represented by the bubble of size Z), four times it returned a partial diagnosis where {FC=Z]~{DC=I 1 (represented by the larger bubble of size 4), and nine times it returned an empty diagnosis where {FC=O) and {DC=l) (represented by an even larger bubble of size 9). For the rudimentary test set, the number of

. 3

Comparison of class sizes

Figure 8. Comparison of defect and fault class sizes for (a) locally exhaustive and (b) rudimentary test sets.

dclccts opttiiiall! dt; ipnud (hgurc 8thit i.; <lightly rcdurcd.

1.2 Diagnosis selectivity In redlit). a hiling IC c.m exhibit mure thdn unc defect

t!pc. In an .wenipt tu explore thi.; niore realimc ,ituation, bridging deicci \ \\ere introdused dong with the NPSD.; into our te\ter \etup of Figure 5. Me wanted ohserve i i ' o u r NPSD-l~icu\scd d i a g n w h prwedurr. wuld he diluted b! the presence ( i f random hridging dcicit\. In cithcr words. d w , the pretence o i oilicr delc<t\ prevent the diapnc).;i\ ~ l i

UPSDC (%ire that i t i \ not our intenttun hcrc tu hhuu that the hridging detect.; ciln he Ji i lgn~i~cd using our apprmch. Diafnosis n1'bnd;ing detect\. and dny uther dcicd type ibr thxt niauer. i an he xiompli.;hcd hou t ~ l r tuple bawd diagno.;i\ appro.ich.j

We pcrt;)rmcd our experiment by adding 7X hridging dciecrs !Section 3 1) to ihe lict of 390 NI'SDs. Specifically. the SPICE wnulateJ tchtcr re\pon\e, fur the 7 X bridging defect\ were included w i t h the 39)o tester rc\pon.es of the NPSD,. Onl! WSD mnir~iidults (the \ a m a\ uwd i n Section 1 . 1 1 uerc used duniig diagiio\is. The results for the locally crh.iu\ti\c te*t .;et of [hi.; .;e.wnd didgno\i\ cuperi-

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ment are shown in Table 4. (The results for the rudimentary test set were similar.)

#NPSDs: 390 #SSLs: 235

Locally exhaustive test set

Table 4. Diagnosis results for NPSDs obtained uslng tester responses that included bridging defects. Fault class empty -- Fault class not

NPSD does not empty -- NPSD behave as SSL behaves as SSL

193 197

Our discussion of the results are partitioned into two cate- gories based on the defect type diagnosed. Table 4 shows that 38 of the 78 bridging were not diagnosed at all. This is a “good” result since these 38 bridging defects were not mis- takenly diagnosed as NPSDs. The remaining 40 bridging defects were diagnosed as an NPSD since the fault class for these bridge defects contained at least one macrofault repre- senting an NPSD. This is not unexpected since the tester response for each bridge defect exactly matched one or more NPSD tester responses.

Of the 390 NPSDs, nine had an empty fault class as before while 313 could be correctly diagnosed (both location and type correctly identified). However, for each of the remaining 68 NPSDs, the corresponding tester response exactly matched the response of one or more bridging defects, again indicating an equivalence relation under the applied test set. For these 68 NPSDs, it is possible that a bridge defect could lead to a misleading diagnosis. Finally, it should be noted that for all 68 NPSDs and the 40 bridges mentioned in the last paragraph that the defect location was however correctly identified.

4.3 SSL-based diagnosis of NPSDs Another experiment was performed to determine the util-

ity (or futility) of using SSL faults for diagnosing complex defects like NPSDs. Since fault tuples can be used to repre- sent SSL faults [19], the same fault tuple based diagnosis procedure can be used. The only difference is that an SSL- based diagnosis uses a list of macrofaults representing col- lapsed SSL faults instead of NPSDs.

The results from this experiment are shown in Table 5 . It can be seen that 193 of the 390 NPSDs have an empty fault class. This means the SSL-based diagnosis failed to diagnose 193 NPSDs. For the remaining 197 cases, SSL-based diag- nosis was able to diagnose the defect location.

Since 195 of the 390 NPSDs happened to behave exactly like stuck-at faults, SSL-based diagnosis was able to diag- nose the location of the corresponding NPSDs. In addition, SSL-based diagnosis was able to diagnose the location of two other NPSDs that happen to behave like stuck-at faults

- (31 patterns) Rudimentary test set

(20 patterns) I93 197

for the two test sets utilized. (These two NPSDs do exhibit non-SSL behavior for other tests not included in the locally exhaustive or rudimentary test sets.) However, SSL-based diagnosis was obviously unable to diagnose the defect type of the 197 NPSDs. For the remaining 193 NPSDs that did not behave like SSL faults, SSL-based diagnosis was not able to diagnose even the location of the defect. Finally, it should be noted however that a more sophisticated SSL- based diagnosis (e.g. [25]) is likely to perform better defect localization.

5 Key Observations The question motivating this work was: Can fault tuples

be used in DSM defect diagnosis? The results of our expen- ment seem to provide an initial answer to this question.

Our first claim is that fault tuples are capable of accn- rately modeling complex misbehaviors caused by some defects. The provided examples in the form of fault tuple macrofaults developed for NPSDs is a good illustration of this fact. It is very easy to imagine how the same strategy can be applied to other relevant defects such as opens.

The second major observation indicated by the obtained results is that defect diagnosis using fault tuples has potential for producing a better “resolution”, i.e., fault tuples are better suited for identifying defect location but also may provide information about the type of the defect--a major advantage in the DSM era where optical inspection of defects becomes very difficult. But the diagnostic resolution offered by fault tuples must he further investigated since the setup of the experiment used to investigate resolution (Section 4.2) was quite simple in that realistic tester responses will be “con- taminated” by many more types of unexpected responses. We plan to allocate a substantial effort to investigate the diagnostic resolution capability of fault tuples in more detail.

A third and final observation, while not unexpected, is still worth highlighting. The level of achievable diagnosabil- ity depends on both circuit structure and the test set. In this paper, these two important aspects of the diagnosis of com- plex faults was almost entirely ignored. We are convinced that both issues sbonld be investigated in the very near future before postulating any realistic scenario for complex defect diagnosis based on fault tuples.

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6 Conclusions The diagnosis experiment presented in this paper was

meant as a case study for determining both the location and type of defect from tester responses produced by DSM ICs. The importance of this approach to diagnosis appears to be more and more relevant in the development of modem IC processes and devices. In this paper, we argued that tradi- tional diagnostic techniques are not sufficient and new approaches for the DSM era are needed. We have postulated that fault tuples should be used as a possible base for such approaches.

The core of the paper was devoted to understanding the potential applicability of fault tuples in defect diagnosis. We interpret the obtained results as very promising and therefore we plan to allocate significant effort to the development of fault tuple based defect diagnosis methodologies and algo- rithms [26].

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Acknowledgements We would like to thank our research sponsors for their

support of this work and the valuable feedback provided by the ITC reviewers.

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