DC/DC Converter UpdateMarkus Friedl (HEPHY Vienna)

B2GM, 22 July 2012

Motivation: Belle II SVD

We can’t feed the full SVD with existing Kenwood power supplies using linear voltage regulators (as planned in TDR)

OK with DC/DC converters

22 July 2012M. Friedl (HEPHY Vienna): DC/DC Converter Update 2

1748APV25chips

Front-endhybrids

Rad-hardvoltage

regulators

Analog level translation,data sparsification andhit time reconstruction

Unified Belle IIDAQ system

~2mcoppercable

Junctionbox

~10mcoppercable

FADC+PROCUnified optical

data link (>20m)

Finesse Transmitter Board (FTB)

CO

PPER

DC/DCconverters

Introduction General idea is

similar to power grids: transmit higher

voltage at lower current to the front-end to minimize Ohmic cable loss

Please look at my slides from last B2GM for a general introduction and references

Indico Link22 July 2012

M. Friedl (HEPHY Vienna): DC/DC Converter Update 3

DC/DC R&D at CERN and Aachen

DC/DC is the baseline for an upgrade of the CMS experiment

CMS and ATLAS Tracker groups have been studying the use of DC/DC converters for future S-LHC upgrade

CERN Microelectronics group is developing rad-hard DC/DC converter ASICs and air coils

Intensive tests with existing CMS Tracker modules (APV25) and rad-hard DC/DC converter prototypes at Aachen

APV25 + DC/DC work together without noise penalty! See my previous presentation for details and

references

22 July 2012M. Friedl (HEPHY Vienna): DC/DC Converter Update 4

ASIC: AMIS Family

Being developed since 2007 AMIS5 (final) now produced, expected back in

August 2012

22 July 2012M. Friedl (HEPHY Vienna): DC/DC Converter Update 5

Efficiency vs. Iout Efficiency vs. TID

80…85% Rad-hard beyond 100MradAlso tested: no SEB or SEGR A

MIS

4 m

easu

rem

en

ts

“SM01C” CERN DC/DC Module

22 July 2012M. Friedl (HEPHY Vienna): DC/DC Converter Update 6

Final AMIS chip not yet available, but substitute is CERN group developed a DC/DC module (SM01C)

based on commercial converter chip (LTC3605) with similar performance as AMIS, but not rad-hard

Optimized design & layout Size: 28.4 x 13.5 mm2

Shielded air core coil Available for tests Chip will later be replaced

by rad-hard AMIS ASIC

SM01C Converter Module

Meeting with CERN Developers

On 23-24 April, I met Federico Faccio and Georget Blanchot, the DC/DC developers, at CERN

I got a few SM01C DC/DC modules for tests Final module costs (very approximately, for a few

hundred): Chip ~10€, packaging ~2€, PCB ~5€, components

~5€ Shield: ?, air coil ~50€ (if made in industry) Total per module: O(100€)

Remote voltage sensing not recommended (stability issue) Better have slightly higher output voltage to allow

cable drop Possibility of redundancy (2 converters in

parallel, 1 enabled) To be confirmed by designers

22 July 2012M. Friedl (HEPHY Vienna): DC/DC Converter Update 7

Tests with SM01C DC/DC Modules

Junction box board with DC/DC converters to be placed in SVD DOCK boxes

1 and 2 bare hybrid boards (without sensors) attached for tests with 2m final cable

22 July 2012M. Friedl (HEPHY Vienna): DC/DC Converter Update 8

Results: Noise Comparison

Same noise within measurement precision (few %) between conventional and DC/DC powering!

22 July 2012M. Friedl (HEPHY Vienna): DC/DC Converter Update 9

0 1 2 30

100

200

300

400

500

600 APV25 Noise (old hybrid only) Conven-

tionalDC/DC

APV#

Nois

e [

e]

(known problem)

0 1 2 30

100

200

300

400

500

600 APV25 Noise (new hybrid only)Conventional DC/DC

APV#

Nois

e [

e]

Test hybrid(larger)

Belle II design(smaller)

Results: Efficiency

Overall efficiency is 75% at Vin=10V with 2 hybrids load 4 hybrids and lower Vin @ Belle II higher efficiency

(~85%) Anyway more than enough for SVD purposes

Additional (small) improvement possible by larger coil

22 July 2012M. Friedl (HEPHY Vienna): DC/DC Converter Update 10

4 5 6 7 8 9 10 1150%

55%

60%

65%

70%

75%

80%

85%

90%

DC/DC Efficiency vs. Input Voltage

(2 hybrids load)Vout=2.6V

Vin [V]

Effi

cie

ncy

100 200 300 400 500 600 700 800 900 100050%

55%

60%

65%

70%

75%

80%

85%

90%

DC/DC Efficiency vs. Load(Vin=10V) Vout=2.

6V

Iout [mA]

Effi

cie

ncy

Summary & Outlook

Belle II SVD will use DC/DC converters to power front-end Existing Kenwood power supplies are enough for

future SVD CERN is developing rad-hard converter ASIC

Final chip expected back in August Meanwhile: drop-in based on commercial chip Tested successfully with APV25 hybrids

No difference in noise Efficiency of 75% obtained at Vin=10V and 2

hybrids load ~85% expected in final configuration

Will continue tests with full detector modules

22 July 2012M. Friedl (HEPHY Vienna): DC/DC Converter Update 11