silicon detector readout 14 june 2012 markus friedl (hephy) ipm-hephy detector school

Silicon Detector Readout 14 June 2012 Markus Friedl (HEPHY) IPM-HEPHY Detector School

Contents Silicon Detector Front-End Amplifier Signal Transmission Back-End Signal Processing Summary 14 June 2012M.Friedl: Silicon Detector Readout2

Example: CMS Experiment at CERN 14 June 2012M.Friedl: Silicon Detector Readout3 Tracker (Silicon Strip & Pixel Detectors)

CMS Tracker 14 June 2012M.Friedl: Silicon Detector Readout4 Silicon Strip Sensor Front-End Electronics

Silicon Detector Front-End Amplifier Signal Transmission Back-End Signal Processing Summary 14 June 2012M.Friedl: Silicon Detector Readout5

Various CMS Tracker Modules 14 June 2012M.Friedl: Silicon Detector Readout6 Sensors Electronics

Silicon Strip Detectors Typically 300m thick, strip pitch 50...200m Reverse bias voltage for full depletion 50...500V Connection by wire bonds 14 June 2012M.Friedl: Silicon Detector Readout7 CMS Test Sensor with various geometries (1998)Belle Sensor with 45 strips (2004) Wire bond

Silicon Pixel Detectors Pixels can be square (CMS) or oblong (ATLAS) Structure size similar to strip detectors, but N 2 channels Connection by bump bonds 14 June 2012M.Friedl: Silicon Detector Readout8 CMS Pixel Readout SchemeCMS Pixel SensorATLAS Pixel Sensor

Principle of Operation p-n junction is operated at reverse bias to drain free carriers Traversing charged particle creates electron-hole pairs Carriers drift towards electrodes in the electric field Moving carriers induce current in the circuit current source 14 June 2012M.Friedl: Silicon Detector Readout9

Equivalent Circuit of the Detector Applies to many types of detectors, not only silicon Example: wire chamber Coaxial capacitor configuration Moving charges induce current Example: photomultiplier tube Small plates Charge (current) is amplified in each stage 14 June 2012M.Friedl: Silicon Detector Readout10 Current source with capacitor in parallel

Comparison: Voltage vs. Current Source PropertyVoltage SourceCurrent Source Voltageconstantanything Currentanythingconstant Idle (no power)Open (I=0)Shorted (V=0) 14 June 2012M.Friedl: Silicon Detector Readout11 IDEAL PropertyVoltage SourceCurrent Source (Linear) equivalent circuit Resistor causesInternal voltage dropInternal current drop ConversionNorton-Thevenin equivalent: R V = R I ; V = I R V/I ExamplesBattery Wall plug (AC) Detector NIM module outputs REAL

Moving Charges 14 June 2012M.Friedl: Silicon Detector Readout12

Ramos Theorem (1939) Moving charges between inside electric field (e.g. parallel plates) induces current in electrodes i = E q v Current is proportional to electric field E, (moving) charge q and velocity v of the charge It doesnt matter if the charges eventually reach the electrodes or not, only motion counts Fully valid for parallel plate capacitor configuration (large area diode) A bit more complicated for strip detectors more later 14 June 2012M.Friedl: Silicon Detector Readout13

A Bit of Theory 14 June 2012M.Friedl: Silicon Detector Readout14 Space charge density is given by doping Electric field is calculated by Poissons equation Potential is found by integration of field Shown here: full depletion = space charge just extends over full detector

Bias Voltage and Depletion In reality, the electric field is imposed by applied bias voltage What happens if V bias < V depl ? Electric field does not cover full bulk Only part of detector contributes to charge collection lower efficiency Do not operate a detector like that What happens if V bias > V depl ? Linear offset is added to electric field Field tends to become more flat Faster charge collection (Ramo) Limited by breakdown voltage 14 June 2012M.Friedl: Silicon Detector Readout15

Induced Currents (1) 14 June 2012M.Friedl: Silicon Detector Readout16

Induced Currents (2) Typical silicon detector (D=300m) Very low (

Silicon Detector Summary Various Geometries: (Diode), strips, pixels Detector is a current source || capacitance p-n junction operated under reverse bias voltage > V depl Charged particle creates electron-hole pairs Carrier motion in the electric field induces current on electrodes Signal is typically

Pile-up Events Strip detector measurement in a high intensity beam Trigger hit ambiguities and non-peak sampling can occur 14 June 2012M.Friedl: Silicon Detector Readout38 pileups Trigger from this particle Also returns several other samples > 0!

How to Avoid Such Ambiguities? Better timing information implies more data, more energy and/or a higher noise figure Faster Shaping = narrower output pulses Limited by noise performance On-chip pulse shape processing (APV25) Deconvolution filter which processes samples and essentially narrows down the output to a single bunch crossing Off-chip data processing Using multiple subsequent samples and apply a pulse shape fit 14 June 2012M.Friedl: Silicon Detector Readout39

Hit Time Finding Shaper output curve is well known with two parameters Peak amplitude, peak timing Event-by-event fit of shaping curve determines those two Timing resolution of ~3ns (RMS) measured with APV25 14 June 2012M.Friedl: Silicon Detector Readout40

Occupancy Reduction 12 November 2011Markus Friedl (HEPHY Vienna): Status of SVD41 Belle SVD2 Belle II SVD Belle II SVD with Hit time finding Belle Belle II: 40 x increase in luminosity

Front-End Amplifier Summary Integrated circuits with typically 128 channels 2 stages: Preamplifier (integrator: current charge) Shaper (band-pass filter to reduce noise) Noise is referred to input and expressed as charge: ENC = a + b C det (a,b...const, C det...detector capacitance) Shaper bandwidth determined speed and noise Fast large noise; slow low noise Required speed is usually defined by the experiment Slow shaping and pile-up can lead to ambiguities Tricks to circumvent speed limitation, e.g. hit time finding 14 June 2012M.Friedl: Silicon Detector Readout42

Why? Detector front-end is usually quite crowded Radiation environment does not allow commercial electronics Material budget should be as low as possible Power consumption as well (requires cooling = material) Thus, only inevitable electronics is put at the front-end Everything else is conveniently located in a separate room outside the detector, traditionally called counting house Allows access during machine and detector operation 14 June 2012M.Friedl: Silicon Detector Readout44

Example: CMS Experiment Electronics hall is almost as big as experimental cavern Signal distance up to 100m Huge amount of signal transmission lines 14 June 2012M.Friedl: Silicon Detector Readout45 Experimental cavern Electronics cavern

Generic Transmission Chain Signal directions Readout (large amount): front-end to back-end, analog or digital Controls (small amount): back-end to front-end, digital (clock, trigger, settings) Usually, the front-end chips cannot drive the full path Repeater (driver/receiver) is needed to amplify signals 14 June 2012M.Friedl: Silicon Detector Readout46 Front-endRepeater Back-end < 2mup to 100m

Excursion: Electrical Signal Transmission 14 June 2012M.Friedl: Silicon Detector Readout47 Single-ended against GND Huge ground loop GND compensation Single-ended in coaxial cable No ground loop GND compensation Differential twisted pair (+shield) Largely immune

Cable Bandwidth Every cable has a finite bandwidth / damping Nonlinear attenuation with rising frequency 14 June 2012M.Friedl: Silicon Detector Readout48 Example: CAT7 network cable (shielded twisted pairs) Significant especially for analog signal transmission

Alternative: Optical Fiber Fibers have extremely high bandwidth and very little loss Also automatically provide electrical isolation between sender and receiver sides However: requires conversion on both ends, which makes an optical link more expensive than a cable Best suitable for long-haul, high-speed digital data transmission such as telecom Nonetheless also often used in HEP experiments Optical transmission usually implies digital signals with NRZ coding (pure AC signal with only very short DC sequences) 14 June 2012M.Friedl: Silicon Detector Readout49

Comparison: Copper vs. Optical Fiber PropertyCopper CableOptical Fiber Cablerigiddelicate (e.g. radius) Connectorshuge varietyfew standards Size/weightlargesmall Bandwidthlimitedhigh Losshighlow Driver + receivercheapexpensive Level isolationnoyes 14 June 2012M.Friedl: Silicon Detector Readout50

Example: CMS Tracker (1) Optical fiber required because of material budget Exceptional case: analog optical transmission Special requirements for linearity, gain stability and noise 14 June 2012M.Friedl: Silicon Detector Readout51

Example: CMS Tracker (2) Several components are customized and thus expensive O(10000) are small quantities for industry Estimated cost per link: ~150 (cf. ~15 with cable) 14 June 2012M.Friedl: Silicon Detector Readout52

Example: Belle II Silicon Vertex Detector Analog APV25 readout is through copper cable to FADCs Junction box provides LV to front-end APV25 drives 12m cables! 14 June 2012M.Friedl: Silicon Detector Readout53 1748 APV25 chips Front-end hybrids Rad-hard DC/DC converters Analog level translation, data sparsification and hit time reconstruction Unified Belle II DAQ system ~2m copper cable Junction box ~10m copper cable FADC+PROC Unified optical data link (>20m) Finesse Transmitter Board (FTB) COPPER

Example: Belle II Silicon Vertex Detector Using same APV25 chip as in CMS, but much shorter distance no optical link required Analog signals are attenuated in long copper cable First attempt was an analog equalizer chip (enhancing higher frequencies) with moderate success Later tried purely digital filter after digitization Perfect regeneration with digital signal processing (FIR filter) at the back-end inside an FPGA Multiplication of 8 consecutive samples with 8 filter coefficients and summing in real-time (40 MHz) 14 June 2012M.Friedl: Silicon Detector Readout54

Example: Belle II Silicon Vertex Detector 14 June 2012M.Friedl: Silicon Detector Readout55 Raw APV25 output FIR Optimized channelNon-optimized channel FIR filter with 8 coefficients operating continuously at 40MHz Removes cable loss and reflections due to imperfect termination! withoutwith

Signal Transmission Summary Signals of large number of readout channels to be transmitted to back-end for data processing Options: copper cable or optical fiber Copper is much cheaper, but has frequency-dependent loss Can be compensated e.g. with digital FIR filter at back-end Optical links are more complicated to handle Usually digital with NRZ coding Exception: CMS Tracker uses analog optical links 14 June 2012M.Friedl: Silicon Detector Readout56

Perform all the steps which cant be done in the front-end Readout chain: Receiver (electrical or optical), digitization (if analog input), data processing and reduction in FPGA (field programmable gate array), output to DAQ (data acquisition) Receiver for clock, trigger and controls (centrally distributed) Purpose of the Back-End 14 June 2012M.Friedl: Silicon Detector Readout58

Example: CMS-Pixel-FED FED means Front End Driver (misleading) Contains all the elements mentioned before 14 June 2012M.Friedl: Silicon Detector Readout59 Analog optical receivers ADCs FPGAs FPGA To DAQ CLK, Trigger

Boards and Crates Such boards are typically built according to a certain (industrial) standard bus system Standard: VME (Versa Module Eurocard), size 9U Obsolete: CAMAC, Fastbus Modern: TCA All those standards describe Geometry of modules Electrical interface, power supply Bus system for communication with crate controller & PC Organized in crates and racks 14 June 2012M.Friedl: Silicon Detector Readout60

VME (9U) Crates 14 June 2012M.Friedl: Silicon Detector Readout61 Empty crate as sold by industry Belle I Silicon Vertex Detector (cable input) CMS Pixel-FED (optical input)

Whats an FPGA? FPGA is a huge array of logical gates which can be combined according to the users need Programming by software using basic gates & library blocks e.g. and, adder, latch, , CPU core Either by schematics or by VHDL programming language 14 June 2012M.Friedl: Silicon Detector Readout62

Comparison: FPGA vs. CPU PropertyFPGACPU Parallelismanya few cores Speed (clock)O(100MHz)O(1GHz) I/O linesO(1000)64 Best suitable forFast, simple, massive parallel processing Complex, serial programs At the back-endFirst low-level data reduction High-level data processing (DAQ) 14 June 2012M.Friedl: Silicon Detector Readout63

Example: APV25 Output Data Stream 14 June 2012M.Friedl: Silicon Detector Readout64 Amplitude [ADC] Time [25ns] idle header Data frame Strip data (pedestals) Hit data

Strip Data Composition Analog signal output of one event is a multiplexed stream of 128 data values, but not just the actual strip signal ADC i = S i + N i + P i + CMN istrip number ADC i measured amplitude in ADC units S i particle signal N i noise (random fluctuations) P i pedestal (zero value; individual for each strip) CMNcommon mode noise (common to all strips in one event) Pedestal and noise can be measured and saved for each channel, CMN is removed event-by-event 14 June 2012M.Friedl: Silicon Detector Readout65

How to Process Strip Data? Data stream with individual pedestals (dots) Dominated by pedestal variation 14 June 2012M.Friedl: Silicon Detector Readout66 Pedestals subtracted, common mode noise and individual strip noise remains After commom mode correction, average is at zero with random noise excursions for each strip Next: Apply hit threshold

Typical Tasks for Silicon Strip Detector ADC converts data to digital Find and extract strip data Put the strip data in natural order (needed if entangled, e.g. APV25) Subtract zero value for each strip Remove common-mode noise (appears on all strips in common) Apply hit threshold (zero suppression, sparsification) = keep only hit data Optional post-processing (e.g. APV25) 14 June 2012M.Friedl: Silicon Detector Readout67

FPGA Limits Simple state machine, but no complex programming (instruction list) as with a CPU Typically integer arithmetic Made for fast I/O and throughput; internal memory is limited Ideal for first stage of data processing O(10) times more throughput than a state-of-the-art CPU More complex operations at a later stage with reduced data are performed on CPU farms (DAQ) 14 June 2012M.Friedl: Silicon Detector Readout68

Back-End Signal Processing Summary Performs digitization, data processing (reduction) and output to subsequent DAQ (computer farm) stage Pedestal subtraction, common mode correction, zero suppression Boards following a bus module standard E.g. VME (9U) Organized in crates and racks Typically uses FPGAs (field programmable logic arrays) Ideal for low-level massive parallel processing More powerful than CPUs for such tasks Complex calculations are done in subsequent computer farm 14 June 2012M.Friedl: Silicon Detector Readout69

Thank you for your attention! 14 June 2012M.Friedl: Silicon Detector Readout71

silicon detector readout 14 june 2012 markus friedl (hephy) ipm-hephy detector school

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