Computer Hardware Generations - Muhammad Hardware Generations ... • The Second Generation, 1959-64: Discrete Transistors. ... RTN Statement Examples A ← B

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  • EECC550 - ShaabanEECC550 - Shaaban#1 Lec # 1 Winter 2001 12-4-2001

    Computer Hardware GenerationsComputer Hardware Generations The First Generation, 1946-59: Vacuum Tubes, Relays,

    Mercury Delay Lines: ENIAC (Electronic Numerical Integrator and Computer): First

    electronic computer, 18000 vacuum tubes, 1500 relays, 5000additions/sec.

    First stored program computer: EDSAC (Electronic Delay StorageAutomatic Calculator).

    The Second Generation, 1959-64: Discrete Transistors.

    The Third Generation, 1964-75: Small and Medium-ScaleIntegrated (MSI) Circuits.

    The Fourth Generation, 1975-Present: The Microcomputer.VLSI-based Microprocessors.

  • EECC550 - ShaabanEECC550 - Shaaban#2 Lec # 1 Winter 2001 12-4-2001

    The Von-The Von-NeumannNeumann Computer Model Computer Model Partitioning of the computing engine into components:

    Central Processing Unit (CPU): Control Unit (instruction decode, sequencingof operations), Datapath (registers, arithmetic and logic unit, buses).

    Memory: Instruction and operand storage.

    Input/Output (I/O).

    The stored program concept: Instructions from an instruction set arefetched from a common memory and executed one at a time.

    -Memory

    (instructions, data)

    Control

    DatapathregistersALU, buses

    CPUComputer System

    Input

    Output

    I/O Devices

  • EECC550 - ShaabanEECC550 - Shaaban#3 Lec # 1 Winter 2001 12-4-2001

    CPU Machine Instruction Execution StepsCPU Machine Instruction Execution Steps

    Instruction

    Fetch

    Instruction

    Decode

    Operand

    Fetch

    Execute

    Result

    Store

    Next

    Instruction

    Obtain instruction from program storage

    Determine required actions and instruction size

    Locate and obtain operand data

    Compute result value or status

    Deposit results in storage for later use

    Determine successor or next instruction

  • EECC550 - ShaabanEECC550 - Shaaban#4 Lec # 1 Winter 2001 12-4-2001

    Hardware Components of Any ComputerHardware Components of Any Computer

    Processor (active)

    Computer

    ControlUnit

    Datapath

    Memory(passive)

    (where programs, data live whenrunning)

    Devices

    Input

    Output

    Keyboard, Mouse, etc.

    Display, Printer, etc.

    Disk

    Five classic components of all computers:Five classic components of all computers:

    1. Control Unit; 2. 1. Control Unit; 2. Datapath Datapath; 3. Memory; 4. Input; 5. Output; 3. Memory; 4. Input; 5. Output}

    Processor

  • EECC550 - ShaabanEECC550 - Shaaban#5 Lec # 1 Winter 2001 12-4-2001

    CPU OrganizationCPU Organization Datapath Design:

    Capabilities & performance characteristics of principalFunctional Units (FUs):

    (e.g., Registers, ALU, Shifters, Logic Units, ...)

    Ways in which these components are interconnected (busesconnections, multiplexors, etc.).

    How information flows between components.

    Control Unit Design: Logic and means by which such information flow is controlled.

    Control and coordination of FUs operation to realize the targetedInstruction Set Architecture to be implemented (can either beimplemented using a finite state machine or a microprogram).

    Hardware description with a suitable language, possiblyusing Register Transfer Notation (RTN).

  • EECC550 - ShaabanEECC550 - Shaaban#6 Lec # 1 Winter 2001 12-4-2001

    A TypicalA TypicalMicroprocessorMicroprocessorLayout:Layout:

    The IntelThe IntelPentium ClassicPentium Classic

  • EECC550 - ShaabanEECC550 - Shaaban#7 Lec # 1 Winter 2001 12-4-2001

    A TypicalA TypicalMicroprocessorMicroprocessorLayout:Layout:

    The IntelThe IntelPentium ClassicPentium Classic

  • EECC550 - ShaabanEECC550 - Shaaban#8 Lec # 1 Winter 2001 12-4-2001

    A Typical PersonalComputer (PC) System BoardLayout (90% of all computingsystems worldwide).

    CPU

    Memory

    I/O: Mass Storage

    I/O: Misc

    I/O

  • EECC550 - ShaabanEECC550 - Shaaban#9 Lec # 1 Winter 2001 12-4-2001

    Computer System ComponentsComputer System Components

    Proc

    CachesSystem Bus

    Memory

    I/O Devices:

    Controllers

    adapters

    DisksDisplaysKeyboards

    Networks

    NICs

    I/O Buses

  • EECC550 - ShaabanEECC550 - Shaaban#10 Lec # 1 Winter 2001 12-4-2001

    Performance Increase of Workstation-ClassPerformance Increase of Workstation-ClassMicroprocessors 1987-1997Microprocessors 1987-1997

    Integer SPEC92 PerformanceInteger SPEC92 Performance

  • EECC550 - ShaabanEECC550 - Shaaban#11 Lec # 1 Winter 2001 12-4-2001

    Year

    1000

    10000

    100000

    1000000

    10000000

    100000000

    1970 1975 1980 1985 1990 1995 2000

    i80386

    i4004

    i8080

    Pentium

    i80486

    i80286

    i8086

    Microprocessor Logic DensityMicroprocessor Logic Density

    MooresMoores Law: Law:2X transistors/ChipEvery 1.5 years

    Alpha 21264: 15 millionPentium Pro: 5.5 millionPowerPC 620: 6.9 millionAlpha 21164: 9.3 millionSparc Ultra: 5.2 million

    Moores Law

  • EECC550 - ShaabanEECC550 - Shaaban#12 Lec # 1 Winter 2001 12-4-2001

    Increase of Capacity of VLSI Dynamic RAM ChipsIncrease of Capacity of VLSI Dynamic RAM Chips

    size

    Year

    1000

    10000

    100000

    1000000

    10000000

    100000000

    1000000000

    1970 1975 1980 1985 1990 1995 2000

    year size(Megabit)

    1980 0.06251983 0.251986 11989 41992 161996 641999 2562000 1024

    1.55X/yr,or doubling every 1.6years

  • EECC550 - ShaabanEECC550 - Shaaban#13 Lec # 1 Winter 2001 12-4-2001

    Computer Technology Trends:Computer Technology Trends:

    Rapid ChangeRapid Change Processor:

    2X in speed every 1.5 years; 1000X performance in last decade.

    Memory: DRAM capacity: > 2x every 1.5 years; 1000X size in last decade.

    Cost per bit: Improves about 25% per year.

    Disk: Capacity: > 2X in size every 1.5 years.

    Cost per bit: Improves about 60% per year.

    200X size in last decade.

    Expected State-of-the-art PC by end of year 2001 : Processor clock speed: > 2500 MegaHertz (2.5 GigaHertz)

    Memory capacity: > 1000 MegaByte (1 GigaBytes)

    Disk capacity: > 100 GigaBytes (0.1 TeraBytes)

  • EECC550 - ShaabanEECC550 - Shaaban#14 Lec # 1 Winter 2001 12-4-2001

    A Simplified View of TheA Simplified View of TheSoftware/Hardware Hierarchical LayersSoftware/Hardware Hierarchical Layers

  • EECC550 - ShaabanEECC550 - Shaaban#15 Lec # 1 Winter 2001 12-4-2001

    Hierarchy of Computer ArchitectureHierarchy of Computer Architecture

    I/O systemInstr. Set Proc.

    Compiler

    OperatingSystem

    Application

    Digital DesignCircuit Design

    Instruction Set Architecture

    Firmware

    Datapath & Control

    Layout

    Software

    Hardware

    Software/Hardware Boundary

    High-Level Language Programs

    Assembly LanguagePrograms

    Microprogram

    Register TransferNotation (RTN)

    Logic Diagrams

    Circuit Diagrams

    Machine Language Program

  • EECC550 - ShaabanEECC550 - Shaaban#16 Lec # 1 Winter 2001 12-4-2001

    Levels of Program RepresentationLevels of Program RepresentationHigh Level Language

    Program

    Assembly LanguageProgram

    Machine LanguageProgram

    Control SignalSpecification

    Compiler

    Assembler

    Machine Interpretation

    temp = v[k];

    v[k] = v[k+1];

    v[k+1] = temp;

    lw$15, 0($2)lw$16, 4($2)sw$16, 0($2)sw$15, 4($2)

    0000 1001 1100 0110 1010 1111 0101 10001010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111

    ALUOP[0:3]

  • EECC550 - ShaabanEECC550 - Shaaban#17 Lec # 1 Winter 2001 12-4-2001

    A Hierarchy of Computer DesignA Hierarchy of Computer DesignLevel Name Modules Primitives Descriptive Media

    1 Electronics Gates, FFs Transistors, Resistors, etc. Circuit Diagrams

    2 Logic Registers, ALUs ... Gates, FFs . Logic Diagrams

    3 Organization Processors, Memories Registers, ALUs Register Transfer

    Notation (RTN)

    4 Microprogramming Assembly Language Microinstructions Microprogram

    5 Assembly language OS Routines Assembly language Assembly Language

    programming Instructions Programs

    6 Procedural Applications OS Routines High-level Language

    Programming Drivers .. High-level Languages Programs

    7 Application Systems Procedural Constructs Problem-Oriented

    Programs

    Low Level - Hardware

    Firmware

    High Level - Software

  • EECC550 - ShaabanEECC550 - Shaaban#18 Lec # 1 Winter 2001 12-4-2001

    Hardware DescriptionHardware Description Hardware visualization:

    Block diagrams (spatial visualization): Two-dimensional representations of functional units and their

    interconnections. Timing charts (temporal visualization): Waveforms where events are displayed vs. time.

    Register Transfer Notation (RTN): A way to describe microoperations capable of being performed

    by the data flow (data registers, data buses, functional units) atthe register transfer level of design (RT).

    Also describes conditional information in the system whichcause operations to come about.

    A shorthand notation for microoperations.

    Hardware Description Languages: Examples: VHDL: VHSIC (Very High Speed Integrated

    Circuits) Hardware Description Language, Verilog.

  • EECC550 - ShaabanEECC550 - Shaaban#19 Lec # 1 Winter 2001 12-4-2001

    Register Transfer Notation (RTN)Register Transfer Notation (RTN) Dependent RTN: When RTN is used after the data flow is

    assumed to be frozen. No data transfer can take place over apath that does not exist. No statement implies a function thedata flow hardware is incapable of performing.

    Independent RTN: Describe actions on registers withoutregard to nonexistence of direct paths or intermediateregisters. No predefined data flow.

    The general format of an RTN statement:

    Conditional information: Action1; Action2

    The conditional statement is often an AND of literals (statusand control signals) in the system (a p-term). The p-termis said to imply the action.

    Possible actions include transfer of data to/fromregisters/memory data shifting, functional unitoperations etc.

  • EECC550 - ShaabanEECC550 - Shaaban#20 Lec # 1 Winter 2001 12-4-2001

    RTN Statement ExamplesRTN Statement ExamplesA B

    A copy of the data in entity B (typically a register) isplaced in Register A

    If the destination register has fewer bits than the source,the destination accepts only the lowest-order bits.

    If the destination has more bits than the source, the valueof the source is sign extended to the left.

    CTL T0: A = B The contents of B are presented to the input of

    combinational circuit A

    This action to the right of : takes place when controlsignal CTL is active and signal T0 is active.

  • EECC550 - ShaabanEECC550 - Shaaban#21 Lec # 1 Winter 2001 12-4-2001

    RTN Statement ExamplesRTN Statement ExamplesMD M[MA]

    Memory locations are indicated by square brackets.

    Means the memory data register receives the contents of themain memory (M) as addressed from the Memory Address(MA) register.

    AC(0), AC(1), AC(2),AC(3) Register fields are indicated by parenthesis.

    The concatenation operation is indicated by a comma.

    Bit AC(0) is bit 0 of the accumulator AC

    The above expression means AC bits 0, 1, 2, 3

    More commonly represented by AC(0-3)

    E T3: CLRWRITE The control signal CLRWRITE is activated when the

    condition E T3 is active.

  • EECC550 - ShaabanEECC550 - Shaaban#22 Lec # 1 Winter 2001 12-4-2001

    Computer Architecture Vs. Computer OrganizationComputer Architecture Vs. Computer Organization The term Computer architecture is sometimes erroneously restricted

    to computer instruction set design, with other aspects of computerdesign called implementation.

    More accurate definitions:

    Instruction set architecture: The actual programmer-visibleinstruction set and serves as the boundary between the softwareand hardware.

    Implementation of a machine has two components:

    Organization: includes the high-level aspects of a computersdesign such as: The memory system, the bus structure, theinternal CPU unit which includes implementations of arithmetic,logic, branching, and data transfer operations.

    Hardware: Refers to the specifics of the machine such as detailedlogic design and packaging technology.

    In general, Computer Architecture refers to the above three aspects:

    1- Instruction set architecture 2- Organization. 3- Hardware.

  • EECC550 - ShaabanEECC550 - Shaaban#23 Lec # 1 Winter 2001 12-4-2001

    Instruction Set Architecture (ISA)Instruction Set Architecture (ISA)... the attributes of a [computing] system as seen by theprogrammer, i.e. the conceptual structure and functionalbehavior, as distinct from the organization of the data flowsand controls the logic design, and the physicalimplementation. Amdahl, Blaaw, and Brooks, 1964.

    The instruction set architecture is concerned with:

    Organization of programmable storage (memory & registers): Includes the amount of addressable memory and number of available registers.

    Data Types & Data Structures: Encodings & representations.

    Instruction Set: What operations are specified.

    Instruction formats and encoding.

    Modes of addressing and accessing data items and instructions

    Exceptional conditions.

  • EECC550 - ShaabanEECC550 - Shaaban#24 Lec # 1 Winter 2001 12-4-2001

    Computer Instruction SetsComputer Instruction Sets Regardless of computer type, CPU structure, or

    hardware organization, every machine instruction mustspecify the following:

    Opcode: Which operation to perform. Example: add,load, and branch.

    Where to find the operand or operands, if any: Operandsmay be contained in CPU registers, main memory, or I/Oports.

    Where to put the result, if there is a result: May beexplicitly mentioned or implicit in the opcode.

    Where to find the next instruction: Without any explicitbranches, the instruction to execute is the next instructionin the sequence or a specified address in case of jump orbranch instructions.

  • EECC550 - ShaabanEECC550 - Shaaban#25 Lec # 1 Winter 2001 12-4-2001

    Instruction Set Architecture (ISA)Instruction Set Architecture (ISA)Specification RequirementsSpecification RequirementsInstruction

    Fetch

    Instruction

    Decode

    Operand

    Fetch

    Execute

    Result

    Store

    Next

    Instruction

    Instruction Format or Encoding: How is it decoded?

    Location of operands and result (addressingmodes): Where other than memory? How many explicit operands? How are memory operands located? Which can or cannot be in memory?

    Data type and Size. Operations

    What are supported Successor instruction:

    Jumps, conditions, branches. Fetch-decode-execute is implicit.

  • EECC550 - ShaabanEECC550 - Shaaban#26 Lec # 1 Winter 2001 12-4-2001

    General Types of InstructionsGeneral Types of Instructions Data Movement Instructions, possible variations:

    Memory-to-memory.

    Memory-to-CPU register.

    CPU-to-memory.

    Constant-to-CPU register.

    CPU-to-output.

    etc....

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