cmos photonics for ultra-dense...

CMOS Photonics for Ultra-dense Communication

Vladimir StojanovićUniversity of California, Berkeley

Milos Popović (Boulder), Rajeev Ram, Jason Orcutt, Hanqing Li (MIT), Krste Asanović (UC Berkeley)

Jeffrey Shainline, Christopher Batten, Ajay Joshi, Anatoly Khilo

Mark Wade, Karan Mehta, Jie Sun, Josh Wang

Chen Sun, Sen Lin, Michael Georgas, Benjamin Moss, Jonathan Leu

Yong-Jin Kwon, Scott Beamer, Yunsup Lee, Andrew Waterman, Miquel Planas, Rimas Avizienis, Henry Cook, Huy Vo

Roy Meade, Gurtej Sandhu and Micron Fab12 team (Zvi, Ofer, Daniel, Efi, Elad, …)

DARPA, Micron, NSF, BWRC

IBM Trusted Foundry

Acknowledgments

Slide 2

More-than-Moore perspective

World’s first 60GHz CMOS AmplifierNiknejad & Brodersen

One of the first CMOS radiosRudell & Gray

1997

2004

2012

World’s first SiPhotonic transmitter in 45nm SOIStojanovic, Popovic, Ram

Enhanced CMOS enables new applications

Inductors in IC processNguyen & Meyer1990

3

Thin BOX SOI CMOS Electronics Bulk CMOS Electronics

<150 nm SiO2

Our work: Monolithic CMOS photonic integration

4

9Si and polySi waveguide formation

5

Slide 5

Si waveguide

polySi waveguide

• Each λ carries one bit of dataBandwidth Density achieved through DWDMEnergy-efficiency achieved

through low-loss optical components and tight integration

Integrated photonic interconnects

Slide 6

Single channel link tradeoffs

10-dB

15-dB

Loss

5-fF 25-fFRx Cap7

512 Gb/s aggregate throughput

assuming 32nm CMOS

Georgas CICC 2011

Laser energy increases with data-rate

Limited Rx sensitivity

Modulation more expensive -> lower extinction ratio

Tuning costs decrease with data-rate

Moderate data rates most energy-efficient

Need to optimize carefully

8

DWDM link efficiency optimization

Optimize for min energy-cost

Bandwidth density dominated by circuit and photonics area (not coupler pitch)

Slide 9

Photonic-Interconnected DRAM (PIM)

Towards an Optical DRAM System

[ISCA 2010]

EOS22 Test ChipHigh Performance 45nm SOI

Micron D1L Test ChipPower-optimized0.22µm Bulk

70M transistors1000 optical devices

DARPA POEM

2M transistors1000s optical devices

6m

m

5m

m

Slide 10

World’s First Processor to Communicate with Light (EOS22)

Slide 11

submitted to Nature – August 2015 – please keep confidential – funded in part by DARPA POEM program, Stojanovic, Asanovic, Popovic, Ram

Silicon-Photonic components integrated directly on the chip

[Sun, Wade, Lee, Orcutt et al. Nature 2015]11

Processor Cores – 45nm SOI

RISC-V open ISA

Scalar-vector cores - Boot Linux

0.2-1.35GHz, 4-16 GFlops/W

Slide 12

0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.2015.8 12.8 10.6 8.7 7.1 5.7 4.6 3.7 3.1 2.6 2.1 1.6 20016.7 14.0 11.6 9.6 7.9 6.4 5.3 4.3 3.6 3.0 2.4 1.9 250

14.9 12.4 10.3 8.6 7.0 5.8 4.8 4.0 3.3 2.8 2.2 30015.6 13.0 10.9 9.1 7.5 6.2 5.2 4.3 3.7 3.0 2.4 350

13.6 11.3 9.6 7.9 6.6 5.5 4.7 3.9 3.3 2.6 40014.1 11.8 9.9 8.3 6.9 5.8 4.9 4.2 3.5 2.8 450

12.2 10.3 8.6 7.2 6.1 5.2 4.4 3.7 3.0 50012.5 10.5 8.8 7.5 6.3 5.4 4.5 3.8 3.1 550

10.8 9.1 7.7 6.5 5.6 4.7 4.0 3.3 60011.0 9.3 7.9 6.7 5.8 4.9 4.2 3.3 65011.2 9.5 8.1 6.9 5.9 5.0 4.3 3.5 70011.4 9.7 8.3 7.1 6.1 5.2 4.4 3.6 750

9.8 8.4 7.2 6.2 5.3 4.5 3.6 8008.6 7.4 6.4 5.4 4.6 3.7 8508.7 7.5 6.5 5.5 4.7 3.8 9008.8 7.6 6.6 5.6 4.8 3.9 950

7.3 6.6 5.7 4.8 4.0 10006.7 5.7 4.9 4.0 1050

5.8 5.0 4.1 11005.9 5.0 4.2 1150

5.1 4.2 12005.1 4.3 1250

4.2 13001350

Frequency (MH

z)

Vdd (V)

Not Operational

Gflops/W

[Lee ESSCIRC 2014]

Best waveguide losses ever reported in a sub-100nm production CMOS line

13

470nm width

700nm width

Key Device Components

Slide 14


Integrated Heater

Drop Waveguide

Output Waveguide

Modulator Microring

Input Waveguide

[Shainline OL 2013, Wade OFC 2014]


Slide 15


SiGe from PMOS strain engineering used in Photodetectors

SiGe Photodetector

Waveguide

Waveguide Taper

[Orcutt 2013, Alloatti APL 2015]


Slide 16


Vertical couplers

Waveguide Taper

Diffraction GratingWaveguide

[Wade OIC 2015]

Transmitter

Driven by a CMOS logic inverter (1.2Vpp)

5 Gb/s data rate at ~30fJ/b with >6dB extinction ratio, 3dB insertion loss

Up to 12 Gb/s with 2-3dB extinction

InTransmit Site 50um

PRBS31

8:1

In/Out Grating

Couplers

VBIAS

Modulator Driver

Modulator

[Wade OFC 2014][Sun VLSI 2015]

Slide 17

Receiver

Low parasitics from monolithic integration enable single-stage 5kΩ TIA receiver

10 Gb/s operation at 290 fJ/bit with 8.3uA sensitivity

VPD

φ

φ

Clock Buffers

OutA

OutB-

+Dummy TIA

TIA

5k Ω

5k Ω

Photo-

detector

-

+

ReceiverReceive Site 50um

BER Checker

2:8

Input Grating Coupler

[Georgas VLSI 2014]

Slide 18

5 Gb/s Chip-to-Chip Link

Rx Out A

Rx Out B

Chip 1

PRBS31

8:1

Thermal Tuner

PD Tx

Chip 2

BER Check

2:8

PD

RxOptical

Amplifier1189nm

Laser

3.8 dBm

-0.2 dBm

-3.2 dBm

-10.5 dBm

-14.5 dBm

-7.2 dBm

0.8 dBm

-5.9 dBm-3.2 dBm 9.65uA

2.04uA

Bit 1

Bit 0-9.9 dBm

Laser Power

Bit 1

Bit 0

Time [ps]

Decis

ion T

hre

shold

[uA

]

0 50 100 150 200

-2

0

2

1e-0011e-0021e-0031e-0041e-0051e-0061e-0071e-0081e-0091e-010<1e-010

Slide 19

“zero-change” monolithic competitive with state-of-the-art heterogeneous platforms

680 fJ/bit, 14mW optical power [Zheng PTL 2012**]

5 Gb/s Link Efficiency Summary

Slide 20

*Includes all closed-loop circuits + 0.5 nm tuning power **0.5nm tuning power only

662 fJ/bit for circuits

Thermal Tuning*275 fJ/bit (42%)

Receiver357 fJ/bit (54%)

Optical power: 3.6mW (13mW extrapolated without amplifier)

Modulator Driver30 fJ/bit (5%)

Not using our best identified devices

1dB loss couplers [Wade, OIC 2015] (current ones are 4dB)

5-10x better photodetector (0.1-0.2 A/W photodetector)

Expect to obtain >40x smaller laser power (65fJ/b optical)

5 Gb/s Link Efficiency Summary

Slide 21

662 fJ/bit for circuits

Thermal Tuning*275 fJ/bit (42%)

Receiver357 fJ/bit (54%)

Optical power: 3.6mW (13mW extrapolated without amplifier)

*Includes all closed-loop circuits + 0.5 nm tuning power

Modulator Driver30 fJ/bit (5%)

560 fJ/bit for laser – wall-plug**

**11.6% QD laser wall-plug efficiency

DWDM Transceiver Banks

11 rings coupled to same waveguide

200 GHz channel spacing with 3 THz FSR, >30dB channel isolation Slide 22

Tx and Rx DWDM Transceiver Banks

Slide 23

-16

-14

-12

-10

-8

-6

-4

-2

0

1170 1172 1174 1176 1178 1180 1182 1184 1186 1188 1190

Tra

nsm

issi

on [

dB]

Wavelength [nm]

01

23

45 6

78

9 10

0

12 3

4

Tx

Rx

-12

-10

-8

-6

-4

-2

0

1170 1172 1174 1176 1178 1180 1182 1184 1186 1188 1190

Tra

nsm

issi

on [

dB]

Wavelength [nm]

0 1

2 34 5

6

78 9

100

9 10

Advanced lithography enables tight ring resonance control

11 x 8 Gbps Tx Demonstration

11 rings, each demonstrating 8 Gbps modulation Independently testing one at a time Potential for 88 Gb/s on a single fiber/waveguide Each ring is auto-locked

Slice 8 Slice 9 Slice 10

Slice 4 Slice 5 Slice 6 Slice 7

Slice 0 Slice 1 Slice 2 Slice 3

>8 Gb/s limited by duty-cycle distortion of off-chip clock source

Slide Slide 24

cmos photonics for ultra-dense...

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