isscc 2008 press kit

®

2008

PRESS KIT

ISSCCVISION STATEMENT

The International Solid-State Circuits Conference is the foremost global forum forpresentation of advances in solid-state circuits and systems-on-a-chip. TheConference offers a unique opportunity for engineers working at the cutting edgeof IC design and use to maintain technical currency, and to network with leadingexperts.

TABLE OF CONTENTSISSCC 2008 – EXECUTIVE SUMMARY ..................................................................................................................1

ACTIVITIES AT ISSCC 2008 ............................................................................................................................................3CONFERENCE THEME......................................................................................................................................................4SIGNIFICANT RESULTS ..................................................................................................................................................5

ISSCC 2008 – CONFERENCE OVERVIEW ............................................................................................................9EVENTS..........................................................................................................................................................................11PAPER STATISTICS........................................................................................................................................................12PLENARY SESSION ......................................................................................................................................................13TECHNICAL HIGHLIGHTS ..............................................................................................................................................15EVENING SESSIONS......................................................................................................................................................20Short Course..................................................................................................................................................................21Tutorials ........................................................................................................................................................................22CIRCUIT-DESIGN FORUMS............................................................................................................................................23

ISSCC 2008 – ANALOG..................................................................................................................................................25OVERVIEW......................................................................................................................................................................27FEATURED PAPERS........................................................................................................................................................29Special-Topic Session GREEN ELECTRONICS: ENVIRONMENTAL IMPACTS, POWER, E-WASTE....................34Tutorial FUNDAMENTALS OF CLASS-D AMPLIFIER OPERATION & DESIGN ............................36Forum DIGITALLY-ASSISTED ANALOG & RF CIRCUITS ..........................................................37

ISSCC 2008 – DATA CONVERTERS ........................................................................................................................39OVERVIEW ....................................................................................................................................................................41FEATURED PAPERS........................................................................................................................................................43Special-Topic Session UNUSUAL DATA-CONVERTER TECHNIQUES................................................................46Tutorial PIPELINED A/D CONVERTERS: THE BASICS................................................................47Forum DIGITALLY-ASSISTED ANALOG & RF CIRCUITS ..........................................................48Trends............................................................................................................................................................................49

ISSCC 2008 – HIGH PERFORMANCE DIGITAL................................................................................................51

OVERVIEW ....................................................................................................................................................................53FEATURED PAPERS........................................................................................................................................................54Panel CAN MULTI-CORE INTEGRATION JUSTIFY THE INCREASED COST OF PROCESS SCALING?............58Tutorial LEAKAGE REDUCTION TECHNIQUES..................................................................................................59Forum TRANSISTOR VARIABILITY IN NANOMETER-SCALE TECHNOLOGIES ..............................................60Trends............................................................................................................................................................................61

ISSCC 2008 – IMAGERS, MEMS, MEDICAL AND DISPLAY ..................................................................63OVERVIEW ....................................................................................................................................................................65FEATURED PAPERS........................................................................................................................................................67Special-Topic Session HIGHLIGHTS OF IEDM 2007 ..................................................................................................72Special-Topic Session TRUSTING OUR LIVES TO SENSORS? ..................................................................................74Tutorial CMOS TEMPERATURE SENSORS ..........................................................................................75Forum WIDE-DYNAMIC-RANGE IMAGING........................................................................................76Trends............................................................................................................................................................................77

ISSCC 2008 – LOW-POWER DIGITAL ..................................................................................................................81OVERVIEW ....................................................................................................................................................................83FEATURED PAPERS ......................................................................................................................................................84Tutorial SOC POWER-REDUCTION TECHNIQUES ..............................................................................88

ISSCC 2008 – MEMORY ..............................................................................................................................................89OVERVIEW ....................................................................................................................................................................91FEATURED PAPERS ......................................................................................................................................................93Panel PRIVATE EQUITY: FIGHT THEM OR INVITE THEM......................................................100Tutorial NAND MEMORIES FOR SSD ......................................................................................101Forum EMBEDDED MEMORY DESIGN FOR NANOSCALE VLSI SYSTEMS ............................102

ISSCC 2008 – RF ............................................................................................................................................................103OVERVIEW ..................................................................................................................................................................105FEATURED PAPERS ....................................................................................................................................................107Special-Topic Session MEMS FOR FREQUENCY SYNTHESIS AND WIRELESS RF COMMUNICATIONS

(OR LIFE WITHOUT QUARTZ CRYSTALS) ..............................................................112Special-Topic Session FROM SILICON TO AETHER AND BACK! ....................................................................115Tutorial SILICON mm-WAVE DESIGN......................................................................................116Forum ARCHITECTURES AND CIRCUIT TECHNIQUES FOR NANOSCALE RF CMOS ............117Trend............................................................................................................................................................................119

ISSCC 2008 – TECHNOLOGY DIRECTIONS ....................................................................................................121OVERVIEW ..................................................................................................................................................................123FEATURED PAPERS ....................................................................................................................................................125Special-Topic Session MEMS FOR FREQUENCY SYNTHESIS AND WIRELESS RF COMMUNICATIONS

(OR LIFE WITHOUT QUARTZ CRYSTALS) ..............................................................131Tutorial CMOS + BIO: THE SILICON THAT MOVES AND FEELS SMALL LIVING THINGS ......134Forum POWER SYSTEMS FROM THE GIGAWATT TO THE MICROWATT –GENERATION,

DISTRIBUTION, STORAGE AND EFFICIENT USE OF ENERGY ................................135

ISSCC 2008 – WIRELESS...........................................................................................................................................137OVERVIEW ..................................................................................................................................................................139FEATURED PAPERS ....................................................................................................................................................140Special-Topic Session MEMS FOR FREQUENCY SYNTHESIS AND WIRELESS RF COMMUNICATIONS

(OR LIFE WITHOUT QUARTZ CRYSTALS) ..............................................................145Tutorial DIGITAL PHASE-LOCKED LOOPS ..............................................................................148Forum ARCHITECTURES AND CIRCUIT TECHNIQUES FOR NANOSCALE RF CMOS ............149

ISSCC 2008 – WIRELINE ..........................................................................................................................................151OVERVIEW ..................................................................................................................................................................153FEATURED PAPERS ....................................................................................................................................................155Special-Topic Session TRENDS AND CHALLENGES IN OPTICAL-COMMUNICATIONS FRONT-END ............158Tutorial BASICS OF HIGH-SPEED CHIP-TO-CHIP AND BACKPLANE SIGNALING....................160Forum FUTURE OF HIGH-SPEED TRANSCEIVERS ................................................................161Trends..........................................................................................................................................................................162

ISSCC 2008 – PRESS-RELEASE SESSION OVERVIEWS ......................................................................163CONDITIONS OF PUBLICATION ..................................................................................................................................164SESSION OVERVIEWS ................................................................................................................................................165

ISSCC 2008 – PRESS-COPY MATERIALS ........................................................................................................197CONDITIONS OF PUBLICATION ..................................................................................................................................198TABLE OF FEATURED PAPERS ....................................................................................................................................199PRESS COPY ..............................................................................................................................................................203

ISSCC 2008 – CONTACT INFORMATION ..........................................................................................................239TECHNICAL EXPERTS..................................................................................................................................................241GENERAL CONTACTS ..................................................................................................................................................242

ISSCC 2008

Executive Summary

• Activities

• Conference Theme

• Significant Results

© Copyright 2007 ISSCC — Do Not Reproduce Without Permission- 3 -

EXECUTIVE SUMMARY

EXECUTIVE SUMMARYACTIVITIES AT ISSCC 2008

Tutorials presented Sunday, February 3:

� 10 independent lectures presented by experts from each of the ISSCC 2008 Program Subcommittees: Analog, Data Converters, High-Performance Digital, Imagers, MEMS, Medical and Displays, Low-Power Digital, Memory, RF, Wireless, and Wireline.

Advanced-Circuit-Design Forums presented Sunday, February 3 and Thursday, February 7:

� Informal all-day interaction in which circuit experts exchange information on their current research.

Short Course presented Thursday, February 7:

� 4 linked 90-minute lectures given by experts in the field

Technical Paper Sessions presented Monday through Wednesday, February 4 to 6:

� 4 presentations in the Plenary Session on Monday morning

� 31 paper sessions beginning Monday afternoon and continuing through Wednesday afternoon

� 175 regular-length papers

� 62 short papers

Evening Sessions presented on Sunday, Monday and Tuesday evenings:

� 7 Special-Topic Sessions

� 2 Panel Sessions

Social Hours on Monday and Tuesday evenings after the paper sessions.


EXECUTIVE SUMMARY

CONFERENCE THEME

“System Integration for Life and Style”The ISSCC 2008 Conference theme is “System Integration for Life and Style”. Semiconductor technology con-tinues its advance into the nanometer domain, broadening the range of electronics systems being addressed:from enormous processing and storage in computing, to micropower and wireless mobile functions. Increasedintegration of all these capabilities is enabling new and exciting systems which alter our lives and our lifestylesin endless ways. Ultra-low-power-sensor and wireless techniques deliver new tools for advances in medical andlife sciences. Entertainment and computing continue to merge on the desktop. Now, mobile phones are in-creasingly a platform for a whole range of functions, bringing on-line information, finance, security andaudio/video entertainment, changing our lifestyles in ways previously unimagined. The key to these advances isthe integration of all of these functions into sophisticated systems, allowing more processing to fit into tiny pack-ages, and bringing down power consumption to the point that everything can be battery powered in a hand-helddevice. To reap the promised rewards, design and system integration must master all levels of the technologyjigsaw puzzle. With the huge opportunities of nanometre technology, there are also challenges for designers.They must manage both vast complexity in digital domains, and the realization of high performance analog, RFand interface functions with difficult device behavior and low voltage supplies. Contributions are solicited fromauthors to demonstrate ways in which the integration of novel circuit and systems can deliver functions that en-rich the users’ life and style.


EXECUTIVE SUMMARY

SIGNIFICANT RESULTS

Analog

� An op-amp with a 0.33mV offset independent of temperature using a single room-temperature calibration [3.6]

� A 3.6GHz fractional-N PLL with 290fs integrated jitter from 1kHz to 40MHz using quantization-noise cancellation [19.1]

� A 0.5MHz-to-480MHz all-silicon frequency reference with good temperature stability and low jitter [19.6]

Data Converters

� Outstanding power efficiency with Figure-of-Merit of 4.4fj/conversion-step in a Successive-Approximation-Register (SAR) ADC [12.4]

� Data converters are moving into deep submicron with 6 converters in 65nm and the first in 45nm [27.8]

� A low-voltage ADC for a sensor application operates down to 200mV supply [30.8]

High-Performance Digital

� Simultaneous improvements in both single- and multi-thread performance [4.1, 4.2]

� Highest level of integration ever reported (2 billion transistors) [4.6, 4.7]

IMMD

� A single-chip eye tracker offering extremely high frame rates and fast processing for tracking eye movements in real time [2.2]

� A single-chip “brain radio” extracts EEG signals within a specified band as narrow as 5Hz and draws only 8μW from a 2V supply. [8.1]

� An EEG chopper amplifier with 1-GΩ input impedance, 120dB CMRR, and 0.57μVrms total noise, operates in a 0.5 to 100Hz band while consuming 2.3μA from a 3V supply. [8.2]

� Silicon diffusivity, in combination with advanced readout electronics, resulting in a temperature sensor with outstanding performing [32.1]

� A 3-axis accelerometer with ground-breaking power consumption [32.2]


EXECUTIVE SUMMARY

Low-Power Digital

� Micro-architecture and circuit innovations reduce power consumption by 5x of an x86 processor [13.1]

� A 45nm 3.5G baseband and multimedia-application-processor SoC extends the features and services of next-generation mobile phones. [13.2]

� A unique single SoC IC that integrates an image sensor and a collection of powerful processors for image analysis and understanding [16.1]

� Neural-network circuitry mimicking human brain operation is used to implement machine-based object recognition [16.2]

� Subthreshold operation down to 230mV is demonstrated for motion estimation, with excellent power-performance efficiency of 411GOPS/W [16.6]

Memory

� Fastest embedded DRAM macro in bulk CMOS [14.1]

� First GDDR5 DRAM (with quadruple data-rate) developed [14.5]

� First high-volume functional 153Mb SRAM chip at 45nm high-k metal-gate technology [21.1]

� First-time implementation of dynamic SRAM forward-body-bias technique at high frequency [21.1]

� First 45nm SOI SRAM macro for ASIC applications [21.2]

� A 2-bit-per-cell NAND Flash with a remarkable 34MB/s program rate [23.1]

� First-reported NAND-Flash Memory with three-dimensional silicon integration in 45nm lithography [28.3]

RF

� 76-to-95GHz receiver in 65nm digital CMOS [9.1]

� Fractional-THz CMOS frequency sources [26.1, 26.3]

� 60GHz integrated frequency-tripler with quadrature outputs in 90nm CMOS [26.5]

� 60GHz power amplifiers [31.1, 31.2, 31.3]

� �ntegrated quad-band CMOS power amplifier [31.7]


EXECUTIVE SUMMARY

Technology Directions

� A 16mm2 complete wireless sensor-node SoC for smart bandaids is used for vital-sign monitoring in body-area network applications [7.2]

� The smallest Nuclear-Magnetic-Resonance (NMR) system (2500cm3) is used for detection of biomolecules [7.3]

� The first imager (1.1x1.5 mm2) implanted into a human eye, partially restoring vision to a blind patient [7.4]

� A match-size miniature endoscope with high-efficiency image sensor [7.4]

� Mating an RFID tag to a sensor interface [15.1]

� 107 pJ/bit transmission at 100kb/s at a distance of 60cm enables an electronic tabletop [15.4]

� 2.1μW power-management circuit providing greater than 60% efficiency allows body heat to power wireless sensor nodes [15.8]

� A single-chip CMOS technique for the rapid detection of bacteria using the specificity of phages [18.4]

� A combination of RF-MEMS, temperature-compensated silicon MEMS and SoC for an ultra miniaturized 2.4GHz radio [29.1]

� A 52μW wake-up radio at 2GHz enables long lifetime for wireless sensor network radio [29.2]

� 45nm planar bulk-strained CMOS well-suited to RF and mm-wave radios using multigate FinFET technology for better low-frequency analog performance [29.4, 29.8]

Wireless

� The first fully-integrated 14-band MB-OFDM UWB transceiver [6.4]

� State-of-the-art 3G transceiver that eliminates RF filters [10.2]

� Highly integrated extremely-compact GSM radio SoCs in CMOS [10.4,10.5,10.6]

� The first dual-band MIMO CMOS radio SoC for 802.11n wireless LAN [20.2]

Wireline

� A 40Gb/s CMOS Serial-Link Receiver with Adaptive Equalization and CDR [5.2]

� Fully-integrated 10Gb/s IEEE 802.3an-Compliant Ethernet Transceiver in 0.13μm CMOS for 100m UTP Cable [5.5]

� A 27Gb/s Forwarded-Clock I/O Receiver Using an Injection-Locked LC-DCO in 45nm CMOS [25.1]


EXECUTIVE SUMMARY

NOTES

ISSCC 2008

Conference Overview

• Events

• Paper Statistics

• Plenary Session

• Technical Highlights

• Discussion Sessions

• Short Course

• Tutorials

• Advanced-Circuit-Design Forums


CONFERENCE OVERVIEW

EVENTS

TUTORIALS (SUNDAY, FEBRUARY 3, 2008)

� 10 90-minute Tutorials, each taught twice, by circuit experts from the Program Committee, serve to meet attendees’ needs for introductory material in circuit specialties.

ADVANCED-CIRCUIT-DESIGN FORUMS (SUNDAY, FEBRUARY 3, 2008)

� Circuit experts exchange information on their current research in an all-day informal environment.

TECHNICAL SESSIONS (MONDAY TO WEDNESDAY, FEBRUARY 4 TO 6, 2008)

� 4 invited talks presented in the Plenary Session and 237 technical papers presented in 31 Regular Sessions, highlight the latest circuit developments.

EVENING SESSIONS (SUNDAY, MONDAY & TUESDAY, FEBRUARY 3 TO 5, 2008)

� 7 Special-Topic presentations, in which experts provide insight and background on a subject of current importance.

� 2 Panels in which experts debate a selected topic and field audience questions in a semi-formal atmosphere.

SOCIAL HOURS (MONDAY, FEBRUARY 4 AND TUESDAY, FEBURARY 5, 2008)

� Network with experts in a wide range of circuit specialties; meet colleagues in an informal exchange; browse the technical-book exhibits; browse student-design posters!

SHORT COURSE (THURSDAY, FEBRUARY 7, 2008)

� Intensive All-Day Course on a single topic, taught by world-class instructors, can serve to “jump start” a change in an engineer’s circuit specialty.

ADVANCED-CIRCUIT-DESIGN FORUM (THURSDAY, FEBRUARY 7, 2008)

� Circuit experts exchange information on their current research in an all-day informal environment.


CONFERENCE OVERVIEW

PAPER STATISTICSOVERALL:

� 4 papers invited

� 656 papers submitted to ISSCC 2008

� 237 papers accepted, including:

� 101 papers from North America, including � 55 Industry papers� 46 University papers

� 67 papers from the Far East, including � 41 Industry papers� 26 University papers

� 69 papers from Europe, including � 29 Industry papers� 40 University papers

� 32 Sessions, over 3 days

INTERNATIONAL SCOPE:Americas: 42 % (39% 2007)Far East: 28 % (31% 2007)Europe: 29 % (30% 2007)

WIDE COVERAGE:Analog 9% (7% 2007)

Data Converters 10% (7% 2007)High-Speed Digital 7% (13% 2007)

IMMD 11% (12% 2007)Low-Power Digital 6% (6% 2007)

Memory 12% (8% 2007)RF 11% (10% 2007)TD 12% (12% 2007)

Wireless 11% (12% 2007)Wireline 11% (13% 2007)


CONFERENCE OVERVIEW

PLENARY SESSION

1.1 The 2nd Wave of Digital Consumer Revolution: Challenges and OpportunitiesHyung Kyu Lim, Samsung Advanced Institute of Technology

� Online Social Networking grows without bound to share our personal experiences such as “MySpace”,“Facebook” and “Second Life”.

� Nomadic Life Style blurs the boundaries of work and life increasing speed and complexity.

� Cool Excitement enables 3E (Extremely-Exciting-Experience) with 3D UGC (User-Generated- Content) intuitive web-surfing on the large display through active participation wherever and whenever you want.

� Safer and Healthier Life implements real-time monitoring, on-the-spot diagnosis, and emergency paging, using mobile devices for u-health services.

� True Mobile Internet implements mobile WiMAX (Worldwide Interoperability for Microwave Access) for MMS (Multimedia Messaging Service), MMC (Multimedia Multiparty Conference) using multi-modal user interfaces, 3D SoCs/SiPs, and SSDs (Solid-State Drives).

� Smart Home implements a 3D virtual world with ultra-high resolution VoD, and intuitive web-surfing on large displays where you live, using new User Interface and Input Device Technologies, UD Display Technologies, and 3D Technologies.

1.2 Surface and Tangible Computing, and the “Small” Matter of People and Design

Bill Buxton, Microsoft Research

� The rapid evolution of electronic technologies, integration techniques, and fabrication processes, have enabled the rapid development of a wide-range of new interactive products.

� The real significance of these developments, however, is in the inter-relationship with other products of their kind, and the experience and services it engenders. And, it is precisely this user-experience that is so notoriously difficult to get right from a design perspective.

� This presentation looks at the evolution of two different classes of computational devices: large surface-type computational devices and small graspable computational objects.

� It will be demonstrated that these two extremes of the computational spectrum can meet in a seamless integrated experience as illustrated by specific examples and video demos, some of which are based on the Microsoft Surface Computer.

� Implications for circuit designers are discussed.


CONFERENCE OVERVIEW

1.3 Embedded Processing: At the Heart of Life and Style

Mike Muller, ARM

� Embedded processers are used in the vast majority of silicon products − ARM cores are used in 90% of mobile phones.

� As the largest IP supplier to SoC developers, ARM has a unique perspective on the problems of performance, cost, and power for mobile products in nanometer CMOS.

� Nanometer CMOS technology allows great improvements, including more functions, for each chip, but power is an increasing problem.

� Power consumption in the active state increases with the number and speed of the gates, but standby power will get worse due to more leaky transistors, unless special steps are taken.

� We must address these issues head on if we want the usual battery life along with the desired new features.

� This presentation will show how the IC system developer must address the problems at a variety of levels to get the best performance – better circuit cells, better optimization of power to each block, better processor architectures that exploit the complexity available, and better synergy between hardware and software.

1.4 Why Can’t A Computer Be More Like A Brain? Or What To Do With All Those Transistors?

Jeff Hawkins, Numenta

� “Hierarchical Temporal Memory” (HTM), a new theory, explains the behavior of the human neocortex, and provides a framework for building models that can be executed on conventional computers.

� The broad and flexible capabilities enabled by HTM may be an effective means of dramatically advancing artificial intelligence hosted in high-performance computer platforms.

� Research suggests that the structure of the neocortex is hierarchical, and that the emulation of six levels of hierarchy is sufficient to achieve sophisticated recognition and analysis of visual images.

� The brain’s physical structure, like that of the modern microprocessor, constrains how information is stored. To build machines which approach human transaction thruput rates, data will need to be organized in hierarchical memory structures.

� Presently, HTM technology is being explored in traditional computer architectures; the age of intelligent machines may be just beginning, and if so, there will be many opportunities to rethink how integrated circuits may play a leading role.


CONFERENCE OVERVIEW

Technical HighlightsAnalog

� A reconfigurable charge-domain filter chip with CMOS parametric amplifiers that has on-chip gain and bandwidth control [3.2]

� An op-amp with a 0.33mV offset independent of temperature using a single room-temperature calibration [3.6]



� A DC-to-DC converter improves light-load efficiency by 20% by changing the operating frequency while maintaining a predictable noise spectrum [24.4]

� A highly-efficient supply with 10MHz bandwidth for CDMA polar modulators using a hybrid DC-to-DC converter and Class-AB driver [24.8]

Data Converters

� Outstanding power efficiency with Figure-of-Merit of 4.4 fj/conversion-step in a Successive-Approximation-Register (SAR) ADC [12.4]

� New ADC architectures are proposed based on low-gain amplifiers and simple-inverters as amplifiers [27.3, 27.4]


� Very-high sampling rates in a 24GS/s massively-interleaving 6-bit ADC [30.3]


� Digital calibration and correction is widely used to enhance ADC performance [30.3, 30.4, F7]

High-Performance Digital



� Monitoring, understanding, and exploiting manufacturing variability [Session 22]

� Self-correcting processors deal with variation and soft errors [22.1, 22.2]


CONFERENCE OVERVIEW

IMMD


� A new White-RGB color-filter pattern improves low-light imaging capabilities for mobile applications [2.5]


� An EEG chopper amplifier with 1GΩ input impedance, 120dB CMRR, and 0.57μVrms total noise, operates in a 0.5 to 100Hz band while consuming 2.3μA from a 3V supply. [8.2]

� A 10b CMOS scanning-display driver has 75ns settling time and better than 3mV accuracy for 3-inch QVGA LTPS LCDs [8.6]

� Silicon diffusivity, in combination with advanced readout electronics, resulting in a temperature sensor with outstanding performance [32.1]


Low-Power Digital







CONFERENCE OVERVIEW

Memory



� First high-volume functional 153Mb SRAM chip at 45nm high-k metal-gate technology [21.1]



� Most-area-efficient dynamic power management technique with no wake-up-cycle requirement [21.2]

� Novel non-strobed regenerative sense-amplifier that improves access time by 34% in a 45nm SRAM [21.3]


� A 16Gb NAND Flash storing 3 bits per cell [28.1]


RF

� 76-to-95GHz receiver in 65nm digital CMOS [9.1]

� Full or near-full integration of wireless receivers in CMOS [9.1, 9.2, 9.6]

� Phased-array receivers at mm-wave frequencies in CMOS [9.3, 9.4]

� Secure communication-link proof-of-concept using space-domain communication [9.5]

� Discrete-time wideband-receiver architecture with harmonic rejection [17.1]


� Very-low-power and high-quality CMOS integrated VCO [26.2]



� Higher-efficiency LDMOS and CMOS power amplifiers [31.4, 31.5]

� Software-defined transmitter PA concept in CMOS [31.6]

� Integrated quad-band CMOS power amplifier [31.7]


CONFERENCE OVERVIEW

Technology Directions

� A wireless sensor network using wearable 30cm3 nodes with 3-year battery life has been used to study human activity and interaction between people, as a first demonstration of social electronics [7.1].

� A 16mm2 complete wireless sensor-node SoC for smart bandaids is used for vital-sign monitoring in body-area network applications [7.2].

� The smallest Nuclear-Magnetic-Resonance (NMR) system (2500cm3) is used for detection of biomolecules [7.3].

� The first imager (1.1x1.5mm2) implanted into a human eye, partially restoring vision to a blind patient [7.4]

� A match-size miniature endoscope with high-efficiency image sensor [7.4].

� A single-chip complete wireless neural-recording system for neural prostheses consumes only 6mW[7.6].

� The highest-density stimulation array (256x256 stimulation sites on 4x4mm2 silicon) for stimulation of acute brain slices [7.7].

� A textile-integrated healthcare-monitoring chip uses a “fashionable” circuit-board technology [7.8].


� 10pJ/bit transmission at 100kb/s at a distance of 60cm enables an electronic tabletop [15.4]

� Contactless communication using inductive coupling allows data transfer at 11Gb/s [15.7]

� 2.1μW power-management circuit providing greater than 60% efficiency allows body heat to power wireless sensor nodes. [15.8]

� Infrared sensor -array system with Si-lens, with 800μV/°C sensitivity [18.1]



� A 52μW wake-up radio at 2GHz enables long lifetime for wireless sensor network radio [29.2]

� Towards cognitive radios for more-efficient use of UHF spectrum thanks to a power-spectrum analyzer integrated together with a radio [29.3]



CONFERENCE OVERVIEW

Wireless


� A 45nm CMOS 0.6-to-10GHz wideband-receiver front-end [6.7]




� A discrete-time WiFi/WiMAX receiver that enables process-node scaling [20.4]

Wireline



� A 10.3125Gb/s Burst-Mode CDR Circuit Using a Δ∑ DAC [11.4]

� A 90nm CMOS DSP MLSD Transceiver with Integrated AFE for Electronic Dispersion-Compensation of Multi-Mode Optical Fibers at 10Gb/s [11.7]


� An 800MHz 122dBc/Hz-at-200kHz Clock Multiplier Based on a Combination of PLL and Reticulating DLL [25.2]


CONFERENCE OVERVIEW

EVENING SESSIONS

SUNDAY

SE1: Green Electronics: Environmental Impacts, Power, E-Waste

SE2: MEMS for Frequency Synthesis and Wireless RF Communications(or Life without Quartz Crystal)

MONDAY

E1: Private Equity: Fight them or Invite them

SE3: From Silicon to Aether and Back

SE4: Unusual Data-Converter Techniques

SE5: Trusting Our Lives to Sensors

TUESDAY

E2: Can Multicore Integration Justify the Increased Cost of Process Scaling?

SE6: Highlights of IEDM 2007

SE7: Trends and Challenges in Optical Communications Front-End


CONFERENCE OVERVIEW

SHORT COURSE:[Thursday, February 7, 2008]

EMBEDDED POWER MANAGEMENT FOR IC DESIGNERS

COURSE OBJECTIVE: New generations of consumer electronics products consume less power than their predecessors, but the requirement of the power delivery keeps changing in the direction of lower voltage and higher current. Simulta-neously, market pressures dictate that every new generation of a product provide increased functionality at reduced cost, and emerging applications such as RF ID tags and sensor networks require elimination of con-ventional power sources altogether. These trends have caused power management to be a critical issue in modern IC design. The switching regulators predominantly used for DC power conversion in battery-operateddevices introduce switching noise as the current they supply is increased, whereas analog and mixed-signal circuits that use the power become increasingly sensitive to such noise as their supply voltages are decreased.Increasingly, multiple voltage domains, each with different load scenarios, must be supported. Moreover, costminimization often requires as much of the power management circuitry as possible to be implemented in ahighly scaled CMOS technology optimized for digital circuitry. Hence, techniques to convert and use power efficiently are essential for success. This short course explains the fundamental power management issues facedby IC designers and presents state-of-the-art circuit- and system-level techniques for power management. It isintended for both entry-level and experienced engineers.

OVERVIEW:

� The Short Course is offered twice on Thursday, February 7: The first offering is scheduled for 8:00AM to 4:30PM. The second offering is scheduled for 10:00AM to 6:30PM.

� Navigating the Path to a Successful IC Switching Regulator DesignInstructor: Jonathan Audy

� Circuit Techniques for Switching Regulators Instructor: Vadim Ivanov

� Power Reduction and Management Techniques for Digital CircuitsInstructor: Stefan Rusu

� Power/Energy for Autonomous and Ultra-Portable DevicesInstructor: Seth R. Sanders


CONFERENCE OVERVIEW

TUTORIALS:[Sunday, February 3, 2008]

T1: Fundamentals of Class-D Amplifier Operation & Design

T2: Pipelined A/D Converters: The Basics

T3: CMOS Temperature Sensors

T4: SoC Power-Reduction Techniques

T5: Digital Phase-Locked Loops

T6: Leakage-Reduction Techniques

T7: NAND Memories for SSD

T8: Silicon mm-Wave Circuits

T9: CMOS+Bio: The Silicon that Moves and Feels Small Living Things

T10: Basics of High-Speed Chip-to-Chip and Backplane Signaling


CONFERENCE OVERVIEW

FORUMS:[Sunday, February 3, 2008]

F1: Embedded Memory Design for Nanoscale VLSI Systems

F2: Wide-Dynamic-Range Imaging

F3: Architectures and Circuit Techniques for Nanoscale RF CMOS

[Thursday, February 7, 2008]

F4: Power Systems from the Gigawatt to the Microwatt – Generation, Distribution, Storage and Efficient Use of Energy

F5: Future of High-Speed Transceivers

F6: Transistor Variability in Nanometer-Scale Technologies

F7: Digitally Assisted Analog and RF Circuits


CONFERENCE OVERVIEW

NOTES

ANALOG

Subcommittee

• Overview

• Featured Papers

• Evening Session

• Special-Topic Session

• Tutorial

• Forum(co-sponsored by Analog, Data Converters, and RF)


Sessions: 3, 19, 24 [AP18, 52, 68]

ISSCC 2008 – ANALOG

Subcommittee Chair: Bill Redman-White, NXP Semiconductors and University of Southampton, UK

OVERVIEW

MOST-SIGNIFICANT RESULTS

� A reconfigurable charge-domain filter chip with CMOS parametric amplifiers that has on-chip gain and bandwidth control [3.2]

� An op-amp with a 0.33μV offset independent of temperature using a single room-temperature calibration [3.6]



� A DC-to-DC converter improves light-load efficiency by 20% by changing the operating frequency while maintaining a predictable noise spectrum [24.4]

� A highly-efficient supply with 10MHz bandwidth for CDMA polar modulators using a hybrid DC-to-DC converter and Class-AB driver [24.8]

APPLICATIONS AND ECONOMIC IMPACT

� A reconfigurable charge-domain filter with CMOS parametric amplifiers facilitates highly digitized radios [3.2]

� A low-offset op-amp, with offset independent of temperature using only a single room-temperature calibration reduces production-trimming cost [3.6]

� A PLL with quantization-noise cancellation provides low jitter over a wide offset frequency range [19.1]

� An all-silicon frequency reference replacing crystal oscillators reduces the cost of equipment including backplane SERDES [19.6]

� A DC-to-DC Converter which maintains efficiency at light loads, while maintaining a predictable noise spectrum facilitates control of spurious frequencies in mobile radio SoCs [24.4]

� A new hybrid supply regulator with a 10MHz bandwidth and high efficiency improves CDMA polar modulators [24.8]


Sessions: 3, 19, 24 [AP18, 52 68] ANALOG

EVENING SESSION

Green Electronics: Environmental Impacts, Power, E-Waste [SE1]

TUTORIAL

Fundamentals of Class-D Amplifier Operation & Design [T1]

FORUM

Digitally-Assisted Analog & RF Circuits [F7]


Session: 3 [AP18] ANALOGFEATURE

Reconfigurable Filters and Gain Blocks

A Widely-Tunable Reconfigurable CMOS Analog Baseband IC for Software-Defined Radio [3.1]NEC

A Gain-Boosted Discrete-Time Charge-Domain FIR LPF with Double-Complementary MOS Parametric Amplifiers [3.2]Sony

PRESENT STATE OF THE ART

� Reconfigurable filters and gain blocks are needed to support multimode applications such as software-defined radio

� Multimode applications often require a wide range of gains and filtering functions for optimum performance

� Using only fixed filters, multiple parallel filters are required for multimode applications, leading to increased cost, power, and size.

� Configurable filters within current electronic systems use switches between fixed filters, which switches affect the performance of the resulting filter.

NOVEL CONTRIBUTIONS

� Clever use of duty-cycle-modulated transconductors enables frequency and gain tuning [3.1]

� Use of charge-domain techniques to provide a wide variety of gain and filtering functions [3.2]

CURRENT AND PROJECTED SIGNIFICANCE

� Facilitates software-defined radio [3.1, 3.2]

� Cellphones that function in multiple networks and in multiple modes [3.2]



Low-Cost Offset-Drift Trim

A BiCMOS Operational Amplifier Achieving 0.33μV/ºC Offset Drift using Room-Temperature Trimming [3.6]TU Delft; National Semiconductor

PRESENT STATE OF THE ART (THE PROBLEM)

� Amplifier offset drift is often not subject to calibration, and sets the lower limit for the accuracy of a system. Offset-drift trim schemes for MOS input amplifiers often require a costly two-temperature-trim scheme

� MOS-input-amplifier offset drift, unlike bipolar-input-amplifier offset drift, is not minimized when the amplifier’s offset voltage is trimmed to zero

� Calibrating a system for offset drift over temperature is inconvenient and costly

� Current trim schemes that minimize the drift of MOS input amplifiers often require measurements made at two different temperatures, a process which is quite costly

NOVEL CONTRIBUTIONS

� A trim scheme derived from room temperature measurements removes the need for measurements at two temperatures [3.6]


� Lower cost for precision-instrumentation systems [3.6]


Session: 19 [AP52, 53] ANALOGFEATURE

Digitally-Enhanced PLLs and Oscillators

A Low-Noise Wide-BW 3.6GHz Digital ΔΣ Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and QuantizationNoise Cancellation [19.1]MIT

A 0.5-to-480MHz Self-Referenced CMOS Clock Generator with 90ppm Total Frequency Error and Spread-Spectrum Capability [19.6]Mobius Microsystems; University of Utah


� Reducing the cost of modern wireless and wired system-on-chip (SoC) implimentations requires the use of plain-digital CMOS processes, with no support for traditional analog devices widely used in existing PLL designs.

� Crystal references are found today in virtually all electronic equipment. They take significant board area and are fairly costly as external components.

NOVEL CONTRIBUTIONS

� Currently, a hot research area is the development of silicon replacements for crystal references, which are among the few components still left off of SoCs. [19.1]

� Replacing analog-PLL building blocks with digital counterparts results in all-digital-PLLs that can be implemented in the lowest-cost CMOS processes. Furthermore, digital signal-processing techniques begin to be widely used to compensate the non-idealities and variations of nanometer CMOS devices, reducing PLL’s phase noise and spurs. [19.1]

� Advanced digital compensation techniques that cancel the process, temperature, and bias-dependent variations of a free-running oscillator enables the full integration of a self-referenced oscillator, achieving performance close to that of crystals. [19.6]


� Enhanced-purity clock signals will improve the performance of tomorrow’s cellphones and networking equipment [19.1].

� Replacing crystal references and integrating the replacements on silicon will significantly decrease both cost and board area of future electronic equipment [19.6]



Predictable EMI Spectra in Switching Regulators for Any Load

An Auto-Selectable-Frequency Pulse-Width Modulator for Buck Converters withImproved Light-Load Efficiency [24.4]Hong Kong University of Science and Technology


� Pulse-width modulators have fixed noise and EMI spectra and are thus particularly good for powering sensitive electronic devices. However, power efficiency drops with light loads. A variable- frequency modulator can improve the power efficiency, but the noise and EMI spectrum are not predictable.

NOVEL CONTRIBUTIONS

� The frequency of a buck-supply pulse-width modulator is automatically selected to one of a set of pre-defined frequencies depending on the load condition. [24.4]

� The predefined converter-switching frequencies are sub-harmonics of the normal switching frequency, allowing well-defined noise and EMI output spectra with high power efficiency. [24.4]


� Allows increased the standby time of battery-powered radio systems. [24.4]

� Extends running time of handset application modes that require less power (such as MP3 playback). [24.4]



Higher Efficiency for CDMA RF-Power Modules

A 10MHz Bandwidth 2mV-Ripple PA Supply Regulator for CDMA Transmitter [24.8]Arizona State University


� Polar transmitters are commonly used to enhance the efficiency of radio power amplifiers. This type of transmitter requires the supply voltage of the power amplifier to establish the envelope of the transmission.

� For CDMA applications, this envelope-tracking technique requires supply regulators with high bandwidth and high efficiency.

� Linear regulators have high bandwidth, but low power efficiency. On the other hand, switching power converters can achieve high efficiency, but have limited bandwidth.

NOVEL CONTRIBUTIONS

� A parallel combination of a linear regulator and a switching converter improves the bandwidth of a regulator while maintaining high efficiency. The resulting amplifier pushes the bandwidth of the regulator to 10MHz, which tracks the desired envelope to within 0.2%, while providing a maximumefficiency of 82%. [24.8]


� During data and/or voice transmission, a large amount of power is consumed in the PA. Improving the efficiency of the PA is the most effective way to extend talk time in cellphones. Polar transmitters have been used successfully in Bluethooth and GSM/EDGE applications because of their intrinsicly lower bandwidth requirements. [24.8]

� This power-regulator technique will allow polar transmitters, with their intrinsicly higher efficiency and linearity, to be used with wider-band standards like CDMA. Further research still needed for even-higher-bandwidth system such as WCDMA [24.8]


Evening: SE1 [AP12] ANALOG

SPECIAL-TOPIC SESSION

Green Electronics: Environmental Impacts, Power, E-WasteOrganizer: Jan Sevenhans, AMI Semiconductor, Vilvoorde, Belgium

Chair: Rudolf Koch, Infineon, Munich, Germany

OVERVIEWElectronics companies supplying products for automotive and industrial applications provide the electronic“smarts” needed to make the industry green. Such electronic products are needed as the smarts in gas-combustion and hybrid vehicles for control of the powertrain, and engine parameters to reduce gas consumption, and limit pollution to near-zero parts-per-million of carbon dust per kilowatt. Developing elec-tronic sensors to help enforce environmental laws in industrialized nations around the world under UN su-pervision is the next step for the electronics industry. They must provide the technology needed for pollutionmonitoring and control. Worldwide action is needed – in China and the Far East, as well as in Europe and theUSA, and, on all continents – to ensure the future of our planet for all creatures, since the action of the windsand other forces unite the globe. By this means, electronic engineers can help provide answers to challengesprovided by Greenpeace and others, to improve the environment every year.

OBJECTIVE

� To demonstrate that industry is taking the environment seriously as a design factor in new ways such as the use of green packaging, and clean manufacturing processes.

� To show that electronics in vehicles is helping the environment by optimizing operation to reduce fuelconsumption, and that hybrid cars are gradually replacing the traditional combustion-engine direct drivewith electrical drives.

CHALLENGE

� Cleaner more-efficient less-costly semiconductor process technologies are possible: the critical point is the need for early attention, during technology research and development, in order for benign alternatives to be ready for insertion into manufacturing processes.

� The automotive industry is an example of environmental- and power-friendly improvements. Driven by needs such as pollution-reduction and power-saving, the hybrid car came into this world. What is the electronics industry equivalent?


Evening: SE1 [AP12] ANALOG

STRUCTURE

Green Fab and ManufacturingDuane S. Boning, MIT, Cambridge, MACleaner more-efficient less-costly semiconductor process technologies are possible: the critical point is attention, early, during tech-nology research and development, in order for these benign alternatives to be ready for insertion into manufacturing processes. It isthus essential that new processes, new materials, and new tools, be developed simultaneously from a performance, cost, and envi-ronmental point-of-view. This can be illustrated by 3D wafer integration, where some process options for wafer-level bonding can beshown to consume an inordinate amount of energy and material. Currently, alternative bonding and wafer-release processes are beingdeveloped.

Green PackagingGarry Hamming, Amkor, ArizonaThe packaging industry is making the development of Pb-free leadframe packages, Pb-free bump-compositions for flip-chip packag-ing, and Pb-free solder masks, a high priority. Replacing the Pb with environmentally-friendly materials is a manufacturing challenge,but the entire microelectronics industry is moving swiftly in this direction.

Automotive Green ElectronicsMarcos Laraia, AMI Semiconductor, Pocatello, IDEnvironmental regulations and a growing consumer awareness are creating many opportunities for green electronics in the automo-tive market. Trends such as hybrid and electric cars, renewable fuels, improved gas mileage, and emission-reduction goals, all createnew technical challenges for which increasingly complex integrated circuits are required. We will take an under-the-hood look at someof the many ways electronics can be used to lessen the environmental impact of current and future motor vehicles.

Green Aspects of Photovoltaic-Cell Processing and its ApplicationsRobert Mertens, IMEC, Leuven, BelgiumAmongst all semiconductor technologies, photovoltaics has the strongest “ green” image. Therefore, the production of solar cells mustbe extremely environmentally benign. Crystalline silicon solar cells will dominate the photovoltaic market for at least 15 years, and theenvironmental aspects of that technology must, therefore, be considered. The energy consumption of silicon solar cell production hasthe strongest environmental impact, so energy-payback times must be minimized. Recent developments indicate that energy-paybacktimes of 1 year are feasible, if research to minimize the silicon consumption per Watt of solar power continues.

Green Hybrid-Car ElectronicsJustin Ward, Toyota, Gardena, CA“The automobile has been evolving for the past 100 years. Over the course of its evolution, it has seen significant improvements inpower, performance, and other refinements with simultaneous decreases in the industry’s impact on the environment. Following Toy-ota’s principle of KAIZEN (continuous improvement), we continue to push the evolution of the automobile through the use of advancedtechnologies. The introduction of the Prius in 1997 ushered in the hybrid era, providing the ability to better balance performance andthe environment. We will describe the history of hybrid vehicle development from the perspective of Toyota’s visionaries: Sakichi Toy-oda, Kenya Nakamura, and Masanao Shiomi.

Environmental Push for GreenMartin Hojsik, Greenpeace International, Bratislava, Slovak RepublicIs the fastest-growing industry also the fastest-growing problem? Companies must take this challenge seriously. But, to be taken seriously, the environment must become embedded in managements’business models. But engineers are the ones who have to bring this concern into practice. The biggest areas of environmental impor-tance concerning electronics these days are hazardous chemicals, climate, and waste. Decisions on substances to be used, must betaken, based not only on their engineering performance, but also on their impact on the environment and health. Policies like “pre-caution” and “producer responsibility” will have to become more than policies – they should be part of common practice!

RECAPThe Analog Subcommittee is providing an overview of the environmental aspects of the global electronics industry: green manufac-turing, green packaging, green electronics in the automotive industry, green photovoltaic-cell processing, green hybrid-car electron-ics, and the environmental push for green operation in general. Representatives of the electronics industry and of academia join withGreenpeace to review the status of green electronics today, and to look ahead to the roadmap for the future.


Tutorial: T1 [AP4] ANALOG

TUTORIAL

Fundamentals of Class-D Amplifier Operation & DesignBrett Forejt, Texas Instruments, Dallas, TX

OVERVIEWClass-D amplifiers, due to their high efficiencies, are extremely attractive for audio power amplifiers in integratedlow-power applications. In such applications, long battery life and reduced heat are crucial. The conventionalchoices for audio amplifiers have been class-A/AB/B circuits. These classes, while having excellent fidelity, havepoor efficiency. As important as the efficiency is, the fidelity of the sound is even more so. The performance ofClass-D systems has rapidly improved in recent years to rival that of traditional “high-performance” continuoustime amplifiers. This Tutorial will include the following topics:

� How Class-D works, and its applicability

� Advantages and Disadvantages

� Design insights

� Application challenges in large systems

� Performance Optimization

� Fidelity (Noise, Total Harmonic Distortion, Click & Pop, etc…)

SPEAKER BIOGRAPHY

Brett Forejt graduated from Carnegie Mellon University in 1995 with his BSEE and from Oregon State Univer-sity in 1998 with his MSEE. Brett has over 12 years of industry experience in analog and mixed-signal design,starting in 1995 with Hewlett Packard. In 1997 he joined Texas Instruments working in wireless telephony. Brettcontinues to work for Texas Instruments in the High-Performance Analog Division, in the Audio and ImagingProducts group, where he is a Senior Member of the Technical Staff. Brett is a Senior Member of the IEEE, andhas served on the ISSCC Analog Subcommittee since 2005.


Forum: 7 [AP96] ANALOG, RF, DATA-CONVERTERS

FORUM

Digitally-Assisted Analog and RF Circuits

OBJECTIVEThis all-day Forum is geared toward analog and RF designers who deal with deeply-scaled CMOS technologiesand new applications. Cost-reduction and integration opportunities compel designers to use scaled CMOS tech-nologies, which enable integration of large amounts of digital signal processing with low power consumption andsmall area. However, analog/RF designers face the stark reality of working with devices that, while blazingly fast,are not conducive to the tried-and-true circuit techniques and architectures that have enjoyed a decades-long runof success. This creates a pressing need for new architectures for the analog and RF interfaces that exploit theavailability of large numbers of cheap digital devices in schemes to enhance performance and mitigate poorerintrinsic device performance.

AUDIENCE This Forum offers circuit designers and engineering students a panorama of the key limitations to achieving highanalog and RF performance, and it proposes digital performance-enhancement techniques taking advantage ofthe availability of fast small low-power digital signal processing.

SCOPEThe Forum offers seven contributions from experts reporting theoretical analyses and experimental results forRF and analog interfaces based on digitally-assisted approaches. There are talks on the circuit design of RFblocks (LNAs, up and down-converting mixers, VCOs, and PAs), on the analog and mixed-signal baseband blocks(analog filters, pipelined ADCs, delta-sigma modulators, and sensor interfaces).

PROGRAMThe Forum deals with the design of a variety of different types of circuits and systems to give a comprehensiveoverview of the capabilities of digitally-assisted solutions: Larry Larson will summarize digitally-enhanced-linearization and efficiency-enhancement techniques for next-generation RF systems. Robert Staszewski willfocus on recently-developed all-digital and digitally-intensive PLL architectures. The ‘analog’ content of theseblocks is assisted by ultra-fast but inexpensive digital logic, which runs mostly automatically and in the back-ground. Joel Dawson will focus on digitally-assisted power-amplifier linearization techniques. Antonio Di Gian-domenico will deal with wired telecommunications systems, discussing where and why digital-assistance isnecessary, and what are the advantages at the system-level. Maarten Vertregt will focus on digitally-enhancedanalog in Nyquist converters, discussing, in particular, the power/performance constraints. Starting from theapplication trends, he will list the performance-limiting factors, and propose proper calibration techniques. RobertAdams will give an overview of mismatch-shaping and calibration techniques for D/A Converters, including al-gorithms for dynamic element-matching, mismatch-shaping, and background self-calibration, which are ideallysuited for implemenation in scaled technologies. Finally, Andrea Baschirotto will present digitally-assisted so-lutions for large-dynamic-range sensor interfaces.

The Forum will conclude with a panel discussion, where the attendees have the opportunity to ask questions andshare their views.


NOTES

Data Converters

Subcommittee

• Overview

• Featured Papers

• Evening Session

• Tutorial

• Forum

• Trend Charts

(co-sponsored by Analog, Data Converters, and RF)


Sessions: 12, 27, 30 [AP40, 74, 80] DATA CONVERTERS

ISSCC 2008 – DATA CONVERTERSSubcommittee Chair: David Robertson, Analog Devices

OVERVIEW


� Redundancy is used to allow discarding of non-functional blocks or re-tuning of blocks to optimize the performance in different situations. [12.1, 12.2, 30.7, 30.8]

� Outstanding power efficiency with Figure-of-Merit of 4.4 femtojoules in a Successive-Approximation-Register (SAR) ADC [12.4]

� New ADC architectures are proposed based on low-gain amplifiers and simple-inverters as amplifiers[27.3, 27.4]


� Very-high sampling rates in a 24GS/s massively-interleaving 6-bit ADC [30.3]


� Digital calibration and correction is widely used to enhance ADC performance [30.3, 30.4, F7]


� Power-efficiency breakthroughs in Data Converter designs are driven by portable, mobile, and “implantable” applications. [12.1 through 12.8]

� “Digital Calibration” and “Digitally-Assisted Analog” are growing techniques leveraging the very-high density of digital logic in modern small-feature processes [30.3, 30.4, F7]

� New techniques are being developed to address the challenges of deep-submicron integration, a critical requirement for system-on-chip (SoC) Integration [27.8, 30.1, 30.4, 30.8]

� Higher-speed converters address very-high-speed communication applications [30.3]

� ΔΣ architectures continue to achieve higher speeds, higher bandwidths–moving beyond audio and cellphones, to video and broadband communications [27.4, 27.5, 27.6, 27.7]

� Entirely new directions in data-conversion technology are being explored [30.5, 30.6, SE4]



SPECIAL-TOPIC SESSIONUnusual Data-Converter Techniques [SE4]An exploration of new and different approaches to the data-converter problem.

TUTORIALPipelined A/D Converters: The Basics [T2]Covering the basics of one of the fundamental converter architectures, used for 6 to 16 bits, and 1MS/s to 10GS/s.

FORUMDigitally-Assisted Analog and RF Circuits [F7]Picking up where last year’s Special-Topic Sessions left off, this Forum will explore the use of digital calibration and compensation as part of the emerging trend for improving analog and RF circuit performance.


Session: 12 [AP40] DATA CONVERTERSFEATURE

New Benchmarks for Conversion Efficiency for Analog-to-Digital Converters

A 150MS/s 133µW 7b ADC in 90nm Digital CMOS Using a Comparator-Based Asynchronous Binary-Search Sub-ADC [12.3]IMEC; VUB

A 1.9µW 4.4fJ/Conversion-Step 10b 1MS/s Charge-Redistribution ADC [12.4]University of Twente; Philips Research


� For many applications, converters with sufficient dynamic range and bandwidth have been available for a number of years. The emphasis for innovation has been to lower the power and cost, and to make it easier to integrate the converters into large digital “systems-on-a-chip”. The EFFICIENCY of the converter becomes the focus for innovation.

� Shrinking CMOS lithography offers the promise of lower digital power consumption, but poses challenges for analog circuits, particularly those looking for greater dynamic range.

NOVEL CONTRIBUTIONS

� New architectures increase power efficiency, by powering down circuits that are not being used [12.3, 12.4]

� Circuits are designed for low supply voltages, often at 1V or less. [12.3, 12.4]


� Lower power is very valuable for mobile applications, but extremely low power is critical for human-embedded applications such as pacemakers, retinal implants, cochlear implants, and even hearing aids.


Session: 30 [AP80] DATA CONVERTERSFEATURE

New Speed Benchmark for CMOS ADC

A 24GS/s 6b ADC in 90nm CMOS [30.3]Nortel; STMicroelectronics


� 10 to 40Gigabit-per-second optical receivers require very-high-speed digitizers.

� Low cost and a high level of digital integration are desirable, making CMOS implementation necessary.

NOVEL CONTRIBUTIONS

� Time interleaving of lower-speed converters has become a popular technique for achieving higher sample rates. [30.3]

� Interleaving of a staggering 160 SAR converters achieves a 24GS/s sampling rate. [30.3]

� Channel matching by calibration with channel alignment under timing control [30.3]


� An important step in speed improvement for optical transceiver implementation [30.3]

� An important demonstration of how far the principle of interleaving can be taken. [30.3]


Sessions: 12, 27, 30 [AP40, 74, 80] DATA CONVERTERSFEATURE

“Converters Downsize”

Data Converters Continue to Convert to Deep Submicron


� Technology advances in digital circuits are often driven by shrinking lithography, enabling higher speeds, lower power, and greater integration. In the analog world, there are penalties along with rewards for deeper submicron technologies, namely lower supply voltages which mean lower signal-to-noise ratio for analog signals. As well, transistor leakage and increased 1/f noise introduce new sources of error. Nevertheless, the compelling drive for increased system integration forces designers to develop effective converters in even deeper-submicron technologies.

� This year, at ISSCC 2008, new data-converter designs demonstrate that converters continue to scale-down, with more than 50% of the circuits implemented at 0.13µm or less, and 25% of the designs at 65nm or less.

NOVEL CONTRIBUTIONS

� The first 45nm ΔΣ ADC data converter for voice-band applications [27.8]


� Data-converter designers are working to stay with advanced digital process technologies, and adapt to the challenges of reduced device performance and low supply voltages.

0

2

4

6

8

10

>= 0

Te

0.18um 0.13u90n

Tech

echnology GData C

um-nm

65nm

hnology Gener

eneration foConverter Pa

45nm

ration

or ISSCC 200apers

08


Special: SE4 [AP29] DATA CONVERTERS


Unusual Data-Converter TechniquesCo-Organizers: Venu Gopinathan (Bangalore, India), Boris Murman (Palo Alto, CA)

Chair: Venu Gopinathan

OVERVIEW

� Flash, SAR, ΔΣ, and pipelined architectures are all well-established approaches to data conversion. But is there a different way to solve the data-converter problem? This Special-Topic Evening session is aimed at addressing 4 alternative approaches. The first tries to avoid explicit feedback for charge transfer. The second explores the use of optics as a means for getting ultra-precise timing. Data conversion without aliasing (and hence with smaller in-band quantization noise) is addressed by the third presentation. Fourth, time-to-digital-conversion is described as a means to survive ultra-short-channel CMOS-technology limitations.

OBJECTIVE

� To explore some of the unusual converter techniques that are on the horizon, ones that have a potential to represent significant discontinuities in the field. These techniques address fundamental limitations of conventional approaches, and are not just evolutionary developments.

� To explain design tradeoffs for each of these techniques, and, thereby, spur future research.

STRUCTURE

1. “Comparator and Zero-Crossing-Based ADCs: Challenges and Possible Solutions,” by Harry Lee ( MIT)

2. “Optically-Assisted Analog-to-Digital Conversion”, by David Miller (Stanford University)

3. “Data Conversion and Digital Signal Processing without Sampling”, by Yannis Tsividis (Columbia University)

4. “Time-to-Digital Converters: Opportunities in Nanometer CMOS”, by Baher Haroun (Texas Instruments)

RECAP

� Four experts, one in each of these areas, will share their insights on related issues, and will discuss the various tradeoffs, advantages, and disadvantages, that go with these approaches.


Tutorial: T2 [AP4] DATA CONVERTERS

TUTORIAL

PIPELINED A/D CONVERTERS: THE BASICSAaron Buchwald, Mobius Semiconductor, Irvine, CA

OVERVIEWFor resolutions from 8 to 14 bits, at speeds from 1MS/s to greater than 1GS/s, pipelined ADCs have become aubiquitous ADC architecture. The topic of pipelined converters will be discussed in terms of the following:

� Intuitive spatial analogies for sub-ranged ADCs.

� Architectural tradeoffs.

� Straight-forward explanation of redundancy, which leads directly to understanding of redundant SAR architectures and non-switched-capacitor implementations.

� Capacitor sizing for kT/C and matching considerations.

� Amplifiers and thermal noise.

� Design example

SPEAKER BIOGRAPHYAaron Buchwald is currently CEO and co-founder of Mobius Semiconductor, a privately-held start-up in Irvine,CA. He has 25 years experience in the field of analog-integrated-circuit design. Dr. Buchwald joined Broadcomin 1994 as the first member of the analog group, where he was lead designer for several generations of ADCsand front-end circuitry for products in the cable, satellite, and networking markets. He was later responsible fordevelopment of multi-gigabit serial transceivers for XAUI, CX4, and Fiber Channel. Dr. Buchwald was formerlyan Assistant Professor at the Hong Kong University of Science and Technology (HKUST). Prior to that, he workedat Siemens in Munich, Germany, and Hughes Aircraft Co. in El Segundo CA. Dr. Buchwald has a BSEE from theUniversity of Iowa, and an MS and PhD from the University of California, Los Angeles. He is Co-author of the bookIntegrated Fiber-Optic Receivers, Kluwer, 1995, and was co-recipient of the ISSCC Outstanding-Paper Award in1997 for design of a 10-bit video-rate data converter.


Forum: F7 [AP96] ANALOG, DATA-CONVERTERS, RF

FORUM

Digitally Assisted Analog and RF Circuits

ObjectiveThis all-day Forum is geared toward analog and RF designers that deal with deeply-scaled CMOS technologies,and new applications. Cost-reduction and integration opportunities compel designers to use scaled CMOStechnologies, which enable integration of large amounts of digital signal processing with low power consumptionand small area. However, analog/RF designers face the stark reality of working with devices that, while blazinglyfast, are not condusive to the tried-and-true circuit techniques and architectures that have enjoyed a decades-long run of success. This creates a pressing need for new architectures for the analog and RF interfaces, one thatexploits the availability of large numbers of cheap digital devices to enhance the overall performance, and tomitigate the poorer intrinsic-device performance.

Audience This Forum offers circuit designers and engineering students a panorama of the key limitations to achievinghigh analog and RF performance and it introduces digital performance-enhancement techniques taking advan-tage of the availability of fast small low-power digital signal-processing.

ScopeThe Forum offers seven contributions from experts reporting theoretical analysis and experimental results for RFand analog interfaces based on digitally-assisted approaches: There are talks on the circuit design of RF blocks(LNA, up- and down-conversion mixers, VCOs, and PAs), on the analog and mixed-signal baseband blocks (ana-log filters, pipelined ADCs, ΔΣ modulators, and sensor interfaces).

ProgramThe Forum deals with the design of various types of circuits and systems intended to give a comprehensiveoverview of the capabilities of digitally assisted solutions. Larry Larson will summarize the digitally enhanced-linearization and efficiency-enhancement techniques for next-generation RF systems. Robert Staszewski willfocus on recently developed all-digital and digitally-intensive PLL architectures. The ‘analog’ content of theseblocks is assisted by ultra-fast but inexpensive digital logic that runs mostly automatically and in the background.Joel Dawson will focus on digitally-assisted power-amplifier linearization techniques. Antonio Di Giandomenicowill deal with wired telecommunications systems, discussing where and why digital assistance is necessary,and what are the advantages at the system level. Maarten Vertregt will focus on digitally-enhanced analog inNyquist converters, discussing, in particular, the power/performance constraints. Starting from a review of ap-plication trends, he will list the performance-limiting factors, and propose proper calibration techniques. RobertAdams will give an overview of mismatch-shaping and calibration techniques for D/A converters, including al-gorithms for dynamic element matching, mismatch-shaping and background self-calibration that are ideallysuited for implementation in scaled technologies. Finally, Andrea Baschirotto will present digitally-assisted so-lutions for large-dynamic-range sensor interfaces.

The Forum will conclude with a panel discussion, where the attendees have the opportunity to ask questions andshare their views.


TREND CHARTS DATA CONVERTERS

High Efficiency is the Key in ADC DesignThe bandwidth (BW) and the signal-to-noise-and-distortion ratio (SNDR) of an ADC are two key performance metrics for ADCs. ADC designers are challenged to achieve the highest performance at the lowest-possible powerdissipation (P). Hence, the power dissipation is the 3rd key parameter in evaluating ADC performance. In orderto compare different designs, a single graph is generated by plotting the P/(2xBW) [in Joules] against SNDR [in dB].

+ ISSCC 1997-2007� High-Efficiency

Converters


TREND CHARTS DATA CONVERTERS

The Technology for ISSCC 2008 Data Converters is Presented Below:

0

2

4

6

8

10

>= 0

Te

0.18um 0.13u90n

Tech

echnology GData C

um-nm

65nm

hnology Gener


45nm

ration

or ISSCC 200apers

08

Table of ISSCC 2008 Data Converters Developments

0.18µm CMOS 0.13µm CMOS 90nm CMOS 65nm CMOS 45nm CMOS

Paper 12.5 Paper 30.2 Paper 12.1 Paper 12.2 Paper 27.8

Paper 12.6 Paper 12.3 Paper 12.4





Paper 30.1 Paper 30.6


High-Performance

Digital

Subcommittee

• Overview

• Featured Papers

• Evening Session

• Tutorial

• Forum

• Trend Charts


Sessions: 4, 22 [AP20, 64] HIGH-PERFORMANCE DIGITAL

ISSCC 2008 – HIGH-PERFORMANCE DIGITAL

Subcommittee Chair: Samuel Naffziger, AMD, Fort Collins, CO

OVERVIEW




� Monitoring, understanding, and exploiting manufacturing variability [Session 22]

� Self-correcting processors deal with variation and soft errors [22.1, 22.2]


� Increase in single-thread performance reduces software effort and time-to-market [4.1, 4.2]

� Transactional memory lowers the software-productivity barrier to programming multi-core processors[4.1, 4.2]

� Moore’s Law still going strong! [4.6, 4.7]

� Self-correcting processors increase performance, reliability and availability [22.1, 22.2]

EVENING SESSIONCan Multicore Integration Justify the Increased Cost of Process Scaling? [E2]

TUTORIALLeakage-Reduction Techniques [T6]

FORUMTransistor Variability in Nanometer-Scale Technologies [F6]


Session: 4 [AP20] HIGH-PERFORMANCE DIGITALFEATURE

New Processors Push Both Multi-Threaded Throughput and Single-Threaded Performance

A Third-Generation 65nm 16-Core 32-Thread Plus 32-Scout-Thread CMT SPARC®

Processor [4.1]Sun Microsystems

Implementation of a Third-Generation 16-Core 32-Thread CMT SPARC® Processor[4.2]Sun Microsystems


� As continued scaling of process technologies offers more and more transistors per chip, designers are pushing performance through the high throughput of multi-core and multi-threaded designs.

� At the same time, techniques for improving single-threaded performance are still critical.

NOVEL CONTRIBUTIONS

� A 2.3GHz, 400mm2, third-generation chip-multithreaded (CMT) SPARC processor is developed for high performance of both single-threaded and multi-threaded applications. [4.1, 4.2]

� Deep speculation modes with instruction compression enable high instruction-level and memory-level parallelism with low overhead. [4.1, 4.2]

� Sixteen cores are grouped into four-core clusters and together support 32 software threads for maximum throughput. [4.1, 4.2]

� The first implementation of transactional memory in a CPU simplifies programming of multiple threads.[4.1, 4.2]


� The demonstration of highly-threaded cores shows continued improvement in high-throughput computing. [4.1]

� Highly speculative mechanisms show that performance improvements in single-thread applications are still available. [4.1]



Processors Extend Integration and Reliability Limits

A 65nm 2-Billion-Transistor Quad-Core Itanium® Processor [4.6]Intel

Circuit Design for Voltage Scaling and SER Immunity on a Quad-Core Itanium®

Processor [4.7]Intel


� Moore’s-Law scaling enables designers to build increasingly complex and integrated processors, but power and reliability limits threaten to constrain the levels of integration.

NOVEL CONTRIBUTIONS

� A 700mm2 quad-core Itanium® processor integrates 2 billion transistors into a 2GHz, 170W product. This is the first 2 billion+ transistor processor ever reported. [4.6]

� Dynamic voltage and frequency scaling is enabled by monitoring architectural events and deterministically selecting voltage/frequency settings from a predetermined table. Circuits are qualified to operate down to 0.7V supplies, and with carefully-margined pulse generators. [4.6, 4.7]

� Soft-error-hardened circuits protect 99% of the system-interface latches, 30% of the core latches, 34 small register files, and all CAMs. Large register files and caches are ECC-protected. [4.7]


� Successful large CPU integration (21.5mm×32.5mm) demonstrates largest processor design ever, which enables improved performance and functionality. [4.6]

� Table-based voltage and frequency scaling shows viability of dynamic and adaptive power and performance tradeoffs. [4.6]

� Implementation of soft-error protection on latches and register files enables enterprise-class reliability with a relatively modest area and power overhead. [4.7]



Technologies for Self-Correcting Processors

Razor II: In-Situ Error Detection and Correction for PVT and SER Tolerance [22.1]University of Michigan; AMD; ARM

Energy-Efficient and Metastability-Immune Timing-Error Detection and Instruc-tion-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance [22.2]Intel


� Digital state-of-the-art processors currently address increasing variability of the underlying silicon and environmental factors (such as ambient temperature and supply voltage) by adding time-and-voltage safety margins.

� These margins bloat the power budget of processors by over 30%, and reduce performance by a similar amount.

� These inefficiencies in power and performance are increasingly a problem as continued technology scaling increases variation effects.

NOVEL CONTRIBUTIONS

� The first publication at ISSCC of a technique called “Razor” which enables processors to self-correct timing failures. [22.1, 22.2]

� Using this self-correction capability, a novel tuning approach is implemented where voltage and/or frequency margins are dynamically tightened during operation until self-correction commences [22.1, 22.2]

� Methodologies both allow processors to run without safety margins since they can recover from errors, thereby increasing power and performance efficiency. [22.1, 22.2]


� Between 25 and 30% energy efficiency gain is reported, with increased gains expected in future technologies. [22.1, 22.2]


Session: 22 [AP64, 65] HIGH-PERFORMANCE DIGITALFEATURE

Getting a Handle on Process Variation and Degradation

An All-Digital On-Chip Process-Control Monitor for Process-Variability Measurements [22.5]PA Semi

Compact In-Situ Sensors for Monitoring Negative-Bias Temperature Instability Effect and Oxide Degradation [22.6]University of Michigan

A Completely Digital On-Chip Circuit for Local Random-Variability Measurement[22.7]IBM


� Process variation which increases with every new technology node, hurts performance and cost.

� Conservative design techniques are necessary for good yield.

� Necessary margins to guard against variability are not easily understood or measured.

NOVEL CONTRIBUTIONS

� Simple monitoring circuits are introduced that can be incorporated into existing chips with minimal cost [22.5, 22.6, 22.7]


� Monitoring results can be statistically significant and inform future design decisions [22.5]

� Monitoring results can identify margins and help product binning during production testing [22.5, 22.7]

� Monitoring results can help tweak process recipes for better performance [22.5, 22.7]

� Monitoring results can help predict potential future chip failures [22.6]


Panel: E2 [AP63] HIGH-PERFORMANCE DIGITAL

PANEL

Can Multi-core Integration Justify the Increased Cost of Process Scaling?Organizer: Thucydides Xanthopoulos, Cavium Networks, Marlboro MA

Moderator: Don Draper, Rambus, Los Altos CA

OBJECTIVE

� To investigate and debate limits of multi-core integration for general-purpose processors

� To debate whether we are better off with more simple cores or fewer complex cores

� To debate whether we get an acceptable return-on-investment from process scaling

CHALLENGE

� Process scaling is very expensive. Is multi-core integration the right driver?

� Can we harness the computational power of thousands of cores?

� How do we efficiently test highly-integrated multi-core systems?

� How do we provide sufficient memory bandwidth for such systems?

� How do we solve on-chip interconnect challenges?

CONTROVERSY

� Thousands of simple cores or fewer more-complex cores?

� Homogeneous cores or a combination of cores and fixed-function units?

� Higher performance or lower cost and faster time to market?

� What will be the multicore killer application?

� Is single-thread performance important?

� How many cores does the average consumer really need?


Tutorial: T6 [AP6] HIGH-PERFORMANCE DIGITAL

TUTORIAL

Leakage Reduction TechniquesStefan Rusu, Intel Corporation, Santa Clara, CA

OVERVIEWCMOS-technology scaling in the sub-100nm range comes with increased transistor leakage. To continue har-vesting technology-scaling benefits, it is essential for circuit designers and system architects to understand thenature and impact of leakage, its sensitivity to different design parameters, and practical techniques to reduceit. This Tutorial will review process and circuit-design techniques for leakage reduction with examples from 90nmand 65nm designs from industry, as well as academic research. Special emphasis will be devoted to power-gat-ing techniques, the equivalent of clock gating for local-leakage mitigation.

SPEAKER BIOGRAPHYStefan Rusu received the MSEE degree from the Polytechnic University in Bucharest, Romania. His industry ex-perience includes over 15 years with Intel Corporation and 6 years at Sun Microsystems. He is presently a Sen-ior Principal Engineer in Intel’s Enterprise Microprocessor Group leading the technology and special-circuitsdesign activities for the Xeon® MP Processors. He has authored over 75 papers on VLSI circuit technology andholds 30 U.S. patents. He is an IEEE Fellow, a member of the Technical Program Committee for ISSCC, ESSCIRC,and A-SSCC conferences and an Associate Editor of the IEEE Journal of Solid-State Circuits.


Forum: F6 [AP94] HIGH-PERFORMANCE DIGITAL

FORUM

Transistor Variability in Nanometer-Scale Technologies

ObjectiveDesigners of both analog and digital integrated circuits are facing one of the most important and difficult chal-lenges of nanometer-scale integrated circuits, namely transistor variability. Continued advances in transistordensity along a Moore’s-law curve requires designers both to predict and to optimize IC power and performancein the presence of process variations, especially as processes scale to 65nm and below. Some variations are sys-tematic, while others are random—either truly random, or characterized as random because their causes are un-known or too difficult to model. These variations make performance and functionality less predictable, increaseleakage and power dissipation, and thus reduce yield. Combating these effects for integrated circuits that con-tain tens of billions of transistors require dramatic advances in variation-tolerant design techniques.

Audience This Forum is intended for circuit designers and engineering students seeking to understand the nature andsources of process variations, and how to design robust circuits that are tolerant of those variations.

ScopeResearchers from industry and academia will present an overview of process variations and where they comefrom, as well as several methods for coping with them through architectural choices and circuit-design styles,including SRAM designs. Robust design methodologies and their impact on variability-tolerant design will alsobe discussed.

ProgramThe Forum will begin with two introductory presentations on transistor variability. Rich Klein (AMD) will pres-ent an overview of transistor variations and their impact. This overview includes a taxonomy of variations thatencompasses lithography, gate dielectrics, thermal and stress non-uniformities, and environmental effects. LarsLeibmann (IBM) will focus on computational lithography, otherwise known as resolution-enhancement tech-niques, and how they affect design and layout, as well as the opportunities and challenges they present. Next,three speakers will discuss the state-of-the-art in design practices. First, Hisashige Ando (Fujitsu) will discussvariation-tolerance from an architectural perspective, including error detection, tolerance, and redundancy. Sec-ond, Tanay Karnik (Intel) will present variation-tolerance in various static and dynamic circuits and flip-flops, aswell as circuits to detect problems due to variation. Third, Mike Clinton (Texas Instruments) will outline prob-lems and solutions for SRAM design, both in bit cells and peripheral circuits. Finally, Larry Pileggi (Carnegie Mel-lon University) will present methodologies for combating variability. This encompasses the role played byregularity and restricted design rules in overcoming systematic variations, and the benefits of stochastic designand post-manufacturing tuning for scaled CMOS circuits.

The Forum will conclude with a Panel discussion, where the attendees have the opportunity to ask questions andto share their experiences and perspectives.


TREND CHARTS HIGH-PERFORMANCE DIGITAL

TREND CHARTSTTRREENNDD CCHHAARRTTSS

CLOCK FREQUENCY

10

100

1000

10000

1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008

Year

Clo

ck F

requ

ency

(MH

z)

TTRREENNDD CCHHAARRTTSS

Total Power Consumption

0

50

100

150

200

250

1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008

Year

Pow

er C

onsu

mpt

ion

(W)


TREND CHARTS HIGH-PERFORMANCE DIGITAL

TREND CHARTS

Core Count

CHIP COMPLEXITY

1

10

100

1,000

10,000

1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008

Year

ProcessorTransistorsMemoryTransistorsAverage Processor

Average Memory

Imagers, MEMS,

Medical & Displays

Subcommittee

• Overview

• Featured Papers

• Evening Sessions

• Tutorial

• Forum

• Trends


Sessions: 2, 8, 32 [AP16, 32, 84]

ISSCC 2008 – IMAGERS, MEMS, MEDICAL & DISPLAYSSubcommittee Chair: R. Daniel McGrath, Eastman Kodak Co, Rochester, NY

OVERVIEW



� A new White-RGB color-filter pattern improves low-light imaging capabilities for mobile applications[2.5]


� An EEG chopper amplifier with 1-GΩ input impedance, 120dB CMRR, and 0.57μVrms total noise, operates in a 0.5 to 100Hz band while consuming 2.3μA from a 3V supply. [8.2]

� A 10b CMOS scanning-display driver has 75ns settling time and better than 3mV accuracy for 3-inch QVGA LTPS LCDs [8.6]

� Silicon diffusivity, in combination with advanced readout electronics, resulting in a temperature sensor with outstanding performing [32.1]



� Eye-tracker target applications include pointing devices in video games and wearable computing, as well as appliances for disabled people [2.2]

� New color filter enables mobile image sensors to be used in automotive applications and in surveillance applications [2.5]

� Micropower ICs extracting diagnostic signals from the brain enable advanced wearable and implantable medical devices. [8.1, 8.2]

� Mobile displays with high resolution (>200ppi), high color depth, low power dissipation, and low cost,for handheld consumer electronics. [8.6, 8.8]

� Low-cost high-precision temperature sensors [32.1]

� Ultra-low-power high-precision 3-axis accelerometer [32.2]


Sessions: 2, 8, 32 [AP16, 32, 84] IMMD

SPECIAL-TOPIC SESSIONSTrusting Our Lives to Sensors? [SE5]Highlights of IEDM 2007 [SE6]

TUTORIALCMOS Temperature Sensors [T3]

FORUMWide Dynamic-Range Imaging [F2]


Session: 2 [AP16] IMMDFEATURE

Eye Tracker

A 5000S/s Single-Chip Smart Eye-Tracking Sensor [2.2]Yonsei University


� Real-time imaging and signal processing is too expensive for many applications that require high-frame-rate to track movement.

� Applications including pointing devices for video games, wearable computing, and appliances for disabled people, could use eye-movement sensing.

� Current commercial eye trackers are limited in sampling speed to 30 to 60fps which is not enough for most applications.

� For the first time, completely integrated smart CMOS image sensors are becoming available, together with integrated image processing which avoids the problem of transmitting large amounts of data between chips, saving both cost and power.

NOVEL CONTRIBUTIONS

� A single-chip eye tracker offers extremely-high frame rate and fast signal processing for tracking eye movement in real time. [2.2]

� Device tracks the eye-pupil position with a sampling rate of 5000 frames per second, while consuming only 100mW with a 3.3V supply. [2.2]

� An architecture which is scalable from its current 80x60 pixels to a more practical VGA resolution running at 625 frames per second. [2.2]

� A simple expand-and-retract algorithm is used as a countermeasure to glint caused by direct light reflection [2.2]


� This eye-tracker technology will enable low-cost portable pointing devices in video games and wearable computing, as well as appliances for disabled people [2.2]

� We believe that this development will encourage industry to further explore the potential of smart sensors [2.2]



Expanding Imaging Horizons

A White-RGB CFA-Patterned CMOS Image Sensor with Wide Dynamic Range [2.5]Toshiba


� Wide-dynamic-range imagers are required in markets such as surveillance and mobile imaging, but most image sensors today have a very limited dynamic range.

� Pixel-size scaling reduces SNR and dynamic range by limiting the maximum full-well capacity.

� Wide-dynamic-range techniques often suffer from poor color imaging, and cannot be used in color-imaging applications.

NOVEL CONTRIBUTIONS

� A new White-RGB color-filter pattern improves low-light imaging capabilities for mobile applications[2.5]

� Sophisticated multiple-exposure pixel improves the high-light image quality [2.5]

� A low-noise color-processing algorithm enhances color-image quality [2.5]


� This technology will enable mobile image sensors to be used in automotive applications [2.5]

� This technology will enable higher image quality in surveillance and mobile-imaging applications [2.5]



Brainwave Extraction

An 8µW Heterodyning Chopper Amplifier for Direct Extraction of 2µVrms Brain Biomarkers [8.1]Medtronic; MIT

A 200µW Eight-Channel Acquisition ASIC for Ambulatory EEG Systems [8.2]IMEC; KU Leuven


� Small microvolt-level voltage fluctuations in the brain provide information on normal and diseased brain states.

� Detection of weak brain signals is difficult when using low-power integrated circuits.

� The development of low-power ICs to sense and relay such signals is essential for the development of wearable and implantable medical devices.

NOVEL CONTRIBUTIONS

� An amplifier achieves extraction of 2μVrms biomarkers in selected frequency bands relevant to targeted diseases. [8.1]

� An electrode ASIC achieves state-of-the-art power/noise trade-off with a complete system-on-a-chip architecture. [8.2]

� Both ICs represent a leap from basic front-end amplifier circuits to multi-functional diagnostic systems. [8.1, 8.2]


� Wearable and implantable medical-diagnostic equipment. [8.1, 8.2]

� On-chip signal processing using low-power mixed-signal techniques are a key to sensor-system success [8.1]

� Expandable techniques for 1/f noise reduction for high-fidelity measurement in CMOS processes have great potential. [8.1, 8.2]



Display Electronics

A 10b 75ns CMOS Scanning-Display-Driver System for QVGA LCDs [8.6]Analog Devices; UC Berkeley

A Compact Low-Power CDAC Architecture for Mobile TFT-LCD Driver ICs [8.8]Samsung


� Mobile displays using low-temperature polysilicon (LTPS) backplanes have been limited to 8 bits of color depth.

� Increasing demand for mobile displays with more than 16 million colors requires improved LTPS high-speed drivers.

� Mobile displays using amorphous silicon backplanes have been limited to 6 bits of color depth.

� Increasing demand for mobile displays with 16 million colors requires small-form-factor high-resolution DAC architectures.

� Current-driven AMOLEDs require current drivers that program pixels with small emission currents within the available line time.

NOVEL CONTRIBUTIONS

� A 10b CMOS scanning display-driver system with 75ns settling time can drives QVGA mobile displays through three output channels [8.6]

� A novel fast-feedback current-programming method for medium- to large-sized AMOLED displays [8.7]

� A compact linear 10b cyclic CDAC architecture for mobile TFT-LCD displays [8.8]


� Enhanced mobile displays [8.6, 8.8]

� Enhanced medium- to large-size AMOLED Displays [8.7]



Breaking Records in Sensor Performance

A CMOS Temperature-to-Digital Converter with an Inaccuracy of ±0.5OC (3σ) from-55 to 125 OC [32.1]Delft University of Technology

A 1.5µW 1V 2nd-Order ΔΣ Sensor Front-End with Signal Boosting and Offset Compensation for a Capacitive 3-Axis Micro-Accelerometer [32.2]Helsinki University of Technology


� Sensors that measure physical parameters (temperature, acceleration, etc.) will play a crucial role in future electronic systems. Key features of such sensors will be portability, mobility, and low power.

NOVEL CONTRIBUTIONS

� A new principle for temperature measurement is based on thermal diffusivity in silicon. [32.1]

� Record-breaking temperature-sensor performance and device spread in conventional CMOS. [32.1]

� Record-low power consumption. [32.1, 32.3]

� An accelerometer new power reduction of two orders of magnitude. [32.2]

� Accelerometer measures acceleration in three directions simultaneously. [32.2]


� The new method of applying thermal diffusivity in silicon to convert temperature into a digital signal, never been used before, opens a complete new world of applications. [31.1]

� Sample measurement of acceleration in 3 dimensions is a breakthrough application driver. [32.2]


Special: SE6 [AP60, 61] IMMD


Highlights of IEDM 2007Organizer: Albert Theuwissen, Delft University of Technology, and Harvest Imaging, Bree, Belgium

Chair: Roland Thewes, Qimonda, Munich, Germany

OVERVIEWCircuit-device interaction plays an increasingly important role in advanced CMOS technologies, so that, for example, powerand leakage aspects must be considered by circuit designers, as well as in the technology-development process. In thissession, four papers presented at the International Electron Device Meeting (IEDM) in December, 2007, are highlighted toallow the circuit-design community to discuss record performance opportunities and challenges which arise from ad-vanced and extended CMOS processes.

PRESENTATIONS“Localized SOI Technology : An Innovative Low-Cost Self-Aligned Process for Ultra-Thin Si-Film on Thin BOX

Integration for Low-Power Applications”

S.Monfray1, M.P.Samson1, D.Dutartre1, T.Ernst2, E.Rouchouze1, D.Renaud2, B.Guillaumot1, D.Chanemougame1, G.Rabille1,S.Borel2, J.P.Colonna2, C.Arvet1, N.Loubet1, Y.Campidelli1, J.M.Hartmann2, L.Vandroux2, D.Bensahel1, A.Toffoli2, F.Allain2,A.Margin1, L.Clement3, A.Quiroga1, S.Deleonibus2, T.Skotnicki11STMicroelectronics, Crolles, France; 2CEA LETI MINATEC, Grenoble, France; 3NXPSemiconductor, Crolles, France

Power consumption will be a major issue at the 32nm technology node and below. Bulk silicon devices suffer from short-channel effects and high leakage currents, which limit minimum achievable stand-by power. But fully-depleted SOI offerspower-saving advantages. STMicroelectronics researchers demonstrate the first successful integration of localized SOI de-vices — with a HfO2/TiN gate stack — on dedicated areas of bulk-CMOS substrates. The integration technique is a low-cost approach based on SON technology, where a buried sacrificial SiGe layer can be removed directly from the edges ofthe active area in a self-aligned process, to form an entire fully-depleted structure isolated from the substrate. Devices withgate lengths down to 32nm are demonstrated on a 6nm Si film, allowing control of off-current down to 0.1nA/μm. In ad-dition, the technology is fully co-integrable with bulk devices, and is also compatible with alternative substrate technolo-gies, such as direct silicon bond, opening the door to enhanced SoC architectures.

“A 32nm CMOS Low-Power SoC Platform Technology for Foundry Applications with Functional High-Density SRAM”

Shien-Yang Wu, J.J. Liaw, J.Y. Cheng, C.Y. Lin, M.C. Chiang, C.K. Yang, C.W. Chou, K.H. Pan, C.H. Yao, M.Y. Liu, L.C. Hu,C.H. Chang, S.Y. Chang, P.Y. Tong, Y.L. Hsieh, K.C. Ku, K.C. Lin, L.Y. Yeh, C.W. Chang, H.J. Lin, C. Chang, K.S. Chen, C.C. Chen, S.M. Cheng, S.H. Yang, Y.M. Sheu, M.T. Yang, H.C. Tseng, K.T. Huang, T.L. Lee, S.C. Chen, S.M. Jang, Y.C. See,M.S. Liang, Taiwan Semiconductor Manufacturing Company, Hsin-Chu, Taiwan,

For consumer-electronics applications, semiconductor foundries need the capability to provide customers with advanceddigital and analog functions, combined with high-density embedded memories. TSMC researchers describe a state-of-the-art 32-nm low-power CMOS technology platform for mobile SoC applications that integrates the smallest fully-functional2-Mb SRAM test chip ever built (0.15μm2 6-T SRAM cells); low-standby-power transistors; analog/RF functions, and 10layers of copper/low-κ interconnect. The technology platform is optimized for low power, high density, manufacturability,and cost. Transistors with 30nm gate lengths achieve drive currents of 700/380 μA/μm at 1.1V, and off-state leakage cur-rent of 1 nA/μm, for nMOS and pMOS, respectively.


Special: SE6 [AP60, 61] IMMD

“Record RF Performance of 45 nm SOI CMOS Technology”

Sungjae Lee, B. Jagannathan, S. Narasimha, A. Chou, N. Zamdmer, J. Johnson, R. Williams, L. Wagner, J. Kim, J.-O. Plouchart, J. Pekarik, S. Springer, G. FreemaneeIBM, Essex Junction, VT

Exotic compound semiconductors tend to be used in high-speed RF (radio-frequency) applications, such as millimeter-wave digital and analog systems-on-a-chip. But, the industry continually tries to find ways to extend familiar low-cost sil-icon CMOS technology to these applications. A CMOS process known as silicon-on-insulator (SOI) yields very fast devices,but suffers from floating-body and parasitic electrical effects. IBM researchers describe how they overcome these prob-lems to achieve record high-speed performance in a 45nm SOI microprocessor technology. They demonstrate world-record peak transition frequencies (ƒT) of 485 GHz and 345 GHz for floating-body p-FET and n-FET devices, respectively.They employ a notched-body contact layout that significantly reduces parasitic capacitance and gate-leakage current, thusimproving RF performance. The 45nm SOI process also featured a 1.15nm gate oxide, dual stress-nitride liners, eSiGe pFET,advanced activation annealing, and SMT.

“A 45nm Logic Technology with High-κMetal-Gate Transistors, Strained Silicon, 9 Cu-Interconnect Layers,193nm Dry Patterning, and 100% Pb-Free Packaging”

K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Buechler, A. Cappellani, R. Chau, C.-H. Choi, G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He, J. Hicks, R. Huessner, D. Ingerly, P. Pain, R. James, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, B. McIntyre, P. Moon, J. Neirynck, C. Parker, D. Parsons,L. Pipes, M. Prince, P. Ranade, T. Reynolds, J. Sandford, L. Schifren, J. Sebastian, J. Seiple, D. Simon, S. Sivakumar, P.Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams, K. ZawadzkiIntel, Hillsboro, OR

In January 2007, Intel took the industry by surprise when it announced that by year-end (2007) it would begin shippingcircuits based on its 45nm process technology. It was the first such announcement by any company, and came much ear-lier than anticipated. The Intel technology offers record drive current and high speed at low leakage, and power levels, andemploys a hafnium-based high-κ gate dielectric and metal gates in a manufacturing-ready process. Intel described key de-tails of this 45nm technology. Highlights include 1nm electrically-thick high-κ dielectrics; dual-band-edge-work-function metal gates; trench-contact-based local routing; third-generation strained silicon; nine layers of copper interconnectwith a low-κ interlayer dielectric; low-cost 193nm dry patterning for critical layers, and lead-free packaging. Intel has usedthe process to manufacture a 153Mb SRAM memory array with an SRAM cell size of 0.346μm2, as well as multiple mi-croprocessors.


Special: SE5 [AP31] IMMD


Trusting Our Lives to Sensors?Organizer: Johannes Solhusvik, Micron, Osto, NorwayChair: Tim Denison, Medtronic, Columbia Heights, MN

OVERVIEWIn this session, we will discuss challenges associated with designing sensors used in life-critical applications.This is a hot topic these days with the rapid increase in applications relying on sensor input, including automo-biles, industrial machines, aerospace, medicine, robotics, etc. No sensor is perfect, with its own signal-to-noiseratio and reliability limitations. So, how do we ensure the safety of these systems?

OBJECTIVE

� To highlight the extraordinary design considerations when building sensor systems suitable for life-crit-ical applications.

� To highlight lessons learned from sensor systems deployed in real applications.

CHALLENGE

� How does one design a chip that is guaranteed not to cause danger to human lives?

� What safety mechanisms can be implemented in silicon to avoid getting into a dangerous situation when/ifthe sensor fails to operate?

STRUCTUREFour renowned speakers from North America, Europe, and the Far East will share their insights on this topic. Theevening will evolve from consideration of ‘established’ technologies all around us to progressively more ‘blue-sky’ applications that are still in early research.

Presentations are:

“Crash Sensor Development Issues in Automotive Electronic Airbag Systems for Passenger Protection”Young-Ho Cho, KAIST, Daejeon, Korea

“Are Novel Sensor Technologies to be Trusted?”Arndt Bußmann, Helion, Duisburg, Germany

“Sensor and Control Algorithm Challenges for Building an Artificial Pancreas”Bill Van Antwerp, Medtronic MiniMed, Northridge, CA

“BrainGate” Sensor for Interfacing Directly to the Brain – Lessons Learned with First ImplantsArto Nurmikko, Brown University, Providence, RI

RECAPThe goal of this Special-Topic is to increase awareness of the challenges associated with designing sensor sys-tems aimed at life-critical applications


Tutorial: T3 [AP5] IMMD

TUTORIAL

CMOS Temperature SensorsKofi Makinwa, Delft University of Technology, Netherlands

OVERVIEWCMOS temperature sensors are everywhere! They are used in CPUs for thermal management, in DRAMs to con-trol refresh rates and in MEMS frequency references for temperature compensation, to name but a few high-vol-ume applications. In this Tutorial, the operating principles of CMOS temperature sensors will be explained, theirmain sources of inaccuracy identified, and suitable remedies, at the device, circuit, and system levels, described.To further illustrate these concepts, the design of a state-of-the-art CMOS temperature sensor with an inaccu-racy of less than 0.1°C over the military temperature range (-55°C to 125°C) will be presented.

SPEAKER BIOGRAPHYKofi A.A. Makinwa is an Associate Professor at Delft University of Technology, Netherlands, where he leads agroup that designs precision analog circuits, ΔΣ modulators, and smart sensors. He holds the B.Sc. (1st ClassHons.) and M.Sc. degrees from Obafemi Awolowo University, Nigeria, an M.E.E. (cum laude) degree from thePhilips International Institute, Netherlands, and a Ph.D. degree from Delft University of Technology. From 1989to 1999 he was a research scientist at Philips Research Laboratories, after which he joined Delft University ofTechnology. He holds nine U.S. patents, has (co)-authored over 60 technical papers, and has given tutorials atseveral conferences, including the ISSCC. Dr. Makinwa is a (co)-recipient of JSSC, ISSCC and ESSCIRC best-paper awards, a recipient of the Veni and Simon Stevin Gezel awards from the Dutch Technology Foundation, anda member of the Young Academy of the Royal Netherlands Academy of Arts and Sciences.


Forum: F2 [AP10] IMMD

FORUM

Wide-Dynamic-Range ImagingOrganizer: Albert Theuwissen, Delft University of Technology, Delft, Netherlands, and Harvest Imaging, Bree, Belgium

OBJECTIVEThe human eye outperforms silicon imagers in terms of power dissipation, image-processing ability, and dynamic range. Thedynamic range of the human eye is around 90dB, while CCD and CMOS imagers can typically achieve 72dB in linear operation.The demand for solid-state image sensors that have a dynamic range far beyond the dynamic range of the human eye is grow-ing rapidly. Potential applications are in medical, automotive and machine-vision areas. Even in consumer devices in which thepixels are shrinking, the dynamic range requirements are stretching technological capabilities. This Forum is organized to con-tribute to a better understanding of dynamic-range issues, and to stimulate creativity in this field.

AudienceThis Forum is intended for people active in imaging and, more specifically, for people involved in the design, fabrication, and ap-plication of imaging systems intended for applications requiring systems with wide dynamic-range. Examples of application areasinclude consumer, security, automotive, industrial, and professional.

ScopeA panel of researchers and key-specialists from academia and industry will review the background of wide-dynamic-range im-aging, and the methods used to realize wide-dynamic-range imaging systems. Not only will the capturing of wide-dynamic-range images be discussed, but also the processing of the data. The Forum will conclude with an overview of applications inwhich wide-dynamic-range imaging plays a key role.

ProgramThe Forum will start with two presentations that give a general overview of what wide-dynamic-range imaging actually means.Bart Dierickx, Caeleste, will introduce the definition of dynamic range and will highlight the difference from signal-to-noise ratio.He will discuss the focus on linear versus non-linear systems, and temporal versus spatial methods. On one hand, wide dynamic-range might look very appealing and simple-to-implement in image sensors, but on the other hand, in many cases, a quite highprice needs to be paid to get wide-dynamic-range options in the imager. Examples involve blooming issues, smear issues, CDSbreakdown issues, and optical issues. These shortcomings will be discussed in the presentation of Ricardo Motta, PIXIM.

The implementation of wide-dynamic-range imaging techniques will be discussed in the two presentations following the morn-ing break. First of all, pixel-level wide-dynamic-range methods will be discussed and compared by Makoto Ikeda, University ofTokyo. Secondly, system-level wide-dynamic-range approaches will be highlighted by Koichi Mizobuchi, Texas Instruments.

A very important aspect of wide-dynamic-range imaging is the processing of the image-sensor’s signals, and the processing ofwide-dynamic-range images. The first topic after lunch will go into the detail of these processing aspects. Erik Reinhard, Uni-versity of Bristol, will be the speaker.

The two last presentations of this technical Forum will focus on applications. The first application presentation by Hyung Ho Yoo,Samsung, will contain more-general information about several application areas, such as, consumer imaging, industrial, secu-rity, and professional. The second presentation by Dirk Hertal, Sensta, will go into depth on automotive applications. It is be-lieved that imaging for automotive applications is one of the key drivers for further developments in wide-dynamic-range imaging.

At the very end of the Forum, all speakers and members of the organizing committee will gather in a Panel Discussion. In thisway, the audience will get a chance to participate and contribute to the Forum in a lively discussion.


Trends IMMD

TRENDS IN IMAGE SENSORS

The CMOS image sensor business is still one of the fastest-growing segments of the semiconductor industry,due to cellphone cameras and other digital imaging applications. The cellphone-camera adoption rate is expectedto be approximately 70% for 2008, and 3G mobile technology is accelerating its utilization of multiple camerasper cellphone. Other digital-imaging markets include traditional markets such as DSC and camcorders, as wellas emerging markets, including Web cameras, security cameras, automotive cameras, and gaming.

In order to maintain market growth in this industry, many barriers must be overcome. These include better imagequality, higher sensor resolution, smaller chip size, lower cost, higher data-transfer rate, higher system-level in-tegration and lower power consumption. The number of technology barriers in each market depends on the tar-get application.

The resolution and miniaturization races have still not ended, and, while the performance requirements stay con-stant, pixel size is scaling down. In order to compete in this race, new innovative technologies are continuouslybeing developed. These include digital optics, wafer-level cameras, and backside illumination processes. Theimportance of digital signal-processing technology in digital cameras continues to grow. This processing is usedto mitigate noise and to compensate for optical limitations. The level of computation per pixel is increasing to1000’s of operations per pixel, and requires high-performance low-power digital solutions for implementation.As well, there is a parallel trend pushing the industry toward higher levels of integration in established markets.

The trends in emerging markets include wider-dynamic-range and faster-read-out cameras. As the required func-tionality and performance of cameras increase, the technological challenges continue to grow rapidly. To con-tinue having the complexity and performance of CMOS image sensors grow at an exponential rate will be a toughtask. But, doing so will enable digital cameras to be used in more aspects of our lives in the coming years.


Trends IMMD

TRENDS IN SENSORS AND MEMS

The boost in performance of integrated MEMS-interface circuitry opens new application fields. The low powerconsumption of 3-axis accelerometer interfaces enables new mobile applications, and the noise performance ofMEMS accelerometers and gyroscopes now meets the requirements of short-range navigation applications andcombinations with RFID tags.

Sensors are rapidly becoming vital parts of many microprocessors and systems-on-chip (SoCs), with transis-tor counts beyond 1 billion. The sensor output is used to compensate for variability, environmental effects, anddrive power management. New sensor and circuitry techniques are required to realize, for example, temperatureand voltage sensors, as supply voltages scale to values below 1V.

Integrated sensors continue to penetrate the worlds of both biology and medicine. Examples include implantablesensing and stimulating chips, DNA sensors, prosthetic vision, neural simulators, neural amplifiers, and evenminiaturized NMR-analysis systems.

Wireless sensor networks are envisioned in applications including large environmental monitoring, traffic mon-itoring, and building control. Power-optimzed sensor systems that combine sensor functions with A/D convert-ers and wireless interfaces on a single chip, are key enabling factors to make wireless sensor networks a reality.


Trends IMMD

TRENDS IN DISPLAYS

Mobile Displays: Mobile displays require high-resolution (>200ppi), embedded smart functions (such as touchscreen, scanner, and fingerprint recognition), high color depth, low power dissipation, and low cost.

AMOLED Displays: The major technical issues for AMOLEDs are compensation methods for non-uniform elec-trical characteristics of the driving TFTs in pixel arrays, the voltage drop in pixel VDD supply voltage, image stick-ing due to OLED degradation, and operating temperature. A fast direct-type current-programming method canresolve the non-uniformity of driving TFTs.


Trends IMMD

TRENDS IN MEDICAL ICs

Extraction of EEG Signals from the Brain: Small, microvolt-level voltage fluctuations in the brain provide infor-mation on normal and diseased brain states. Detection of these weak signals is difficult when using low-powerintegrated circuits. Low-power ICs to extract these signals are essential for the development of wearable and im-plantable medical devices.

On-Chip Microchemistry and Diagnostics: The detection of tiny amounts of a chemical compounds is a keyissue in biological sciences and medicine, and new approaches providing better sensitivity and reduced cost areimportant. A system for time-resolved fluorescence analysis, and a DNA detection array based on cyclic voltam-metry are current developments.

Biometric Sensing for Security: Medical sensors can potentially be applied in more-general consumer applica-tions. An example of a current development is a fingerprint scanner that, to prevent fraud, verifies that tissueimpedance falls in an expected “live” range.

Low-Power

Digital

Subcommittee

• Overview

• Featured Papers

• Tutorial


Sessions: 13, 16 [AP42, 48] LOW-POWER DIGITAL

ISSCC 2008 – LOW-POWER DIGITALSubcommittee Chair: Wanda Gass, Texas Instruments Incorporated, Dallas, Texas

OVERVIEW








� The latest Intel processor dissipates less than 2 Watts and nearly doubles battery life of handheld devices. [13.1]

� A new 3.5G digital basedband chip delivers longer battery life with more advanced features and services for mobile phones. [13.2]

� An integrated image senor and processor provides cost-effective efficient secured image analysis system. [16.1]

� Brain-mimicking Object-Recognition System [16.2]

� Ultra-low-voltage operation of SoCs will enable smart monitors to function for years on a single cell[16.6]

TUTORIALSoC Power Reduction Techniques [T4]


Session: 13 [AP42] LOW-POWER DIGITALFEATURE

x86 Goes Handheld: Breakthrough Reduces Power by 5x

A Sub-1W to 2W Low-Power IA Processor for Mobile Internet Devices and Ultra-Mobile PCs in 45nm High-κ Metal-Gate CMOS [13.1]Intel


� Current x86 (“Intel Architecture”) processors dissipate about 10W of power, making it a significant battery drain in notebooks.

� This high level of power dissipation also requires active cooling (a fan) and large packages.

NOVEL CONTRIBUTIONS

� A variety of micro-architectural and circuit innovations reduces chip activity to a near-minimum of 2 Watts. [13.1]

� A power breakthrough for x86: the power consumption is reduced by 5x but performance remains the same [13.1]

� An advanced 45nm process is a key enabler for low power: at 1.0V, allowing a 2GHz clock and low leakage current. [13.1]


� Power dissipation of less than 2 Watts nearly doubles the battery life in handheld devices [13.1]

� Ultra-low-power x86 chips allow smaller chip packages and passive cooling (no fan), enabling new product categories such as “Mobile Internet Devices” [13.1]

� Eventually, such developments could lead to x86 devices integrated in mobile phones [13.1]


Paper: 13.2 [AP42] LOW-POWER DIGITALFEATURE

An Ultra-Low Power Cell Phone Solution in Advanced45nm Process

A 45-nm 3.5G Baseband-and-Multimedia-Application Processor using AdaptiveBody-Bias and Ultra-Low Power Techniques [13.2]Texas Instruments


� Power is a big challenge, and increasingly more complex as cell phones continue to add advanced functions as technology scales to deeper sub-micron levels

� Advanced low-power techniques are necessary to achieve low-power but add complexity to SoC design

NOVEL CONTRIBUTIONS

� TI 45nm low-power process technology and digital and analog design platform deployed in 3.5G baseband and multimedia processor [13.2]

� Advanced wireless modem supporting multiple cellular standards (HSUPA/HSDPA, WCDMA, EDGE, GPRS, GSM) [13.2]

� High-Performance Multimedia, Multiprocessor engine [13.2]

� SmartReflex™ Performance and Power Management Technologies, fully deployed using body-bias with improvements [13.2]


� Cost-effective, power-efficient design, providing longer battery life [13.2]



Image Analysis and Understanding

iVisual: An Intelligent Visual-Sensor SoC with 2790fps CMOS Image Sensor and205GOPS/W Vision Processor [16.1]National Taiwan University

A 125GOPS 583mW Network-on-Chip-Based Parallel Processor with Bio-InspiredVisual-Attention Engine [16.2]KAIST


� Video sensors and video-analysis algorithms are critical enablers for applications such as surveillance, healthcare, intelligent-vehicle control, and human-machine interface

� Traditional analog-processing solutions cause precision loss and may lack flexibility

� Existing digital-processing solutions suffer from throughput bottlenecks

� Data-privacy invasion is a major concern

NOVEL CONTRIBUTIONS

� A unique single System-on-Chip IC that integrates a video sensor and a collection of powerful processors for Image analysis and understanding [16.1]

� Neural network circuitry mimicking human brain operation is used to enable machine-based object recognition [16.2]


� Cost-effective power-efficient secured image analysis system [16.1]

� Brain-mimicking object recognition system [16.2]



Subthreshold / Ultra-Low-Voltage Architectures: EmergingTrend in Ultra-Low-Power Mobile System-on-Chip Design

A 320mV 56μW 411GOPS/Watt Ultra-Low-Voltage Motion-Estimation Acceleratorin 65nm CMOS [16.6]Intel


� Handheld and ultra-mobile devices emerge with extremely critical active- and standby-power goals in the sub-1mW to 1μW range with moderate performance demands, opening up new architectural and design challenges

� Subthreshold and ultra-low-voltage circuits demonstrate excellent promise for systems-on-chip in this genre, offering a new emerging design trend for future ultra mobile platforms

� Several new design challenges have arisen in the subthreshold regime, which have opened up many new research opportunities

NOVEL CONTRIBUTIONS

� Intel showcases an ultra-low-voltage video motion-estimation accelerator [16.6]

� Subthreshold operation (down to 230mV) is demonstrated, with an excellent power-performance efficiency of 411GOPS/W using several ultra-low-voltage circuit techniques [16.6]


� Ultra-low-voltage operation of SoCs will enable smart monitors to function for years on a single cell[16.6]


Tutorial: T4 [AP5] LOW-POWER DIGITAL

TUTORIAL

SoC Power-Reduction TechniquesPascal Urard, STMicroelectronics, Crolles, France

OVERVIEWPower consumption is, and continues to be the hottest topic for battery-operated portable devices. This Tutorialwill provide a comprehensive overview of the most commonly adopted digital-CMOS leakage-reduction andpower-management techniques, and their realization at all phases of the IC design process, from system archi-tecture to physical implementation. Highlights of the techniques to be discussed are:

� System-level design considerations for low-power

� Voltage / Frequency scaling

� Clock gating

� Power gating

� DFM implications of these Techniques

SPEAKER BIOGRAPHYPascal Urard is currently the manager of High-Level Synthesis at STMicroelectronics in Crolles, France. He isinvolved in the design of high-performance and low-energy solutions for applications in digital communicationsand multimedia, with a special focus on high-speed wireless communications. He received his MS in Electron-ics Engineering from the Institut Supérieur d’Electronique du Nord (ISEN), located in Lille, France, in 1991. Hehas published or participated in 13 IEEE papers, has 10 awarded or pending patents in the domain of signal processing, and is regularly invited to participate in panel sessions on system-level design. He recently joinedprogram committees of various IEEE conferences such as ISSCC, ESSCIRC, and MEMOCODE. He is a technicaladviser to a few large EDA companies working in system-level design.

MEMORY

Subcommittee

• Overview

• Featured Papers

• Evening Session

• Tutorial

• Forum


Sessions: 14, 21, 23, 28 [AP44, 56, 66, 76]

ISSCC 2008 – MEMORYSubcommittee Chair: Hideto Hidaka, Renesas Technology, Itami, Japan

OVERVIEW




� First high-volume functional 153Mb SRAM chip at 45nm high-κ metal-gate technology [21.1]



� Most-area-efficient dynamic power management technique with no wake-up-cycle requirement [21.2]

� Novel non-strobed regenerative sense-amplifier that improves access time by 34% in a 45nm SRAM [21.3]


� A 16Gb NAND Flash storing 3 bits per cell [28.1]



� DRAM embedded with processors in a bulk CMOS process provided by a foundry enhances total system performance [14.1]

� Faster GDDR5 DRAMs enable sensational graphics and video experiences for consumers [14.5]

� SRAM subarray block for a 6MB L2 cache of next-generation 45nm high-κ metal-gate Intel CoreTM2 CPU [21.1]

� SRAM building block for 45nm SOI ASIC library used in next-generation high-performance network applications [21.2]

� Novel sense-amplifier for future-generation SRAM designs to achieve highest performance sense speeds [21.3]

� SRAM macro used in GHz-class sub-1V applications [21.4]

� High-density SRAM product used in network applications [21.6]


Sessions: 14, 21, 23, 28 [AP44, 56, 66, 76]

APPLICATIONS AND ECONOMIC IMPACT (contiuned)

� Ultra-high program rate achieved in multi-level-cell NAND suitable for a wide range of user applications [23.1]

� High-density flash satisfies the growing need for low-cost data storage [28.3]

PANELPrivate Equity: Fight Them or Invite Them [E1]This panel will discuss how private-equity firms are viewed in the semiconductor industry.

TUTORIALNAND Memories for SSD [T7]This Tutorial will discuss NAND flash memory designs for solid-state-disk (SSD) applications and related systems.

FORUMEmbedded Memory Design for Nanoscale VLSI Systems [F1]This Forum will cover a wide range of embedded-memory technologies and related circuits.


Session: 14 [AP44] MEMORYFEATURE

Embedded DRAM Pushes Random-Cycle Time

A 500MHz Random-Access Embedded 1Mb DRAM Macro in Bulk CMOS [14.1]TSMC


� Embedded DRAM macros in SOI have higher-performance than those in bulk CMOS

� A single column-access path is used for read and then write; Thus, write needs to be delayed and bitline held, both limiting the row cycle time

� Half-VCC sensing is generally used

NOVEL CONTRIBUTIONS

� Fastest embedded DRAM macro available in bulk CMOS provides performance comparable with SOI [14.1]

� Separate ports for read and write, and local bitlines isolated from global bitlines are provided so that write and read can start immediately after the sense-amplifier is turned on [14.1]

� Column operation is defined by the state of only the global bitline; No additional timing signals are required to start column operation [14.1]

� Full-VCC sensing is adopted for embedded DRAM macros [14.1]


� Faster embedded DRAM in bulk CMOS makes SoCs more powerful in delivering system performance [14.1]

� Full VCC sensing allows operation with lower VCC in scaled CMOS technologies with reduced power-supply voltages [14.1]

� Shorter row cycle time resulting from fast, bitline-signal development is important for high-speed operation [14.1]



Graphics DRAM Reaches 6Gb/s/pin

A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques [14.5]Samsung


� 4Gb/s/pin is the fastest published data-rate (ISSCC 2007)

� The product chip currently available is GDDR4 (Double data-rate)

NOVEL CONTRIBUTIONS

� First GDDR5 chip developed [14.5]

� A fast-feedback 1-tap decision-feedback-equalizer (DFE) receiver with minimal overhead [14.5]

� A fast-lock and bandwidth-adjusting PLL [14.5]


� For graphics DRAM enhances high-end graphics performance [14.5]

� DRAM enables higher data rates and improves signal integrity [14.5]



First SRAM chips with 45nm High-κ Metal Gate Technology for High-Performance Applications

A 153Mb SRAM Design with Dynamic Stability Enhancement and Leekage Reduction in 45nm High-κ Metal-Gate CMOS Technology [21.1]Intel


� All processes at 65nm, and most at 45nm, are using nitrided- oxide transistors which have a large leakage current that increases as the thickness is reduced

� As processes move from 65nm to 45nm, variation challenges are increasing significantly

NOVEL CONTRIBUTIONS

� First time for 45nm with new high-κ metal-gate for L2-cache CPU applications [21.1]

� Use of dynamic forward-body-bias for SRAM stability enhancement [21.1]

� On-die programmable active-leakage-control circuit [21.1]


� At the 45nm node, usage of high-κ metal-gate CMOS helps to reduce transistor leakage, and enables a path to higher-performance transistors. [21.1]

� Usage of high-κ enables SRAM scaling to meet aggressive CPU performance requirements while significantly reducing the power consumption [21.1]



SRAM Macro in 45nm SOI Technology has Power-Management

A 450ps-Access-Time SRAM Macro in 45nm SOI Featuring a Two-Stage Sensing-Scheme and Dynamic Power-Management [21.2]IBM


� Multi-cycle dynamic power-management using NFET ground control requires large devices that increase area overhead. This also requires wake-up cycles before SRAM access.

� Large differential-data I/O bus causes considerable AC power consumption in high-performance SRAM macros.

� Domino sense-amplifier scheme in SOI using a single supply can no longer meet performance targets given large amounts of random SRAM-cell variation

NOVEL CONTRIBUTIONS

� Single-device PFET-header dynamic power-management scheme with local charge reservoir [21.2]

� Smallest area-overhead (1.8%) scheme which achieves 37% leakage reductions, and does not require wake-up cycles [21.2]

� A two-stage small-signal sense-amplifier scheme using body-contacted SOI devices reduces data-I/O-bus power by 74%. Overall macro power reduction of 58% is achieved. [21.2]


� SOI SRAM macro enables state-of-the-art power specifications and performance at 45nm [21.2]

� Key SRAM building block for 45nm high-performance ASIC library [21.2]

� Embedded SRAM macro competition includes: Intel [21.1], Toshiba [21.4], and Hitachi [21.5]


Session: 23, 28 [AP66, 76] MEMORYFEATURE

NAND Flash Memory Boosts Performance

A 34MB/s-Program-Throughput 16Gb MLC NAND with All-Bitline Architecture in56nm [23.1]SanDisk; Toshiba

A 50nm 8Gb NAND Flash Memory with 100MB/s Program Throughput and 200MB/sDDR Interface [23.4]Micron; Intel

A 16Gb 3b/Cell NAND Flash Memory in 56nm CMOS with 8MB/s Write Rate [28.1]SanDisk; Toshiba


� Multi-level NAND technology supporting 2 bits per cell is commercially available today for NAND Flash in volume production

� 2-bits-per-cell NAND is the most advanced density reported that allows high-performance writing

� 10MB/s is the fastest-reported for an MLC 2-bit-per-cell NAND Flash

� 8Gb is the largest NAND Flash memory reported

NOVEL CONTRIBUTIONS

� A 2-bit-per-cell NAND Flash achieves a remarkable 34MB/s program throughput [23.1]

� NAND Flash achieves 16Gb density with state-of-the-art 56nm lithography [23.1] [28.1]

� NAND Flash achieves an astonishing 100MB/s program throughput and 200MB/s read throughput using DDR interface [23.4]

� First reported NAND Flash featuring 3 bits per cell with 8MB/s program throughput suitable for a large variety of applications [28.1]


� Higher write rate expands the market for NAND Flash applications, and creates new ones [23.1]

� High storage capacity satisfies new application needs [28.1]


Sessions: 23 [AP67] MEMORYFEATURE

Phase Change Memory Goes Multi-Level

A Multi-Level-Cell Bipolar-Selected Phase-Change Memory [23.5]STMicroelectronics; Intel; University of Pavia


� 90nm is the most advanced lithography for phase-change memory

� Phase-change memory currently allows only one bit per cell

NOVEL CONTRIBUTIONS

� Multi-level phase-change memory in advanced 90nm process [23.5]

� First report of multi-level storage in phase-change memory [23.5]

� New design concepts reduce operating current, allowing faster read and write performance [23.5]


� Going multi-level doubles the density and allows a wider offering for the memory market [23.5]

� Phase-change memory enables creative changes in memory subsystems in a wide range of applications [23.5]

� Multi-level capabilities, plus a promise of a long-term scalability, add low-cost attributes available before only in hard-disk drives [23.5]



NAND Flash goes Three-Dimensional

A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory withShared Bitline Structure [28.3]Samsung


� 56nm technology is commercially available today for NAND Flash in volume production

� Density limited by planar occupancy of Flash-memory arrays

NOVEL CONTRIBUTIONS

� Flash fabricated in an advanced 45nm process lithography [28.3]

� Memory density (Megabytes per mm2) boosted by vertically stacking two silicon layers [28.3]

� Innovative circuit and architectural techniques for multi-level-programming-performance boosting [28.3]


� Significant cost reduction for Flash-memory-hungry applications such as in memory cards and solid-state disks [28.3]

� Enables doubling the density of NAND flash offering [28.3]


Panel: E1 [AP30] MEMORY

PANEL

Private Equity: Fight Them or Invite ThemCo-Organizer/Moderator: Sreedhar Natarajan, TSMC Design Technology, Kanata, Canada

Co-Organizer: Nicky Lu, Etron Technology, Hsinchu, Taiwan

OBJECTIVE

� To debate the domination of private-equity (PE) firms in the industry

� To evaluate whether private-equity takeovers of semiconductor companies is good for innovation.

CHALLENGE

� Too much consolidation of the semiconductor companies through private-equity (PE) takeovers.

� Less research and innovation, since focus of PE firms is different

� PE firms’ involvement in semiconductor industry is short-term in order to increase revenue

CONTROVERSY

� Will PE involvement help the semiconductor industry to grow or will it limit growth?

� Will PE involvement hamper venture capital investment in new companies?

� Does consolidation of semiconductor companies hurt competition and increase monopolistic behavior?


Tutorial: T7 [AP7] MEMORY

TUTORIAL

NAND Memories for SSDKen Takeuchi, University of Tokyo, Tokyo, Japan

OVERVIEWAs the cost of NAND flash memory reduces, a lot of attention is being paid to the use of NAND flash for solid-state disk (SSD) for PC applications. To realize a high-performance highly-reliable SSD, it is essential to under-stand SSD from a broad perspective including device, circuit, system-architecture, and operating-system aspects.

To provide a comprehensive view of SSD, this Tutorial covers the following topics:

� NAND device/circuit basic operation

� SSD overview including market, cost, reliability, performance, and power consumption.

� NAND circuit design for SSD

� NAND controller design for SSD

� Operating system for SSD

SPEAKER BIOGRAPHYKen Takeuchi is currently an Associate Professor at the Graduate School of Frontier Sciences and the Electron-ics Engineering Department of the University of Tokyo. He is now working on VLSI circuit design especially foremerging non-volatile memories. He received the B.S. and M.S. degrees in Applied Physics, and the Ph.D. de-gree in Electric Engineering from the University of Tokyo in 1991, 1993 and 2006, respectively. In 2003, he alsoreceived the M.B.A. degree from Stanford University. After joining Toshiba in 1993, he lead Toshiba’s NAND-flash-memory circuit-design effort for fourteen years. He designed six world’s highest density NAND flash memoryproducts including a 0.7μm 16Mbit, 0.4μm 64Mbit, 0.25μm 256Mbit, 0.16μm 1Gbit, 0.13μm 2Gbit, and 56nm8Gbit NAND flash memories. He holds more than one hundred patents including 72 U.S. patents. Most particu-larly, with his invention, “multipage cell architecture”, presented at the Symposium on VLSI Circuits in 1997, hesuccessfully commercialized the world’s first multi-level-cell NAND flash memory in 2001. He has authored nu-merous technical papers, one of which won the Takuo Sugano Award for Outstanding Paper at ISSCC in 2007.He has served on the ISSCC memory sub-committee since 2007.


Forum: F1 [AP9] MEMORY

FORUM

Embedded Memory Design for Nanoscale VLSI Systems

ObjectiveEmbedded memory has become increasingly important in achieving optimal product goals for power, perform-ance, and cost, in all nanoscale VLSI systems, today. This Full-day Forum is intended to provide a comprehen-sive review of various state-of-the-art embedded-memory technologies, circuit design, and product applications.

Audience The Forum is intended for both practicing engineers in the industry and graduate students in VLSI-related disciplines. They should gain state-of-the-art knowledge of a wide range of embedded memories that have be-come integral parts of the modern VLSI system.

ScopeThe Forum will focus on embedded SRAM, DRAM, and Flash, along with two key emerging memory types,namely MRAM and FeRAM. The key technology-scaling and integration issues will be discussed for each mem-ory. Many critical circuit-design techniques, along with various application requirements, will be presented.

ProgramThe Forum will address a broad range of key technical challenges facing today’s embedded-memory designers.It starts with an architecture overview of the embedded memory for mobile applications that has experienced anexplosive growth in recent years. The requirement of embedded memory for a mobile-applications processor, in-cluding multi-media functions, will be discussed from the perspective of platform architecture. Embedded SRAMhas always been essential in logic applications, but it has become increasingly difficult to achieve low-powerand high-performance targets as the feature size of the SRAM transistor is reduced, well below 100nm. The keytechnology-scaling challenges in SRAM will be examined. Many design techniques to deal with cell stability withgrowing device variation and array leakage, will be presented. Embedded DRAM technology has provided design solutions balancing performance and cost, in consumer electronics. The recent advance in this area ispushing the eDRAM into high-performance computing application. The eDRAM technologies for these two dif-ferent applications will be discussed with their critical circuit and product attributes. The application of flashmemory in embedded processors continues to grow rapidly. The Forum will focus on key technology and cir-cuit-design challenges in this area. The new charge-trapping-based flash memory will be discussed along withthe conventional floating-gate-based structure. Two key emerging non-volatile memories, MRAM and FeRAM, willbe examined on many key technical areas, including the state-of-technology-development, critical-circuit de-sign, product applications, and future scaling trends. The Forum will also provide an excellent opportunity for theattendees to interactively engage with the speakers on key technical issues they may face in real product devel-opment.

RF

Subcommittee

• Overview

• Featured Papers

• Evening Session

• Evening Session

• Tutorial

• Forum

• Trend chart

(co-sponsored by RF, Technology Directions, and Wireless)

(co-sponsored by RF, and Wireless)


Sessions: 9, 17, 26, 31 [AP34,50,72,82] RF

ISSCC 2008 – RF

Subcommittee Chair: John R. Long, Delft University of Technology, Netherlands

OVERVIEW


� Full or near-full integration of wireless receivers in CMOS [9.1, 9.2, 9.6]

� Phased-array receivers at mm-wave frequencies in CMOS [9.3, 9.4]

� Secure communication-link proof-of-concept using space-domain communication [9.5]

� Discrete-time wideband-receiver architecture with harmonic rejection [17.1]


� Very-low-power and high-quality CMOS integrated VCO [26.2]



� Higher-efficiency LDMOS and CMOS power amplifiers [31.4, 31.5]

� Software-defined transmitter PA concept in CMOS [31.6]

� Integrated quad-band CMOS power amplifier [31.7]


Sessions: 9, 17, 26, 31 [AP34,50,72,82] RF


� Low-cost CMOS solutions enable the use of almost-Terahertz radio waves for imaging in applications such as tumor detection (medical) and weapon/explosives detection (security) [9.1]

� Low-cost of CMOS technology opens the door to the use of mm-wave frequency bands (e.g., 60GHz band worldwide) for gigabit-rate wireless in portable consumer electronics [9.1, 9.2, 9.6]

� Phased-arrays used for high-gain steerable-beam antennas is an enabling technology for Gb/s wireless communication at frequencies above 20GHz [9.3, 9.4]

� Secure communication using a space-domain technique is demonstrated in CMOS IC technology [9.5]

� Power amplifiers, low-noise amplifiers, frequency sources, and other high-performance building blocks in low-cost CMOS technology operating at 60GHz [9.7, 26.5, 31.1, 31.2, 31.3]

� Software-defined radio building blocks and architectures [17.1, 31.6]

� Improved power-amplifier efficiency compared to today’s technologies for OFDM signals [31.4, 31.5]

� Ability to sustain a 15:1 load standing-wave ratio (VSWR) in a highly-integrated CMOS power amplifier with +35dBm output power [31.7]

SPECIAL-TOPIC SESSIONS“MEMS for Frequency Synthesis and Wireless RF Communications (or Life without Quartz Crystal)” [SE2](co-sponsored by RF, Technology Directions, and Wireless)Silicon (Si) MEMS resonators as a replacement for quartz resonators for basic frequency and time reference, which re-mains a crucial component in almost any electronic system. Recent developments made in Si MEMS resonators prom-ise stable and accurate temperature-compensated frequency-reference modules covering a wide range of frequencies.

“From Silicon to Aether and Back” [SE3]The interface from antenna to silicon, involving filtering, switching and antenna interface, is commonly done using pas-sive elements. However, the sheer number of passives required to interface to a multi-standard single-chip radio is grow-ing dramatically. Methods of managing this complexity are explored in this Special-Topic Session.

TUTORIALSilicon mm-Wave Circuits [T8]The design of circuits above 30GHz poses unique challenges that require the identification of new design methodologies,often outside the realm of the analog-circuit designer’s background and skill set. Key building blocks, such as amplifiers,mixers, and oscillators, incorporating Si transmission-line techniques, matching circuits, and distributed elements will bediscussed.

FORUM(Co-sponsored by RF, and Wireless)GIRAFE: Architectures and Circuit Techniques for Nanoscale RF CMOS [F3]CMOS technologies at 65nm and below are a challenge for RF and mixed-signal-circuit designers. Nanoscale design hasto cope with the low supply voltage, while considering manufacturing and variability aspects. The increasing performanceof digital circuitry with respect to power and speed, leads to new architectures based on changed integration tradeoffs foranalog, RF, and digital functions. This Forum, led by leading industry experts, will give an insight into these new designrequirements.


Session: 9 [A34] RFFEATURE

Advances in 60GHz CMOS Receivers

A Robust 24mW 60GHz Receiver in 90nm Standard CMOS [9.2]University of California, Berkeley

A 60GHz CMOS Receiver Using a 30GHz LO [9.6]University of California, Los Angeles


� Existing CMOS receivers have a relatively high noise figure compared to those in SiGe or III-V technologies

� The power consumption of CMOS 60GHz receivers is high due to operation close to activity limits

� Low-phase-noise LO at 60GHz is difficult to design for a wide tuning range

NOVEL CONTRIBUTIONS

� Complete receivers with conversion noise figure of 6.2dB demonstrated operating over the entire 60GHz band [9.2]

� Record low-power consumption of 24mW for combined LNA/mixer/VGA [9.2] and 36mW for combined LNA/I-Q mixers [9.6]

� Two-channel 52GHz receiver with LO phase shifting demonstrates capability for realizing highly-integrated phased arrays needed to overcome path loss in communication at 60GHz [9.4]


� 60GHz CMOS chipsets are becoming competitive with SiGe in power and performance [9.2, 9.4, 9.6]

� Short-range line-of-sight (LOS) giga-bit-per-second links can be realized with a single-chip CMOS solution [9.2, 9.6]

� Long-range non-line-of-sight (NLOS) giga-bit-per-second links can be realized with antenna arrays [9.4]


Session: 9 [AP34,35] RFFEATURE

Advances in Silicon Antennas and Phased-Arrays

A 52GHz Phased-Array Receiver Front-End in 90nm Digital CMOS [9.3]IMEC; VUB

A Near-Field Modulation Technique Using Antenna-Reflector Switching [9.5]California Institute of Technology


� Eavesdropping is a major impediment to secure wireless communication. While encryption techniques are robust, often the weakest link is the human factor which limits the security of passwords and encryption keys

� High-performance antenna arrays in the 6-to-18-GHz band are realized with expensive modules

� CMOS transceivers have limited transmit power and low sensitivity

� Present phased-arrays can communicate in one direction only

NOVEL CONTRIBUTIONS

� Two-channel CMOS receiver operates at 52GHz using quadrature LO phase shifting [9.3].

� Fundamentally new approach to secure communication utilizes near-field reflectors to shape the antenna constellation for a given direction of communication. [9.5]

� New ability to generate independent signal constellations in different directions to create a secure communication link or send multiple data streams in various directions. [9.5]


� New generation of phased-arrays operating at multiple frequencies and in multiple directions. [9.3]

� New field of secure communication with very-low probability of interception. [9.5]


Session: 26 [AP72] RFFEATURE

CMOS Breaks Frequency Record

A 410GHz CMOS Push-Push Oscillator with an On-Chip Patch Antenna [26.1]University of Florida

A 324GHz CMOS Frequency Generator Using a Linear-Superposition Techniques[26.3]UCLA; JPL


� Applications such as remote sensing, advanced imaging, and chemical detection, require low-cost solutions at frequencies in the 300GHz range and higher.

� Lower-cost technologies such as CMOS have been limited to frequencies below 200GHz

� Traditional measurement methods such as wafer probing are currently limited to frequencies below 220GHz

NOVEL CONTRIBUTIONS

� A 410GHz oscillator is demonstrated with on-chip antenna [26.1]

� A new method of measurement for frequencies above 220GHz [26.1, 26.3]


� Previous record frequency of 192GHz for CMOS is more than doubled [26.1]

� Very-high-frequency oscillators facilitate manufacturing of terahertz applications such as radars, remote sensing , and medical imaging for cancer detection [26.1, 26.3]

� Availability of very-high-speed oscillators will lessen the cost of security applications such as bio and chemical detection [26.1, 26.3]

� Demonstration that CMOS can replace more expensive technologies such as discrete (non-integrated) components, GaAs, and SiGe enabling smaller and more cost-effective solutions [26.1, 26.3]


Session: 31 [AP83] RFFEATURE

Highly Efficient PA Architectures

A 28.6dBm 65nm Class-E PA with Envelope Restoration by Pulse-Width and Pulse-Position Modulation [31.5]University of Washington; Intel

An Outphasing PA for a Software-Defined Radio Transmitter [31.6]UCLA; Matsushita


� Spectrally-efficient radio-modulation formats demand linear Power Amplifiers. Highly linear PAs typically have large power dissipation overhead. Consequently, there is a growing demand for efficient PA architectures that transcend process technology and thus enable the integration of Power Amplifiers even as CMOS process feature size and supply voltage limits scale downward.

NOVEL CONTRIBUTIONS

� Pulse-width modulation is exploited to achieve the highest PA output power ever demonstrated in 65nm CMOS [31.5]

� A new DSP-assisted method of lossless power combining is used to create an efficient variable-envelope PA system in 90nm CMOS [31.6]


� Highly efficient PA structures in deep-sub-micron CMOS enable ever-higher levels of feature integration at substantially lower cost in handheld communication devices. [31.5, 31.6]


Session: 31 [A83] RFFEATURE

Multi-Band Multi-Mode Cellular PA

A Fully-Integrated Quad-Band GSM/GPRS CMOS Power Amplifier [31.7]Axiom Microdevices


� Continued demand for highly-integrated handheld communication devices

� Economic issues create drive toward integrated CMOS solutions

� Small CMOS feature size and low supply voltage make Power-Amplifier design especially challenging

NOVEL CONTRIBUTIONS

� Distributed Active Transformer (DAT) PA in 130nm CMOS [31.7]

� Meets FCC and GSM/GPRS requirements for low and high bands [31.7]

� Up to 3.2 Watts output at >45% efficiency [31.7]


� This production-proven CMOS Power Amplifier is a major, and some would say the most-difficult, step in the path toward a truly single-chip cellular phone. [31.7]


Special: SE2 [AP12] RF, TD, and WIRELESS


MEMS for Frequency Synthesis and Wireless RF Communications(or Life without Quartz Crystals)

Organizer: Christian Enz,CSEM, Neuchâtel, SwitzerlandChair: Ernesto Perea, STMicroelectronics, Crolles, France

Co-Chair: Ken Cioffi, Altierre, San Jose, CA

OVERVIEWMany recent start-ups are now proposing silicon (Si) MEMS resonators as a replacement for quartz resonators,which remain a crucial component in almost any electronic system for basic frequency and time reference. ThisSpecial Topic Session will give an overview on the recent developments made in Si MEMS resonators in achiev-ing this goal. Technological and electronic solutions for implementing highly stable and accurate temperature-compensated frequency reference synthesis modules covering a wide range of frequencies will be presented. Alsoaddressed will be the many challenges such as stability, phase noise, packaging, reliability, and cost concernsas well as the perspective of integrating the MEMS devices together with other passives such as BAW resonatorsultimately leading to a single-chip radio chip in an SiP

OBJECTIVE

� To give an overview of new MEMS technologies that are, or will be, available in the near future for time and frequency reference generations.

� To present the challenges faced by these emerging technologies.

CHALLENGE

� How can system-in-chip (SiP) enable the efficient combination of MEMS resonators and other RF MEMS devices with a system-on-chip (SoC)

� How should systems be designed to fully take advantage of MEMS devices and particularly Si MEMS resonators for time and frequency references



STRUCTURE

“Silicon Resonators For Ultra-Compact High-Performance Timing References”Bernhard Boser, Chief Scientist, SiTimeSilicon MEMS resonators are processed and packaged using standard CMOS equipment and flows. Smaller size, reducedcomponent count, and low processing cost are strong arguments motivating the replacement of quartz with MEMS. Recent innovation removes long-term drift as the main obstacle to using MEMS resonators as precision timing references.It is accomplished with a unique package that hermetically seals the device in the silicon wafer and ensures a contaminant-free environment. These results have been transferred to the production floor and general-purpose precision clocks basedon MEMS resonators are now in volume production.

Owing to their small size, present MEMS resonator designs exhibit elevated phase noise and jitter compared to clocksbased on high-quality crystals. This shortcoming is addressed with new resonator structures that operate at significantlyhigher power-levels. These devices will enter the market in the near future and enable performance-critical applications suchas high-speed serial communication and RF to be served by MEMS. Increasingly, MEMS resonators will be integratedmonolithically with application-specific integrated circuits, and in the near term we will witness the gradual replacementof quartz in performance-, size-, and cost-critical applications.

“Micromechanical Circuits for Communications-Grade Frequency Control”Clark Nguyen, UC BerkeleyRecent advances in vibrating RF MEMS technology that yield on-chip resonators with Q’s over 10,000 at GHz frequenciesand excellent thermal and aging stability, have now positioned vibrating micromechanical devices as strong candidates forinclusion into a number of future wireless-communication sub-systems. To date, on-chip reference oscillators that meetGSM phase noise specifications and filters with tiny percent bandwidths, yet, low insertion loss, have been realized in thistechnology. The ultimate extent of the performance and economic benefits afforded by vibrating RF MEMS devices will likelygrow exponentially as researchers begin to perceive them more as circuit building blocks than as stand-alone devices. Inparticular, when integrated into micromechanical circuits, in which vibrating mechanical links are connected into largermore-general networks substantial improvements in the performance of the above circuits is expected. In addition, previ-ously unachievable signal-processing functions become possible, such as reconfigurable RF channel-selecting filter banksand ultra-stable reconfigurable oscillators.

“Integrating Si-MEMS, BAW Resonators and RF-CMOS in a SiP For Ultra-low-power Radio”J. Baborowski, CSEM, Neuchatel, SwitzerlandCurrent wireless applications are setting increasing demands for the oscillators’ size, power consumption, and price. High-Q silicon MEMS resonators have great potential for on-chip high frequency applications, integrated-circuit clock genera-tion, and other applications based on a stable frequency-reference signal. The thermal compensation of the silicon resonatoras well as the development of miniature inexpensive lead-free packaging solutions represent, however real technical andscientific challenges.

Two types of silicon resonators with AlN piezoelectric activation will be presented. The first type, the extensional mode res-onator, exhibits a Q factor in vacuum as high as 120,000 and a mainly linear temperature coefficient of frequency (TCf) of-28.5+/-1ppm/°C. The second type, a triple tuning fork, presents a zero first order TCf that has been obtained at the devicelevel by balancing the negative temperature coefficient of stiffness (TCE) of Si and AlN with the positive TCE of SiO2. Thesame technology platform enables the co-integration of Si-resonators with RF BAW filters. Wafer-vacuum-level packagingis the key solution to fabricating a miniaturized ultra-low-power radio.



“RF MEMS for Reconfigurable Radio”K. Masu, Tokyo Institute of TechnologyIn the wireless IT era, wireless transceivers found in mobile phones, PCs, PDAs, etc., are required to be multi-band/multi-mode. For multi-band transceivers, a simple solution is the use of many RF CMOS circuit blocks, which leads to an increasein circuit area. Another solution is a reconfigurable RF circuit, where one circuit can operate as various-wireless-standard circuit block. RF MEMS components and devices have potential of improving RF circuit performance. Furthermore,they will help create small, high-performance implementations of reconfigurable RF CMOS circuits. Several kinds of vari-able MEMS inductors and variable MEMS capacitors, their application to reconfigurable RF CMOS circuits, and their fu-ture application will be discussed.

RECAPThe Technology-Directions Subcommittee together, with the RF and Wireless Subcommittees, is pleased to present a Spe-cial-Topic-Session-format overview on how recently developed MEMS resonators can be used for frequency synthesisand/or time reference, and how they can be combined with other MEMS devices for the design of reconfigurable low-power radios. Four top experts in the field will give different perspectives and discuss the many challenges remaining toachieve a crystal-clear(less) future “life without quartz”.


Special: SE3 [AP28] RF


From Silicon to Aether and Back!Organizers: S. Tanaka, Renesas Technology., Komoro, Japan

M. Tiebout, InfineonTechnologies, Villach, AustiraChair: A. Hajimiri, California Institute of Technology, Pasadena, CA

OVERVIEWThe interface between antenna and silicon IC is complicated by the proliferation of standards. Filtering, switch-ing, and interface to the antenna are commonly accomplished using passive elements, but the large number ofpassives required to interface to a multi-standard single-chip radio increase the component count and size of theradio. Potential solutions to this problem will be explored in this SET.

OBJECTIVE

� Introduce the topic to ISSCC

� Extend the semiconductor-minded IC view to include the complete mobile-terminal picture

CHALLENGE

� Number and size of external components between chip and antenna

� Bill of materials reduction

STRUCTURE

� Multi-Mode Mobile-Device Trends and Challenges, A. Pärssinen, Nokia, Helsinki, Finland

� Front-End Module and Filter Device Technology, Rich Ruby, Avago Technologies, San Jose, CA

� CMOS PA Integration and Future RF Front-End Integration, Donald McClymont, Axiom Miocrodevices, Irvine, CA

� Integration of an RF Front-End on SoC, Hooman Darabi, Broadcom, Irvine, CA

RECAP

� Familiarize attendees and nurture first insights on this topic in the IC-oriented ISSCC community.


Tutorial: T8 [AP7] RF

TUTORIAL

Silicon mm-Wave DesignAli Niknejad, University of California, Berkeley, CA

OVERVIEWA recent surge of interest in Si mm-wave circuits and systems, evidenced by the number of conference and jour-nal papers, and new research organizations, clearly demonstrates keen interest in exploring new applications formm-wave frequencies. The design of circuits above 30GHz poses unique challenges and requires new designmethodology, often outside the realm of the analog circuit designer’s background and skill set. This tutorial willreview fundamental theory and practical techniques applicable to mm-wave circuits. The design of key buildingblocks such as amplifiers, mixers, and oscillators, will be discussed which incorporate Si transmission-line tech-niques, matching circuits, and distributed elements.

SPEAKER BIOGRAPHYAli Niknejad received the BSEE degree from the University of California, Los Angeles, in 1994, and the MS andPhD degrees in Electrical Engineering from the University of California, Berkeley, in 1997 and 2000. From 2000to 2002, he worked in industry where he was involved with research and design of CMOS RF integrated circuits.Presently, he is an Associate Professor in the EECS Department at UC Berkeley. He is a Co-Director of the Berke-ley Wireless Research Center (BWRC) and also the Co-Director of the BSIM Research Group. He served as anAssociate Editor of the IEEE Journal of Solid-State Circuits, and is currently serving on the ITPC for the Interna-tional Solid-State Circuits Conference (ISSCC) and the Custom Integrated Circuits Conference (CICC). His cur-rent research interests lie within the area of RF and microwave and mm-wave integrated circuits and devicemodeling.


Forum: F3 [AP11] RF; WIRELESS

GIRAFE DESIGN FORUMArchitectures and Circuit Techniques for Nanoscale RF CMOS

OBJECTIVERF CMOS has become a mature technology over the past decade. RF SoC realizations of wireless systems are standardtoday for connectivity systems, where first attempts are made to integrate even the PA amplifier for WLAN or for DECT. Thevolume requirements of low-cost GSM/GPRS/EDGE mobile phones are driving these SoCs from 0.13µm to nanoscale tech-nology nodes. 3G and 4G systems require the use of the 45nm or even 32nm node in order to cope with the power andcost targets. Area-efficient implementation of RF, mixed-signal, and power-management functions will be the foundationfor successful deployment of SoCs in these technologies. The high ft of nanoscale CMOS will be a key enabler for the useof RF CMOS in millimeter-wave systems for data transmission or radar applications.

AUDIENCEAttendance is limited and preregistration is required. This all-day Forum encourages open information exchange. The tar-geted participants are circuit designers and concept engineers working on wireless systems, who want to learn about theimpact of nanoscale technologies on circuit and system design.

SCOPECMOS technologies at 65nm and below are a challenge for RF and mixed-signal circuit designers. The Forum will presentinsights into the design requirements provided by leading industry experts. Nanoscale design must cope with the low sup-ply voltage, while manufacturing and variability aspects are considered. The increasing performance of digital circuitry(with respect to power and speed) leads to new architectures based on changes of tradeoffs for integrating analog, RF anddigital functions. Especially for RF, mixed-signal and power-management circuitry, nanoscale CMOS transistors and pas-sives might not provide better performance figures except for the pure fT of the transistors. Therefore Moore’s law will nothold for these circuitry, whereas the industry is still forced to follow the shrink path in order to provide each year 1-billioncell phone SoCs with ever-increasing feature set.

PROGRAMThe Forum will begin with three talks that will provide an overview of the analog and RF performances perspectives ofnanoscale RF CMOS, from both research and commercial point of views. Stefaan Decoutre (IMEC) will talk about today’sresearch activities at 32nm and below. His focus will be on alternative device architectures providing increased robustnessto short channel effects. The commercial view will be covered by Shine Chung (TSMC) talking about nanoscale-RF-CMOSfoundary requirements. Statistical variations are a new phenomena seen in nanoscale technologies, which will be discribedby Marcel Pelgrom (NXP). The final talk before lunch emphasizes architectural trends and requirements for RF SoCs innanoscale technologies. Khurram Muhammad (TI) will share his insight on fully integrated radios in deep-submicronCMOS.

The afternoon session is dedicated to actual designs in nanoscale RF CMOS, starting with Chris Rudell (Intel) talking abouta 45nm CMOS transceiver targeting WiMAX. Didier Belot (ST) will cover the mm-wave frequency range, which might bean area for future application of RF CMOS. The talk given by Domine Leenaerts (NXP) will compare actual UWB imple-mentations (from 90nm down to 45nm) with respect to circuit performance, ease of scaling and size.

Finally, Lukas Doerrer (IFX) will describe the design and performance of some basic building blocks in 45nm CMOS. TheForum will conclude with a panel discussion, where the attendees have the opportunity to ask questions and to share theirviews.



GIRAFE DESIGN FORUMArchitectures and Circuit Techniques for Nanoscale RF CMOS

Organizer: Stefan Heinen, Infineon Technologies, Duisburg, GermanyCo-Organizer: Francesco Svelto, University of Pavia, Pavia, ItalyCommittee: Jan Craninckx, IMEC, Leuven, Belgium

Mototsugu Hamada, Toshiba, Kawasaki,JapanDomine Leenaerts, NXP, Eindhoven, NetherlandsChris Rudell, Intel, Santa Clara, CA

Forum Agenda

Time Topics

8:00 Breakfast

8:15 IntroductionStefan Heinen, Infineon Technologies, Duisburg, Germany

8:45 Analog and RF performance perspectives of (sub-) 32nm CMOSStefaan Decoutere, IMEC, Leuven, Belgium

9:30 Foundry Technologies for nanoscale RF integrationShine Chung, TSMC, Hsinchu, Taiwan

10:15 Break

10:45 Nano-meter CMOS is a statistical challenge!Marcel Pelgrom, NXP, Eindhoven, Netherlands

11:30 RF SoC Architecture Trends and Requirements in deep-submicron CMOS: A Perspective

Khurram Muhammad, TI, Dallas, Texas

12:15 Lunch

1:15 Low-voltage, Transceiver Design in 45nm CMOS with an emphasis on WiMAX

Chris Rudell, Intel., Santa Clara, CA

2:00 mmW design in nanoscale CMOSDidier Belot, STMicroelectronics, France

2:45 Break

3:15 UWB circuit design in 90nm, 65nm, and 45nm CMOSDomine Leenaerts, NXP, Eindhoven, Netherlands

4:00 Circuit design in 45nm CMOS processLukas Doerrer, Infineon Technologies, Villach, Austria

4:45 Panel Discussion

5:15 Conclusion


TREND RF

DATACOM TREND CHARTDATACOM TREND CHART

This data-rate trend chart projects the capabilities of wireless and wireline datacom technologies using currentstandards. Millimeter-wave frequency bands (such as 60GHz) constitute a potential disruptive technology, enabling gigabit/s data rates over a short-range wireless link at speeds well over 1,000Mbits/s.

Data rate trend vs. history

0.1

1

10

100

1000

10000

1975 1980 1985 1990 1995 2000 2005 2010

Year

Spe

ed (M

bps)

1Base-T

10Base-T

100Base-T

1000Base-T

10GBase-T

802.11

802.11b

802.11a

802.15.3

Ethernet WLAN WPANUSB

USB1.0

USB1.1

USB2.0


NOTES

Technology

Directions

Subcommittee

• Overview

• Featured Papers

• Evening Session

• Tutorial

• Forum

(co-sponsored by RF, TD, and Wireless)


Sessions: 7, 15, 18, 29 [AP26,46,52,78] TECHNOLOGY DIRECTIONS

ISSCC 2008 – TECHNOLOGY DIRECTIONS

Subcommittee Chair: Anantha Chandrakasan, MIT, Cambridge, MA

OVERVIEW

MOST-SIGNIFICANT RESULTS� A wireless sensor network using wearable 30cm3 nodes with 3-year battery life has been used to study human

activity and interaction between people, as a first demonstration of social electronics [7.1].

� A 16mm2 complete wireless sensor-node SoC for disposable smart bandaids is used for vital-sign monitoring in body-area network applications [7.2].

� The smallest Nuclear-Magnetic-Resonance (NMR) system (2500cm3) is used for detection of biomolecules [7.3].

� The first imager (1.1x1.5 mm2) implanted into a human eye, partially restoring vision to a blind patient [7.4].

� A match-size miniature endoscope with high-efficiency image sensor [7.4].

� A single-chip complete wireless neural-recording system for neural prostheses consumes only 6mW [7.6].

� The highest-density stimulation array (256x256 stimulation sites on 4x4mm2 silicon) for stimulation of acute brain slices [7.7].



� 107 pJ/bit transmission at 100kb/s at a distance of 60cm enables an electronic tabletop [15.4]

� Contactless communication using inductive coupling allows data transfer at 11Gb/second [15.7]

� 2.1μW power-management circuit providing greater than 60% efficiency allows body heat to power wireless sensor nodes. [15.8]

� Infrared sensor -array system with Si-lens, with 800µV/°C sensitivity [18.1]



� A 52µW wake-up radio at 2GHz enables long lifetime for wireless sensor network radio [29.2]

� Towards cognitive radios for more-efficient use of UHF spectrum thanks to a power-spectrum analyzer integrated together with a radio [29.3]



Sessions: 7, 15, 18, 29 [AP26,46,51,78] TECHNOLOGY DIRECTIONS


� Social studies and human interaction (e.g. teamwork) are enabled by the Life Thermoscope [7.1].

� Improved quality of care enabled by disposable smart bandaids encourages low-cost continuous monitoring [7.2].

� The world’s smallest NMR system enables portable detection of proteins, viruses, and biomarkers [7.3].

� Vision restoration for hundreds of thousands of people per year worldwide affected by retinitis pigmentosa [7.4 and 7.5].

� New fashion trends (as well as health monitoring) for kids enabled by embedded circuits in textiles [7.8]

� Organic RFID tags costing less than one cent. [15.3]

� Wireless coupling or thermoelectric power derived from body heat for battery elimination. [15.3, 15.8]

� Thermopile sensor can improve refrigerators, microwave ovens and air conditioners [18.1]

� Rapid low-cost detection of bacteria in the healthcare and food industries [18.4]

� MEMS-based radios enable ultra-miniaturized medical devices [29.1]

� Ultra-low-power wake-up radio combined with traditional radios, enable maintenance-free wireless sensor networks possible [29.2]

� 45nm CMOS has demonstrated the ability to effectively embed analog, RF and mm-wave building blocks [29.4, 29.8]

SPECIAL-TOPIC SESSION(co-sponsored by RF, TD and Wireless)MEMS for Frequency Synthesis and Wireless RF Communications (or Life without QuartzCrystals) [SE2]

TUTORIALCMOS+Bio: The Silicon that Moves and Feels Small Living Things [T9]

FORUMPower Systems from the Gigawatt to the Microwatt – Generation, Distribution, Storage, andEfficient Use of Energy [F4]


Session: 7 [AP26,27] TECHNOLOGY DIRECTIONSFEATURE

Wearable Healthcare Monitoring Systems Coming of Age

Life Thermoscope: Integrated Microelectronics for Visualizing Hidden LifeRhythms [7.1]Hitachi

A 1V Micropower System-on-Chip for Vital-Sign Monitoring in Wireless Body-Sen-sor Networks [7.2]Toumaz Technology; Future Waves

A 1.12mW Continuous Healthcare Monitor Chip Integrated on a Planar Fashion-able Circuit Board [7.8]KAIST


� Power consumption of existing sensor nodes limits the energy autonomy of wearable sensors

� The need for disposable-sensor systems is not addressed

� Attachment to the body or into clothing is not trivial

NOVEL CONTRIBUTIONS

� A wireless-sensor network consisting of 30cm3 nodes with 3-year battery life has been used to study human activity and interaction between people, as a first demonstration of social electronics [7.1].

� A 16mm2 complete wireless-sensor node SoC for disposable smart bandaids is used for vital-sign monitoring in body-area-network applications [7.2].



� Social studies and human interaction (e.g. teamwork) are facilitated by the Life Thermoscope [7.1].

� Improved quality of care using disposable smart bandaids enables low-cost continuous monitoring [7.2].

� New fashion trends (as well as health monitoring) for kids are motivated by circuits embedded in textiles [7.8].


Session: 7 [AP26,27] TECHNOLOGY DIRECTIONSFEATURE

Smart Implants

CMOS Imager Technologies for Biomedical Applications [7.4]IMS-CHIPS

A 1600-Pixel Subretinal Chip with DC-Free Terminals and ±2V Supply Optimizedfor Long Lifetime and High Stimulation Efficiency [7.5]University of Ulm; NMI; Retina Implant

A 128-Channel 6mW Wireless Neural-Recording IC with On-the-fly Spike Sortingand UWB Transmitter [7.6]UC Santa Cruz; U of Newcastle; National Chiao-Tung U


� Epiretinal implants require complex interfaces with an external camera.

� Subretinal implants overcome this problem, but have not been successfully realized.

� DC potentials in implants cannot be tolerated (net charge injection causes detrimental reactions).

� Current endoscopic imaging systems are large (in diameter) and therefore unpleasant to swallow.

� Wireless neural probing is achieved in a discrete manner with separate circuits for amplification and transmission.

� Multichannel neural recording involves a large amount of data; the absence of local neural data reduction (e.g. spike sorting) reduces the number of channels that can be recorded and wirelessly transmitted.

NOVEL CONTRIBUTIONS

� The first subretinal imager (1.1x1.5 mm2) successfully implanted into a human eye partially restores vision to a blind patient [7.4].

� A match-size miniature endoscope with high-efficiency image sensor improves comfort without sacrificing resolution [7.4].

� A second subretinal stimulation chip achieves 4V stimulation peak-to-peak and is DC-free [7.5].

� A single-chip complete wireless neural recording system for neural prostheses consumes only 6mW and includes spike detection and filtering [7.6].


� Vision restoration for hundreds of thousands of people per year worldwide affected by retinitis pigmentosa [7.4, 7.5].


Session: 15 [AP86] TECHNOLOGY DIRECTIONSFEATURE

RFID Advances

A CMOS-SOI 2.45GHz Remote-Powered Sensor Tag [15.1]CEA-LETI/MINATEC

A Triple-Band Passive RFID Tag [15.2]Graz University of Technology

An Inductively-Coupled 64b Organic RFID Tag Operating at 13.56MHz with a DataRate of 787b/s [15.3]IMEC; KU Leuven; Polymer Vision; TNO Science and Industry


� RFID tags without power source

� Monitoring of blood pressure, temperature and other variables used by healthcare professionals frequently require patients to be wired to recording equipment.

� Multiple standards for RFID tags preclude operating tags designed for different frequencies.

� Cost represents the single most demanding requirement for most RFID tags used in supply chains for high-volume products.

NOVEL CONTRIBUTIONS

� Merging a 2.45GHz RFID tag with a pressure sensor allows wireless measurement of environmental variables. This extends the impact of RFID from product location and identification to wireless measurement and tracking of a large variety of important parameters like blood pressure, temperature,or heart rate. [15.1]

� Frequency of operation for RFID tags ranges from hundreds of kilohertz to gigahertz. Each tag “scavenges” the energy required to operate from the RF frequency at which it operates. These scavenging circuits typically operate at a single frequency. Enablement of multi-standard tags demands a multi-mode power scavenging scheme. [15.2]

� The small size of RFID tags is a direct result of the need for low cost. Utilizing an extremely low-cost manufacturing technology such as organic microelectronics presents an equally powerful means of producing exceptionally low-cost tags. [15.3]




� A completely wireless RFID tag can be used to monitor many features of a patient in a hospital or even a home setting. Currently, for example, 24-hour monitoring of cardiac rhythm requires attaching an EKG package, batteries and radio to the patient which they must carry around all day. An almost unnoticeable RFID tag could replace this entire bundle of electronics leaving the patient far more comfortable and mobile. Similarly, monitoring healthy individuals like athletes in competition could improve performance or ensure safety. [15.1]

� International shipping of devices with RFID tags will occur more and more frequently. To preclude multiple tags conforming to multiple standards, and the attendant costs of multiple tagging devices, a single multi-standard tag would allow shipping a pallet of products from the originator in the US to a customer in Europe while allowing the supply chains of both producer and consumer to track shipments in their respective countries. [15.2]

� The lowest-cost tags are the ones that will become dominant in usage. Organic microelectronics using low-cost printing technology will produce tags for a fraction of a cent and allow virtually anything to be tagged and located without the need for wires or batteries. [15.3]



Infrared Sensors

A 64/256-Element Thermopile Infrared-Sensor Chip with 4 Built-In Amplifiers foruse in Atmospheric-Pressure Conditions [18.1]Seiko NPC


� Bolometer IR sensors are expensive today and requires vacuum assembly

� Previous thermopile implementations with atmospheric assemblies have lower sensitivity

NOVEL CONTRIBUTIONS

� This thermopile uses front-side bulk micro-machining, 4 amplifiers and Au-black as an infrared absorber.The thermocouple uses a P+poly-Si/N+poly-Si structure. An 8-pin TO-5 package is used with an Si-lens.[18.1]

� Measured responsivity is 146 to 195V/W [18.1]

� Output of 800µV/°C is achieved at 35°C blackbody temperature [18.1]

� Thermal time constant is less than 2 ms [18.1]


� Applications: air conditioners, microwave ovens, and home security systems [18.1]

� Impact: Very-low cost at high sensitivity [18.1]

� Competition: Microbolometers are too expensive for consumer electronics appliances [18.1]



Ultra-Low-Power and Miniature MEMS-Based Radios

A 2.4GHz MEMS-Based Transceiver [29.1]CSEM

A 2GHz, 52μW Wake-Up Receiver with -72dBm Sensitivity Using Uncertain-IF Architecture [29.2]UC Berkeley


� Need for miniaturized radios in wireless sensor networks and medical applications

� Standard radios for wireless sensor networks require ultra-low-power wake-up radios to enable extended lifetime and maintenance-free operation

NOVEL CONTRIBUTIONS

� First-time demonstration of a 2.4GHz MEMS-based RF transceiver combining BAW resonators, a temperature-compensated MEMS resonator, and an RF-CMOS radio to reduce size, Bill of Materials (BoM) and cost [29.1]

� Wake-up radio achieves 52µW power consumption, allowing for continuous-time operation [29.2]


� Miniaturization and power reduction of radios enables ubiquitous wireless communication, and more convenient medical devices such as implants or hearing aids located in the ear canal [29.1, 29.2]





Organizer: Christian Enz, ,CSEM, Neuchâtel, SwitzerlandChair: Ernesto Perea, STMicroelectronics, Crolles, France

Co-Chair: Ken Cioffi, Altierre , San Jose, CA

OVERVIEWMany recent start-ups are now proposing silicon (Si) MEMS resonators as a replacement for quartz resonators, which re-main a crucial component in almost any electronic system for basic frequency and time reference. This Special Topic Ses-sion will give an overview on the recent developments made in Si MEMS resonators in achieving this goal. Technologicaland electronic solutions for implementing highly stable and accurate temperature-compensated frequency reference syn-thesis modules covering a wide range of frequencies will be presented. Also addressed will be the many challenges suchas stability, phase noise, packaging, reliability, and cost concerns as well as the perspective of integrating the MEMS de-vices together with other passives such as BAW resonators ultimately leading to a single-chip radio chip in an SiP

OBJECTIVE



CHALLENGE





STRUCTURE“Silicon Resonators For Ultra-Compact High-Performance Timing References”Bernhard Boser, Chief Scientist, SiTimeSilicon MEMS resonators are processed and packaged using standard CMOS equipment and flows. Smaller size, reducedcomponent count, and low processing cost are strong arguments motivating the replacement of quartz with MEMS.

Recent innovation removes long-term drift as the main obstacle to using MEMS resonators as precision timing references.It is accomplished with a unique package that hermetically seals the device in the silicon wafer and ensures a contaminant-free environment. These results have been transferred to the production floor and general-purpose precision clocks basedon MEMS resonators are now in volume production.

Owing to their small size, present MEMS resonator designs exhibit elevated phase noise and jitter compared to clocksbased on high-quality crystals. This shortcoming is addressed with new resonator structures that operate at significantlyhigher power-levels. These devices will enter the market in the near future and enable performance-critical applications suchas high-speed serial communication and RF to be served by MEMS. Increasingly, MEMS resonators will be integratedmonolithically with application-specific integrated circuits, and in the near term we will witness the gradual replacementof quartz in performance-, size-, and cost-critical applications.

“Micromechanical Circuits for Communications-Grade Frequency Control”Clark Nguyen, UC BerkeleyRecent advances in vibrating RF MEMS technology that yield on-chip resonators with Q’s over 10,000 at GHz frequenciesand excellent thermal and aging stability, have now positioned vibrating micromechanical devices as strong candidates forinclusion into a number of future wireless-communication sub-systems. To date, on-chip reference oscillators that meetGSM phase noise specifications and filters with tiny percent bandwidths, yet, low insertion loss, have been realized in thistechnology. The ultimate extent of the performance and economic benefits afforded by vibrating RF MEMS devices will likelygrow exponentially as researchers begin to perceive them more as circuit building blocks than as stand-alone devices. Inparticular, when integrated into micromechanical circuits, in which vibrating mechanical links are connected into largermore-general networks substantial improvements in the performance of the above circuits is expected. In addition, previ-ously unachievable signal-processing functions become possible, such as reconfigurable RF channel-selecting filter banksand ultra-stable reconfigurable oscillators.

“Integrating Si-MEMS, BAW Resonators and RF-CMOS in a SiP For Ultra-low-power Radio”J. Baborowski, CSEM, Neuchatel, SwitzerlandCurrent wireless applications are setting increasing demands for the oscillators’ size, power consumption, and price. High-Q silicon MEMS resonators have great potential for on-chip high frequency applications, integrated-circuit clock genera-tion, and other applications based on a stable frequency-reference signal. The thermal compensation of the silicon resonatoras well as the development of miniature inexpensive lead-free packaging solutions represent, however real technical andscientific challenges.

Two types of silicon resonators with AlN piezoelectric activation will be presented. The first type, the extensional mode res-onator, exhibits a Q factor in vacuum as high as 120,000 and a mainly linear temperature coefficient of frequency (TCf) of-28.5+/-1ppm/°C. The second type, a triple tuning fork, presents a zero first order TCf that has been obtained at the devicelevel by balancing the negative temperature coefficient of stiffness (TCE) of Si and AlN with the positive TCE of SiO2. Thesame technology platform enables the co-integration of Si-resonators with RF BAW filters. Wafer-vacuum-level packagingis the key solution to fabricating a miniaturized ultra-low-power radio.



“RF MEMS for Reconfigurable Radio”K. Masu, Tokyo Institute of TechnologyIn the wireless IT era, wireless transceivers found in mobile phones, PCs, PDAs, etc., are required to be multi-band/multi-mode. For multi-band transceivers, a simple solution is the use of many RF CMOS circuit blocks, which leads to an increasein circuit area. Another solution is a reconfigurable RF circuit, where one circuit can operate as various-wireless-standard circuit block. RF MEMS components and devices have potential of improving RF circuit performance. Furthermore,they will help create small, high-performance implementations of reconfigurable RF CMOS circuits. Several kinds of vari-able MEMS inductors and variable MEMS capacitors, their application to reconfigurable RF CMOS circuits, and their fu-ture application will be discussed.

RECAPThe Technology-Directions Subcommittee together, with the RF and Wireless Subcommittees, is pleased to present a Spe-cial-Topic-Session-format overview on how recently developed MEMS resonators can be used for frequency synthesisand/or time reference, and how they can be combined with other MEMS devices for the design of reconfigurable low-power radios. Four top experts in the field will give different perspectives and discuss the many challenges remaining toachieve a crystal-clear(less) future “life without quartz”.


Tutorial: T9 [AP8] TECHNOLOGY DIRECTIONS

TUTORIAL

CMOS + Bio: the Silicon that Moves and Feels Small Living Things Donhee Ham, Harvard University, Cambridge, MA

OVERVIEWSilicon microelectronic chips are emerging as powerful new tools for rapid, sensitive, and label-free analysis ofbiological objects such as cells, proteins, viruses, and DNA. The interface between electronic and biological sys-tems is aimed at revolutionary advances in human health care, e.g., early disease detection. This tutorial at-tempts an effective exposure to this burgeoning field. We will discuss how to structure and design silicon ICsfor front-end bio-sensing and actuation in direct contact with the bio world. Specifically, we will discuss the fol-lowing topics:

� CMOS magnetic resonance biomolecular sensors

� CMOS, all-electronic DNA, protein, & virus microarray sensors

� CMOS magnetic and electric cell actuators

� CMOS-neuron interfaces

SPEAKER BIOGRAPHYDonhee Ham is John L. Loeb Associate Professor of the Natural Sciences at Harvard University, where his re-search group works on (1) RF, microwave, & analog ICs, (2) ultrafast quantum transports using low-dimen-sional nano devices, (3) soliton electronics, and (4) applications of CMOS ICs in biotechnology. He received hisB.S. degree in physics from Seoul National University, graduating atop the Natural Science College, and Ph.D.degree in EE from Caltech, winning the Charles Wilts Prize, best thesis award in EE. His work experiences includethe Laser Interferometer Gravitational Wave Observatory, IBM T. J. Watson Research Center, IEEE technical pro-gram committees including ISSCC, and technical advisory positions on ultrafast solid-state electronics and sci-ence & technology at the nanoscale. He was a fellow of the Korea Foundation for Advanced Studies, a recipientof the IBM Doctoral Fellowship, and a recipient of the IBM Faculty Partnership Award. He is a co-editor of CMOSBiotechnology, Springer, 2007.


Forum: F4 [AP90] TECHNOLOGY DIRECTIONS

FORUM

Power Systems from the Gigawatt to the Microwatt –Generation, Distribution, Storage and Efficient Use of Energy

OBJECTIVEEnergy is the most important resource on our planet. At the global level, humankind has to cope with limited en-ergy availability, and the environmental impact of energy generation. Therefore efficient use of energy alongwith judicious distribution and storage, in order to better utilize the generated energy, is vital. More environmentfriendly energy generation and scavenging technologies will play a significant role in continuing to meet the en-ergy demands. Total available energy is especially scarce in mobile applications and in the emerging field of dis-tributed micro-systems: Every IC designer is thus continuously challenged to an increasingly more efficient useof energy, and energy awareness is becoming a key aspect of cutting-edge system design.

AUDIENCEThis Forum is intended for circuit designers, engineering students, and people from the electronics industry atlarge, wishing to gain an understanding of energy-related design issues both at the circuit and at the system level.The Forum will cover low-power and ultra-low-power systems as well as, high-power applications and high-per-formance computing.

SCOPEA selected panel of experts from industry and academia will present their most advanced research in the field ofenergy. The scope of the Forum is intentionally broad, from energy generation, to storage and efficient use, andcovers both high power and low to ultra-low power applications. This will provide the participant a stimulatingmulti-disciplinary training experience, covering the most advanced energy-related challenges in nowadays, elec-tronics.

PROGRAMThe Forum is divided into three main parts: Energy generation and storage, large power issues, and efficient useof energy. In the first part, Vladimir Bulovic (MIT) will demonstrate how the use of nano-structured materialscan improve the efficiency of solar cells and lighting; Chris Van Hoof (IMEC) will present a range of devices ableto scavenge mechanical and thermal energy available in the environment to power distributed micro-systems;Yuji Suzuki (University of Tokyo) will present micro-scale generators exploiting the chemical energy containedin hydrocarbon fuels; Peter H.L. Notten (Technical University of Eindhoven and Philips) will address the potentialof future rechargeable batteries, for applications ranging from plug-in hybrid cars to integrated all-solid-state bat-teries. In the second part, Pietro Perlo (FIAT) will analyze the advantages of electric vehicles, focusing on sys-tem-level issues and the role of electronics in these cars, while Kenneth M. Huber (PJM) will highlighttechnologies needed to achieve better electric-grid control for efficient-energy distribution. In the last part of theForum, devoted to the efficient use of energy, Seth Sanders (U.C. Berkeley) will examine the problem of powerconversion, addressing challenges, and examples, at different power levels (mobile applications vs. micro-processors); Anantha P. Chandrakasan (MIT) will discuss strategies to build energy-aware systems for mobileand ultra-low-power applications; and Shekhar Y. Borkar (Intel) will investigate the challenge of achieving en-ergy-efficient terascale computing.


NOTES

Wireless

Subcommittee

• Overview

• Featured Papers

• Evening Session

• Tutorial

• Forum

(co-sponsored by RF, Technology Directions, and Wireless)

(co-sponsored by RF, and Wireless)


Sessions: 6,10, 20 [AP24,36,54] WIRELESS

ISSCC 2008 – WIRELESSSubcommittee Chair: Trudy Stetzler, Texas Instruments, Stafford, TX

OVERVIEW



� A 45nm CMOS 0.6-to-10GHz wideband-receiver front-end [6.7]




� A discrete-time WiFi/WiMAX receiver that enables process-node scaling [20.4]


� Wireless USB at 480Mb/s is now possible with the complete integration of 14-band UWB transceiver [6.4]

� Software-defined radio receiver operates from 0.6 to 10GHz [6.7]

� Highly-integrated transceiver opens the door to low-cost multi-media [10.2]

� Low-cost phones for the masses, based on fully-integrated radio SoCs [10.4,10.5,10.6]

� Highly-integrated radio SoC enables low-cost and high-performance wireless LAN [20.2]

� New discrete-time architecture enables radios to scale with Moore’s law to future processes [20.4]

SPECIAL-TOPIC SESSIONMEMS for Frequency Synthesis and Wireless-RF Communications

(or Life without Quartz Crystals) [SE2](co-sponsored by RF, TD, and Wireless)

TUTORIALDigital Phase-Locked Loops [T5]

FORUMArchitectures and Circuit Techniques for Nanoscale RF CMOS [F3](co-sponsored by RF, and Wireless)


Session: 6 [AP24,25] WIRELESSFEATURE

UWB Potpourri

A Fully-Integrated 14-Band 3.1-to-10.6GHz 0.13μm SiGe BiCMOS UWB RF Transceiver [6.4]Alereon

A 0.6-to-10GHz Receiver Front-End in 45nm CMOS [6.7]NXP Semiconductors


� The state-of-the-art in UWB has evolved from proof-of-concept to fully-integrated commercial transceiver implementations.

� UWB solutions have several major applications, including high-data-rate communications, ultra-low-power short-distance moderate-data-rate communications, ranging and localization, and radio imaging.

� Broadband wireless systems such as UWB, use broad regions of the spectrum, for example, from 3.1 to 10.6GHz, as well as the 24GHz band for the abovementioned applications. Transmission is at relatively modest power levels, while high data rate is achieved using wide bandwidth.

� State-of-the-art broadband performance requires the use of advanced semiconductor processes. Examples of such systems have been demonstrated in RF SiGe BiCMOS technology, as well as short-channel CMOS technologies, including 45nm CMOS.

� Emerging low-power radio technologies are being employed in body-area networks for health-care applications that use the body for wireless propagation.

NOVEL CONTRIBUTIONS

� A 1.8Gb/s high-data-rate transmitter using a FIR pulse generator [6.1]

� A pulse-based UWB transceiver with communication and localization capability [6.2]

� A CMOS UWB-communicating camera with 7×7 active pixels [6.3]

� A WiMedia-compliant UWB transceiver supporting band groups from 1 to 6 from 3.1 to 10.6GHz in 0.13μm SiGe BiCMOS [6.4]

� A low-power synthesizer for UWB using injection locking [6.5]


Sessions: 6 [AP24,25] WIRELESSFEATURE

� Spur reduction in UWB frequency synthesizers using I/Q calibration in single-sideband mixers [6.6]

� A demonstration of 45nm CMOS technology for broadband wireless applications [6.7]

� A 60GHz radio with integrated signal processor and up to 15Gb/s data-rate capability [6.8]

� Ultra-low-power transceivers for body-area networks that will be employed for healthcare applications [6.9]


� UWB hardware will allow for wireless connection of high-definition audio/video equipment, obviating the need for cables or wires. [6.1, 6.8]

� UWB systems will enable accurate ranging and radio imaging. [6.2, 6.4]



CELLULAR TRANSCEIVERS

Single-Chip Tri-Band WCDMA/HSDPA Transceiver without External SAW Filtersand with Integrated TX-Power Control [10.2]Analog Devices; Federico Beffa Engineering

A Fully Integrated Quad-Band GPRS/EDGE Radio in 0.13μm CMOS [10.4]Broadcom

A 24mm2 Quad-Band Single-Chip GSM Radio in 90nm Digital CMOS [10.5]Texas Instruments

Integration of a SiP for GSM/EDGE in CMOS Technology [10.6]Infineon


� Mobile phones are the world’s most ubiquitous consumer-electronics device. Over one billion handsets are sold each year (more than 30 for every second of every minute of every hour of every day of the year), and today, there are over two billion subscribers worldwide. Yet two-thirds of the global community is still unconnected and underserved. Bringing mobile-phone services to the developing world requires continuing decreases in the cost and power consumption of mobile-phone silicon chips.

� For more sophisticated mobile-phone consumers, features drive the market. As the customers of future phones demand more-and-more features without increasing size or cost, mobile-phone silicon chips must reach new levels of integration, performance, and power consumption.

� Transceivers for GSM-based applications, including GPRS and EDGE, have achieved ultra-high levels of integration by eliminating costly external components such as filters. However, until now, transceivers for 3G-based applications, including WCDMA and HSDPA, have not been able to achive the level of compactness reached by GSM-based devices.

NOVEL CONTRIBUTIONS

� A novel low-noise RF notch-filter design is the enabling technology for the first WCDMA transceiver achieving competitive performance without external RX SAW filters or LNAs (a typical tri-band WCDMA transceiver requires 6 SAW filters and 3 LNAs). [10.2]

� The highest silicon-chip integration level ever achieved for GSM-based applications including GPRS and EDGE. [10.4, 10.5, 10.6]

� Demonstration of a full GSM/EDGE system including RF, baseband, and even the power-management unit in a single small package. [10.6]




� Low-cost small-size 3G mobile phones allowing powerful mobile multimedia and internet experience. [10.2]

� Low-power GSM and EDGE mobile phones [10.4]

� Low-cost GSM mobile phones to enable the developing world to become connected [10.5]

� Full-featured GSM and EDGE mobile phones to satisfy the insatiable appetite for new features, to serve more sophisticated consumers [10.6]


Sessions: 20 [AP54] WIRELESSFEATURE

WLAN and WPAN

A Dual-Band CMOS MIMO Radio SoC for 802.11n Wireless LAN [20.2]Atheros Communications; Stanford University

A Scalable 2.4-to-2.7GHz WiFi/WiMAX Discrete-Time Receiver in 65nm CMOS[20.4]STMicroelectronics


� Existing 802.11n devices consist of separate transceivers and baseband/MAC ICs

� Existing radio ICs do not easily scale with process technology

NOVEL CONTRIBUTIONS

� Integration of the transceiver for 802.11n along with the baseband PHY and MAC functions on a single die [20.2]

� An innovative merged switch-capacitor mixer, filter, and a charge-redistribution interleaved SAR ADC which simplifies the scaling of radio ICs with process technology [20.4]


� Highly-integrated low-cost 802.11n transceiver SoC has immediate significance in enabling high-volume low-cost high-performance wireless-LAN applications [20.2]

� As process technology shrinks further, scalable radio architectures allow for fast-time-to-market integration of the radio along with the digital components [20.4]





Organizer: Christian Enz, CSEM, Neuchâtel, SwitzerlandChair: Ernesto Perea, STMicroelectronics, Crolles, France

Co-Chair: Ken Cioffi, Altierre, San Jose, CA

OVERVIEW

� Many recent start-ups are now proposing silicon (Si) MEMS resonators as a replacement for quartz resonators, which remain a crucial component in almost any electronic system for basic frequency and time reference. This Special Topic Session will give an overview on the recent developments made in Si MEMS resonators in achieving this goal. Technological and electronic solutions for implementing highly stable and accurate temperature-compensated frequency reference synthesis modules covering a wide range of frequencies will be presented. Also addressed will be the many challenges such as stability, phase noise, packaging, reliability, and cost concerns as well as the perspective of integrating the MEMS devices together with other passives such as BAW resonators ultimately leading to a single-chip radio chip in an SiP

OBJECTIVE



CHALLENGE





STRUCTURE“Silicon Resonators for Ultra-Compact High-Performance Timing References”Bernhard Boser, Chief Scientist, SiTime

Silicon MEMS resonators are processed and packaged using standard CMOS equipment and flows. Smaller size, re-duced component count, and low processing cost are strong arguments motivating the replacement of quartz withMEMS.

Recent innovation removes long-term drift as the main obstacle to using MEMS resonators as precision timing refer-ences. It is accomplished with a unique package that hermetically seals the device in the silicon wafer and ensures acontaminant-free environment. These results have been transferred to the production floor and general-purpose pre-cision clocks based on MEMS resonators are now in volume production.

Owing to their small size, present MEMS resonator designs exhibit elevated phase noise and jitter compared to clocksbased on high-quality crystals. This shortcoming is addressed with new resonator structures that operate at signifi-cantly higher power-levels. These devices will enter the market in the near future and enable performance-critical ap-plications such as high-speed serial communication and RF to be served by MEMS. Increasingly, MEMS resonatorswill be integrated monolithically with application-specific integrated circuits, and in the near term we will witness thegradual replacement of quartz in performance-, size-, and cost-critical applications.

“Micromechanical Circuits for Communications-Grade Frequency Control”Clark Nguyen, UC Berkeley

Recent advances in vibrating RF MEMS technology that yield on-chip resonators with Q’s over 10,000 at GHz fre-quencies and excellent thermal and aging stability, have now positioned vibrating micromechanical devices as strongcandidates for inclusion into a number of future wireless-communication sub-systems. To date, on-chip reference os-cillators that meet GSM phase noise specifications and filters with tiny percent bandwidths, yet, low insertion loss, havebeen realized in this technology. The ultimate extent of the performance and economic benefits afforded by vibratingRF MEMS devices will likely grow exponentially as researchers begin to perceive them more as circuit building blocksthan as stand-alone devices. In particular, when integrated into micromechanical circuits, in which vibrating mechan-ical links are connected into larger more-general networks substantial improvements in the performance of the abovecircuits is expected. In addition, previously unachievable signal-processing functions become possible, such as re-configurable RF channel-selecting filter banks and ultra-stable reconfigurable oscillators.

“Integrating Si-MEMS, BAW Resonators and RF-CMOS in a SiP For Ultra-low-power Radio”J. Baborowski, CSEM, Neuchatel, Switzerland

Current wireless applications are setting increasing demands for the oscillators’ size, power consumption, and price.High-Q silicon MEMS resonators have great potential for on-chip high frequency applications, integrated-circuit clockgeneration, and other applications based on a stable frequency-reference signal. The thermal compensation of the sil-icon resonator as well as the development of miniature inexpensive lead-free packaging solutions represent, howeverreal technical and scientific challenges.

Two types of silicon resonators with AlN piezoelectric activation will be presented. The first type, the extensional moderesonator, exhibits a Q factor in vacuum as high as 120,000 and a mainly linear temperature coefficient of frequency(TCf) of -28.5+/-1ppm/°C. The second type, a triple tuning fork, presents a zero first order TCf that has been obtainedat the device level by balancing the negative temperature coefficient of stiffness (TCE) of Si and AlN with the positiveTCE of SiO2. The same technology platform enables the co-integration of Si-resonators with RF BAW filters. Wafer-vacuum-level packaging is the key solution to fabricating a miniaturized ultra-low-power radio.



“RF MEMS for Reconfigurable Radio”K. Masu, Tokyo Institute of Technology

In the wireless IT era, wireless transceivers found in mobile phones, PCs, PDAs, etc., are required to be multi-band/multi-mode. For multi-band transceivers, a simple solution is the use of many RF CMOS circuit blocks, which leadsto an increase in circuit area. Another solution is a reconfigurable RF circuit, where one circuit can operate as various-wireless-standard circuit block. RF MEMS components and devices have potential of improving RF circuit performance.Furthermore, they will help create small, high-performance implementations of reconfigurable RF CMOS circuits. Sev-eral kinds of variable MEMS inductors and variable MEMS capacitors, their application to reconfigurable RF CMOS cir-cuits, and their future application will be discussed.

RECAP

The Technology-Directions Subcommittee together, with the RF and Wireless Subcommittees, is pleased to pres-ent a Special-Topic-Session-format overview on how recently developed MEMS resonators can be used for fre-quency synthesis and/or time reference, and how they can be combined with other MEMS devices for the designof reconfigurable low-power radios. Four top experts in the field will give different perspectives and discuss themany challenges remaining to achieve a crystal-clear(less) future “life without quartz”.


Tutorial: T5 [AP6] WIRELESS

TUTORIAL

Digital Phase-Locked LoopsMichael H. Perrott, MIT, Cambridge, MA

OVERVIEWPhase-locked-loop (PLL) circuits are a key component of most modern communication circuits, and are also usedin a variety of digital-processor applications in order to generate high-frequency low-jitter clock sources. Here,we examine the issue of digital implementation of these structures, with the aim of achieving excellent noiseperformance. Basic concepts of classical analog PLL structures will first be examined, followed by an overviewof digital-PLL structures, and their associated circuit-implementation issues. Higher-level design and simulationtechniques are presented, as well as several case studies of implemented examples.

SPEAKER BIOGRAPHYMichael H. Perrott received the B.S. degree in Electrical Engineering from New Mexico State University, LasCruces, NM, in 1988, and the M.S. and Ph.D. degrees in Electrical Engineering and Computer Science from theMassachusetts Institute of Technology, in 1992 and 1997, respectively. From 1997 to 1998, he worked at Hewlett-Packard Laboratories in Palo Alto, CA, on high-speed circuit techniques for delta-sigma synthesizers. In 1999,he was a Visiting Assistant Professor at the Hong Kong University of Science and Technology, and taught acourse on the theory and implementation of frequency synthesizers. From 1999 to 2001, he worked at SiliconLaboratories in Austin, TX, and developed circuit and signal-processing techniques to achieve high-performanceclock-and-data-recovery circuits. He is currently an Associate Professor in Electrical Engineering and ComputerScience at the Massachusetts Institute of Technology, and focuses on high-speed circuit and signal-processingtechniques for data links and wireless applications.


Forum: F3 [AP] RF; WIRELESS

GIRAFE DESIGN FORUM

Architectures and Circuit Techniques for Nanoscale RF CMOS

OBJECTIVERF CMOS has become a mature technology over the past decade. RF-SoC realizations of wireless systems are standardtoday for connectivity systems, where first attempts are being made to integrate everything, even the poer amplifier (PA),for WLAN or for DECT. The volume requirements of low-cost GSM/GPRS/EDGE mobile phones are driving these SoCsfrom 0.13µm to nanoscale technologies. 3G and 4G systems require the use of 45nm or even 32nm technologies in orderto cope with the power and cost targets. Area-efficient implementation of RF, mixed-signal, and power-management func-tions will be the foundation for successful deployment of SoCs in these technologies. The high fT of nanoscale CMOS willbe a key enabler for the use of RF CMOS in millimeter-wave systems for data transmission or radar applications.

AUDIENCE Attendance is limited and preregistration is required. This all-day Forum encourages open information exchange.

The targeted participants are circuit designers and concept engineers working on wireless systems, who want to learnabout the impact of nanoscale technologies on circuit and system design.

SCOPECMOS technologies at 65nm and below are a challenge for RF and mixed-signal circuit designers. The Forum will presentinsights into the design requirements provided by leading industry experts. Nanoscale design must cope with the low sup-ply voltage, while manufacturing and variability aspects are considered. The increasing performance of digital circuitry(with respect to power and speed) leads to new architectures based on changes of tradeoffs for integrating analog, RF, anddigital functions. Especially for RF mixed-signal and power-management circuitry, nanoscale CMOS transistors and pas-sives might not provide better performance figures except for the pure fT increase of the transistors. Therefore, Moore’slaw will not hold for these circuits, whereas the industry is still forced to follow the predestined shrink path in order to pro-vide each year 1-billion cell-phone SoCs with ever-increasing feature sets.

PROGRAMThe Forum will begin with three talks that will provide an overview of the analog and RF performance perspectives onnanoscale RF CMOS, from both the research and commercial points of view. Stefaan Decoutre (IMEC) will talk abouttoday’s research activities at 32nm and below. His focus will be on alternative device architectures providing increased ro-bustness to short-channel effects. The commercial view will be covered by Shine Chung (TSMC) talking about nanoscale-RF-CMOS foundary requirements. Statistical variations are a new phenomenon seen in nanoscale technologies, which willbe described by Marcel Pelgrom (NXP).

The final talk before lunch emphasizes architectural trends and requirements for RF SoCs in nanoscale technologies. Khur-ram Muhammad (TI) will share his insights on fully-integrated radios in deep-submicron CMOS.

The afternoon is dedicated to actual designs in nanoscale RF CMOS, starting with Chris Rudell (Intel) talking about a 45nmCMOS transceiver targeting WiMAX. Didier Belot (STMicroelectronics) will cover the mm-wave frequency range, whichmight likely be an area for future application of RF CMOS. The talk given by Domine Leenaerts (NXP) will compare actualUWB implementations (from 90nm down to 45nm) with respect to circuit performance, ease of scaling, and size. Finally,Lukas Doerrer (IFX) will describe the design and performance of some basic building blocks in 45nm CMOS.

The Forum will conclude with a panel discussion, where the attendees have the opportunity to ask questions and to sharetheir views.



PROGRAM

Organizer: Stefan Heinen, Infineon Technologies, Duisburg, GermanyCo-Organizer: Francesco Svelto, University of Pavia, Pavia, ItalyCommittee:

Jan Craninckx, IMEC, Leuven, BelgiumMototsugu Hamada, Toshiba, Kawasaki,JapanDomine Leenaerts, NXP, Eindhoven, NetherlandsChris Rudell, Intel, Santa Clara, CA

Forum Agenda

Time Topics

8:00 Breakfast

8:15 IntroductionStefan Heinen, Infineon Technologies, Duisburg, Germany

8:45 Analog and RF Performance Perspectives of (Sub-) 32nm CMOSStefaan Decoutere, IMEC, Leuven, Belgium

9:30 Foundry Technologies for Nanoscale RF IntegrationShine Chung, TSMC, Hsinchu, Taiwan

10:15 Break

10:45 Nano-meter CMOS is a Statistical Challenge!Marcel Pelgrom, NXP, Eindhoven, Netherlands

11:30 RF SoC Architecture Trends and Requirements in Deep-Submicron CMOS: A Perspective

Khurram Muhammad, TI, Dallas, Texas

12:15 Lunch

1:15 Low-Voltage, Transceiver Design in 45nm CMOS with an Emphasis on WiMAXChris Rudell, Intel, Santa Clara, CA

2:00 Millimeter-Wave Design in Nanoscale CMOSDidier Belot, STMicroelectronics, France

2:45 Break

3:15 UWB Circuit Design in 90nm, 65nm, and 45nm CMOSDomine Leenaerts, NXP, Eindhoven, Netherlands

4:00 Circuit Design in 45nm CMOS ProcessLukas Doerrer, Infineon, Villach, Austria

4:45 Panel Discussion

5:15 Conclusion

Wireline

Subcommittee

• Overview

• Featured Papers

• Evening Session

• Tutorial

• Forum

• Trends


Sessions: 5, 11, 25 [AP23,38,70] WIRELINE

ISSCC 2008 – WIRELINE

Subcommittee Chair: Franz Dielacher, Infineon Technologies, Villach, Austria

OVERVIEW




� A 10.3125Gb/s Burst-Mode CDR Circuit Using a Δ∑ DAC [11.4]

� A 90nm CMOS DSP MLSD Transceiver with Integrated AFE for Electronic Dispersion-Compensation of Multi-Mode Optical Fibers at 10Gb/s [11.7]


� An 800MHz 122dBc/Hz-at-200kHz Clock Multiplier Based on a Combination of PLL and Recirculating DLL [25.2]


� Increasing bit rates with legacy channels require higher-performance equalizers within broadband receivers in order to maintain low system-integration costs. A number of innovative low-power CMOS equalizers operating at multi-Gb/s rates that work on a variety of channels are presented [5.1, 5.3, 5.4, 5.8].

� The first fully-integrated CMOS 10Gb/s Ethernet transceivers enable the deployment of low-cost enterprise networks using both copper and multi-mode optical fiber by combining innovative analog- and digital-signal-processing techniques. Both target rigorous IEEE standards: 802.3an (10GBASE-T) for UTP copper [5.5], and 802.3aq (10GBASE-LRM) for legacy multi-mode fiber [11.7].

� Passive optical networks (PONs) have emerged as a viable solution for the last-mile portion of wireline communication systems. These receivers need to operate in burst-mode, which presents significant technical challenges. Today, the fastest burst-mode receiver is 1.25Gb/s. Under the emerging standard 802.3av, faster 10Gb/s burst-mode receivers are needed. A number of blocks for next-generation PONs operating near 10Gb/s are presented [11.1, 11.3, 11.4].

� The internal synchronization-circuitry is the heart of any communication IC. As proof of the astonishing speed capabilities of CMOS, two clock dividers approaching the 100GHz barrier are presented in [25.5, 25.8].


Sessions: 5, 11, 25 [AP22,38,70] WIRELINE

SPECIAL-TOPIC SESSIONTrends and Challenges in Optical-Communications Front-End [SE7]Optical communications have been undergoing revolutionary transformations, where advances in electronic signal pro-cessing are taking a lead in bringing improved cost-effective system performance. Silicon technologies, with fine-lineCMOS, significantly extended the boundaries of digital signal processing versus analog, and, what was impractical a fewyears ago is now aimed for production in optical systems. What role will digital processing play at the existing and emerg-ing data rates? What are the requirements for the components? Experts from industry and academia will share their viewson these topics.

TUTORIALBasics of High-Speed Chip-to-Chip and Backplane Signaling [T10]This Tutorial presents the basics of high-speed transceivers with emphasis on circuit-design requirements for chip-to-chipand backplane signaling. The topics include channel characterization and equalization, MUX and DEMUX design, decisioncircuits, as well as clock- and data-recovery (CDR) circuits and concepts. Approximately half of the Tutorial will be de-voted to I/O blocks, and half to CDR circuits. The goal of the Tutorial is to help the audience absorb the related papers pre-sented at the Conference.

FORUMFuture of High-Speed Transceivers [F5]This Forum will cover the system challenges and circuit solutions needed to address chip-to-chip, board-to-board, and sys-tem-to-system communications at data rates ranging from 3Gb/s to up to 40Gb/s. The performance limits and tradeoffsof various equalization techniques including transmit pre-emphasis, linear receive equalizers, decision-feedback equaliz-ers (DFE), and analog-to-digital conversion (ADC) followed by digital signal processing (DSP), will be presented. The over-arching theme will be the design of circuits to enable next-generation data rates in both electrical and optical systems.


Session: 5 [AP22] WIRELINEFEATURE

High-Speed Transceivers

A 40Gb/s CMOS Serial-Link Receiver with Adaptive Equalization and CDR [5.2]National Taiwan U.

A 10Gb/s IEEE 802.3an-Compliant Ethernet Transceiver for 100m UTP Cable in0.13µm CMOS [5.5]Teranetics


� Currently, the speed of equalizers and CDRs on a single CMOS chip is limited to 10Gb/s.

� The speed of fully-integrated Ethernet transceivers is limited to 1Gb/s.

NOVEL CONTRIBUTIONS

� Integration of analog equalization and CDR for a 40Gb/s receiver on a single chip [5.2]

� The first integration of a 10Gb/s IEEE 802.3an-compliant Ethernet transceiver in 0.13μm CMOS based on DSP techniques [5.5]


� Enabling inexpensive low-power high-speed communications beyond 40Gb/s [5.2]

� Enabling widespread use of 10Gb/s Ethernet low-cost copper data-links such as UTP cables [5.5]


Sessions: 11 [AP38] WIRELINEFEATURE

OPTICAL COMMUNICATION

A 2.7V 9.8Gb/s Burst-Mode TIA with Fast Automatic Gain Locking and CoarseThreshold Extraction [11.1]Ghent University; FWO Vlaanderen; IWT Vlaanderen; Centre for Integrated Photonics

A 10.3125Gb/s Burst-Mode CDR Circuit Using a ΔΣ DAC [11.4]NTT

A 90nm CMOS DSP Maximum-Likelihood Sequence-Detection Transceiver withIntegrated AFE for Electronic Dispersion Compensation of Multi-Mode OpticalFibers at 10Gb/s [11.7]ClariPhy Communications


� Today, the fastest burst-mode receiver is 1.25Gb/s. Under the emerging standard 803.2av, faster 10Gb/s burst-mode receivers are needed.

� Installed-base multimode fiber supports a data rate of only 1Gb/s with traditional optical receivers. Moving to 10Gb/s requires innovations in transceiver architectures and circuits.

NOVEL CONTRIBUTIONS

� New gain-locking architecture removes error caused by analog impairments [11.1]

� Digitally-assisted control replaces analog filtering, hence allowing an efficient coding in emerging standards [11.4]

� Novel ADC-DSP-based architecture allows much more complex equalization [11.7]


� PON architectures will be able to communicate at 10Gb/s data rate [11.1,11.4 ]

� Data rate over legacy lines can be further increased [11.7]


Session: 25 [AP70] WIRELINEFEATURE

Building Blocks for High-Speed Transceivers

A 27Gb/s Forwarded-Clock I/O Receiver Using an Injection-Locked LC-DCO in45nm CMOS [25.1]Intel; University of Washington

An 800MHz-122dBc/Hz-at-200kHz Clock Multiplier Based on a Combination of PLLand Recirculating DLL [25.2]Conexant System


� DLLs have better jitter performance compared to PLLs, because DLLs do not suffer from jitter accumulation. However, mismatches in the delays, and the up and down currents in the charge pump cause large phase offsets. These offsets result in a substantial amount of reference spur, which in the best case is as large as -37dBc.

� Forwarded-clock parallel-data I/Os suffer from high-frequency jitter amplification over lossy channels. An adjustable-clock-phase PLL is needed at the receiver to filter the jitter and to reliably recover the data. Such a PLL occupies significant area and consumes a lot of power.

NOVEL CONTRIBUTIONS

� An injection-locked DCO is used to clean up the clock, and also provide a phase-deskew range of 1UI that is insensitive to PVT variations. The circuit area is only half the present state-of-the-art, and the power efficiency is 1.6mW/Gb/s [25.1]

� The advantages of a PLL and a DLL are combined for the first time. A new charge-pump design that minimizes the mismatch between the up and down currents is described. These techniques reduce the jitter by reference spur to -48dBc. [25.2]


� Injection locking is used both to clean up the jittery clock, and also to adjust the clock phase to recover data. This eliminates a large-area power-hungry PLL. [25.1]

� A higher-precision clock generator will enable increased data rates in future serial transceivers. [25.2]


Special: SE7 [AP62] WIRELINE


Trends and Challenges in Optical-Communications Front-End

Organizers: Yuriy M. Greshishchev, Nortel, Ottawa, CanadaTakuji Yamamoto, Fujitsu Laboratories, Kawasaki, JapanChair: Naresh Shanbhag, University of Illinois, Urbana, IL

OVERVIEWOptical communications have been undergoing revolutionary transformations in which advances in electronic signal pro-cessing have taken the lead in bringing improved cost-effective system performance. Silicon technologies with fine-lineCMOS have significantly extended the boundaries of digital signal processing versus analog, and, what was impractical fewyears ago, is now aimed for production in optical systems. Areas where signal processing helps to improve optical sys-tem include: electronic dispersion compensation, advanced coding and detection techniques (for example, FEC and MLSE),and optical modems with coherent detection. As a result, a modern coherent optical system is no longer limited to the least-spectrally-efficient OOK-modulation format, but is open to a wide variety of more-efficient digital-communications for-mats, such as QPSK, DQPSK, and QAM. Now, what role will digital processing play at existing and emerging data rates?What are the requirements for the components? Experts from industry and academia will share their views on these top-ics.

OBJECTIVETo discuss recent advances in optical front-ends, emerging data rates, and modulation formats, in solving optical-com-munications problems, such as electronic equalization, improvement in channel spectral efficiency, and components cost

To bring designers’ attention to the new challenging opportunities in the area of multi-gigabit data converters, and signal-processing algorithms and circuits

CHALLENGEHow optical communications can take advantage of well-established digital modulation formats, and DSP techniques, de-spite tremendous speed requirements for the data converters and signal-processing circuits?

What IC designers and DSP specialists should focus on in helping optical systems become more cost-effective


SPECIAL: SE7 [AP62] WIRELINE

STRUCTURE

“PON Propaedeutics”David Bowler, Motorola, Lowell, MAPassive optical networks (PONs) enable first-mile customer access that is fast, flexible, and cost-effective. But, deliveringtriple-play services over a PON carries with it a unique set of challenges, and opportunities for the creative circuit designer.Overall, system and physical-layer subsystem architectures will be discussed along with the design challenges surround-ing a multi-point-to-point burst-mode link. Specific topics that will be discussed include burst-mode transmitters, burst-mode receivers, clock and data recovery, the dispute over extinction ratio, the ranging protocol, non-linear optical problems,and future opportunities for higher-performance and lower-cost designs.

“10Gb/s Optical Data Links With DSP-Based Dispersion Compensation’ Norman L. Swenson, ClariPhy Communications, Irvine, CAThe IEEE 10GBASE-LRM standard, recently adopted for 10G Ethernet, requires electronic dispersion compensation (EDC)to combat modal dispersion on multimode fiber. 10G telecom links are increasingly relying on EDC to mitigate the effectsof PMD and chromatic dispersion. The conventional method of implementing EDC is an analog tapped delay-line or an ana-log implementation of a decision feedback equalizer. More recently, DSP-based CMOS solutions have emerged, offeringadvantages of predictability, scalability, and SoC integration, and enabling implementation of a theoretically optimal algo-rithm: MLSD. We will report on trends in CMOS DSP-based EDC for 10G single-mode and multimode optical fiber links.

“40Gb/s Transport Milks DSP Technology”John Sitch, Nortel, Ottawa, CanadaSilicon technology has now progressed to the point where it is possible to perform comprehensive signal processing onsignals at 40Gb/s, or even 100Gb/s. What transforms the possibility into reality is economics – it is cost-effective to re-place expensive optics with electronic signal processing. Data converters represent possible bottlenecks to be overcome,with suitable design and technology, but electronic technology leads to more operational flexibility, as it is easier to makethe equipment self-adapting. We will discuss the types of impairment that afflict optical communications, and the steps toovercome them by using electronic signal processing, with design examples developed at Nortel, such as QPSK- basedprocessing.

“Signal Processing Challenges Towards 100Gb/s Optical Links” Andrew Singer University of Illinois, Urbana, ILThe optical industry’s transition to 10Gb/s heralded a new era in which signal-processing-enhanced receivers emerged asa low-cost approach to solving problems of dispersion, noise, and nonlinearity in optical links. The design of EDC receivershas been enabled by the relentless progress in the integration of complex signal-processing architectures and circuitry atoptical line rates. Today, the industry is looking forward to 40Gb/s and 100Gb/s systems, where it is expected that new pho-tonic materials, together with advanced modulation and coding techniques, signal processing and mixed-signal circuits,will be leveraged. This talk analizes factors that limit optical-link performance, and highlights exciting opportunities for thesignal-processing and circuits communities to work jointly in designing the optical links of the future.

RECAPPerformance improvement and cost efficiency of optical links are largely in the hands of the IC design community and sig-nal-processing engineers. Silicon integrated circuits potentially allow us to tackle all fiber impairments at 10 –to-20Gb/sdata rates using sophisticated DSP algorithms, manageable power consumption, and digital gate count. Experts from in-dustry and academia will share their view of the importance of electronic signal processing, its future, and integrated-cir-cuit design challenges. The Session will cover a variety of application areas: last-mile access, short-to-mid-range datalinks, and long-haul optical transport.


Tutorial: T10 [AP8] WIRELINE

TUTORIAL

Basics of High-Speed Chip-to-Chip and Backplane SignalingBasics of High-Speed Chip-to-Chip and Backplane SignalingAli Sheikholeslami, University of Toronto, Toronto, Canada

OVERVIEW

� Channel characterization and equalization.

� MUX and DeMUX designs.

� Decision circuits.

� Clock- and data-recovery (CDR) concepts and circuits.

SPEAKER BIOGRAPHYAli Sheikholeslami is currently an Associate Professor at the University of Toronto. He is involved in the designof circuits for high-speed signaling, focusing on applications in chip-to-chip and backplane signaling. He re-ceived his PhD in ECE from the University of Toronto, in 1999.


Forum: F5 [AP92] WIRELINE

FORUM

Future of High-Speed Transceivers

ObjectiveWith the ever-increasing data rates required in modern systems, high-speed transceivers have found applications in abroad variety of systems. Once confined to optical networks and data centers, multi-gigabit/sec serial-link technology hasbecome widespread in applications ranging from HDTVs to cell phones, that is, anywhere that large quantities of informationneeds to be sent from one point to another. As a consequence, mixed-signal designers must understand the circuits re-quired to transmit and receive high-speed data, the signal-integrity issues involved in system design, and the consequencesof deep submicron CMOS technology.

Audience This Forum is targeted toward circuit designers working on high-speed transceiver technology. The applications includechip-to-chip, board-to-board, and system-to-system interconnect, including the use of both electrical and optical signal-ing.

ScopeA group of experienced researchers and designers will review the requirements of transceiver technology, and cover abroad range of applications ranging from ultra-low-power electrical chip-to-chip links, as short as a few centimeters, to com-plex equalization strategies for multi-km-long optical networks.

ProgramThe Forum begins with a presentation from Jared Zerbe (Rambus), who will overview many of the challenges designersface in current and future-generation wireline transceivers. After covering the loss mechanisms present in electrical chan-nels, practical circuit solutions to address current and future transceiver demands will be described. In the second talk,Thomas Toifl (IBM) will continue the discussion on electrical communications with a focus on the design techniques re-quired to enable ultra-low-power and area-efficient transceivers. Next, Andy Joy (Texas Instruments) will describe the ap-plication of ADCs and DSP to the challenge of receiver equalization. System requirements and circuit solutions to meet theequalization and clock- and data-recovery demands of multi-gigabit/s systems will be covered. Koichi Yamaguchi (NEC)will then discuss duo-binary signaling as an alternate approach to achieving high-performance communication acrossband-limited channels. Circuits that transmit, equalize and receive, and perform the clock- and data-recovery of duo-binarysymbols will be described. While the majority of the previous presentations focus on the loss portion of the SNR problem,the fifth presentation from Joy Laskar (Quellan) will address noise. Specifically, active crosstalk cancellation techniquesand circuits will be described in the context of both wireline and wireless receivers.

The next two speakers will shift focus from electrical signaling to optical signaling. Hirotaka Tamura (Fujitsu) will beginthe discussion by covering the roadmap of high-speed I/Os and interconnection technology. The technology limitations ofboth circuits and packaging technology will be described. The second half of this presentation will be on the implementa-tion of integrated circuits required to interface electrical systems to optical fibers and vice versa. The final presenter, OscarAgazzi (Clariphy), will cover the design of DSP-based transceivers for single- and multi-mode optical fibers, including DFEand maximum-likelihood-sequence-estimation (MLSE) receivers. The theoretical and practical aspects of an experimentaltransceiver will be discussed.


Trends WIRELINE

TRENDS IN WIRELINE COMMUNICATIONS

Wireline technologies continue to be driven by two forces, namely, CMOS features-size scaling to 45nm andbelow, and the emergence of new applications techniques, such as passive optical networks (PONs), targetinghome connections. At ISSCC 2008, presentations reflecting these trends will be given:

Network requirements are being enhanced to support consumer demand for “triple-play” (voice, video, and data).The widespread deployment of access networks such as passive optical networking (PON) provide home-accessdata rates up to 10Gb/s. PON reduces system cost by sharing fiber between multiple customers. This sharingchallenges transceiver designers by requiring burst-mode operation of amplifiers and clock-recovery circuits.Continuing innovation is expected in this area for the foreseeable future.

40Gb/s data rates are now being readily accommodated with low-cost power-efficient CMOS chips. This years’ISSCC highlights 40Gb/s clock- and data-recovery circuits and an equalizer, in advanced CMOS.

Backplanes are benefiting from the convergence of ever-improved electrical transceivers serving legacy and near-term applications with the first users of dense high-bandwidth optical transceivers to future systems.

The emergence of digital signal processing and software-based techniques replace building blocks which previ-ously have been analog. These techniques are applied to both electrical links such as 10Gigabit Ethernet, as wellas 10Gb/s optical-dispersion compensation that allows higher data rates across inexpensive multimode fibers.

ISSCC 2008Session Overview

Press-Release Material

•Condition of Publications

•Session Overviews


CONDITIONS OF PUBLICATION

PREAMBLE

• The Session Overviews to follow serve to capture the context, highlights,and potential impact, of the papers to be presented in each Session atISSCC 2008 in February in San Francisco.

• OBTAINING COPYRIGHT to ISSCC press material is EASY !

• You are welcome to use this material, copyright- and royalty-free, with the following understanding:

� That you will maintain at least one reference to ISSCC 2008 in the bodyof your text, ideally retaining the date and location. For detail, see theFOOTNOTE below.

� That you will provide a courtesy FAX of your excerpted press piece andparticulars of its placement, to 416-971-2286, Attention ISSCC PressRelations.

FOOTNOTE

• From ISSCC’s point of view, the phraseology included in the box belowcaptures what we at ISSCC would like your readership to know about this,the 55th appearance of ISSCC, on February 3rd to 7th, in San Francisco.

This and other related topics will be discussed at length at ISSCC 2008, the foremost global forum for new developments in the integrated-circuit industry. ISSCC, theInternational Solid-State Circuits Conference, will be held on February 3-7, 2008, at theSan Francisco Marriott Hotel.


Session 2 Overview / IMMD [AP16]

Image Sensors and TechnologyChair: Yong-Hee Lee, Samsung Electronics, Yongin-City, KoreaAssociate Chair: Jed Hurwitz, Gigle Semiconductor, Edinburgh, Scotland

The imaging area is one of the most exciting and dynamic areas of the electronics industry. Image sensors became pervasive whenwas after they were included inside most mobile phones. Although phone cameras continue to be a huge driver of the industry, thereare still new applications that arrive and continue to push the growth and innovation of the technology. This session highlights advancesin image sensors and technology in several areas: technology, readout circuits, and applications.

The opening paper 2.1 (EPFL) presents the largest 2-dimensional array of single-photon avalanche diodes ever presented. This imageris integrated with an array of time-to-digital converters to enable 3D imaging accurate to within millimeters, along with other applica-tions that can benefit from the accurate photon-counting capability. This chip represents the most advanced solution using this tech-nology that has ever been presented, and highlights that imaging is not just about capturing a pretty picture. Continuing on the themeof optimized solutions, Paper 2.2 (Yonsei U) explains a fully integrated device that can track the movement of an eyeball, were part ofthe algorithm for extracting the coordinate runs on an analog-processing circuit that exists between neighboring pixels. It is one of thefinest examples to date of pixel-plane processing, and highlights what smart imaging can do compared to conventional imaging andDSP, by delivering accurate results 5000 times a second while consuming only 100mW.

Paper 2.3 (Stanford U) represents a complete departure from regular imaging array structures by making an array of micro-arrays thatcontain extremely small CCD pixels. It has the potential to be used for depth and visual imaging, and uses the information that is pres-ent in the scene when the resolution is below the diffractive limit. The pixels in this work are 0.7μm, but commercial sensors are justnow going below 1.4μm and commercial lenses have diffraction limits that are greater than either of these dimensions. We hope thatthis concept will spark further research in this area.

Mobile digital still camera (DSC) and camcorder imaging is no longer all about pixel size, sensitivity and number of pixels, but now highdynamic range is also seen as an important characteristic. Papers 2.4 and 2.5 both demonstrate imagers with wide dynamic range.Paper 2.4 (Matsushita) combines the signal from multiple exposures in an accumulator inside the pixel, avoiding the need for exter-nal memories and data combining while Paper 2.5 (Toshiba) uses a charge-skimming technique and multiple reads with a small inter-nal memory to extend the dynamic range. The need for enhanced dynamic range is shared by a number of emerging markets such asautomotive, so we expect this type of technology to be increasingly used in the future. Paper 2.5 also highlights an increasing area ofinterest for extending the low-light imaging ability of sensors. In this work the color filter pattern on top of the sensor has been alteredfrom the 30-year-old Bayer pattern to use a white pixel instead of one of the two green pixels within the normal 2x2 pattern. This im-proves the sensitivity by nearly a factor of 2.

CMOS image sensors (CIS) have always promised low-power and low-voltage operation, not just for the mobile phone market, but fornew uses in biomedical and sensory applications, which have extremely low power requirements. The CIS presented in Paper 2.6 (NaraIST) achieves the best FoM for power consumption within an array by directly converting the image to a pulse-width modulated sig-nal within the pixel. It produces images, which may not yet be at the same low-light quality level as those produced by the best con-sumer imagers today, but are perfectly respectable for the intended applications. At the other extreme, high-speed high-performanceimaging requires high-performance readout mechanisms. The column-parallel cyclic ADC approach presented in Paper 2.7 (Brook-manlab) is one technique designed to address this requirement, and this paper addresses one of the accuracy limitations through cal-ibration.

The mobile market is becoming a commodity market and Paper 2.8 (Micron) shows a 2Mpixel sensor for the standard mobile imag-ing architecture (SMIA) standard with improved performance resulting from a clever use of a transistor within a shared-pixel scheme.Shared-pixel schemes emerged a number of years ago, and although there are only a few transistors to consider, there are still inno-vations resulting from the way they can be connected; this paper presents yet another way of operating a pixel, which saves one wireand improves the sensitivity.

CIS technology is heavily influenced by CCD technology. Many major improvements happened when devices such as pinned photodi-odes, micro-lenses and buried micro-lenses were transferred over to CMOS. The final 2 papers illustrate that it is possible to imple-ment a depleted hole, PMOS-style, pinned photodiode device on a local N-type substrate (Paper 2.9 from Kodak}) and a buried N-channelsource follower (Paper 2.10 from TU Delft), both of which are likely to have a major impact on the industry as they try to maintain per-formance while shrinking the pixel size.


Session 3 Overview / Analog [AP18]

Filters and AmplifiersChair: JoAnn Close, Analog Devices, San Jose, CAAssociate Chair: Vadim Gutnik, Impinj, Newport Beach, CA

Configurability and calibration are central topics in research on amplifiers and filters. Calibration is often required to compensate forvariations in silicon performance so that product yields are acceptable. Configurability also enables system integration in sensors andtransceivers, which operate in multiple modes and multiple data rates, particularly in the case of software-defined radios. The abilityto tune and configure analog blocks comes at a price however; calibration can be expensive and the overhead required for configura-bility can degrade performance. The circuits presented in this session demonstrate a variety of approaches to calibration and to allowflexible configurations without steep performance penalties.

The first three papers feature reconfigurable filter and amplifier circuits that use three different techniques to achieve a wide range ofgains and passband frequencies. Paper 3.1 (NEC) describes a 90nm CMOS filter that uses duty-cycle-controlled transconductors toprovide a choice of Butterworth, Chebyshev or Elliptic filter responses with passband frequencies varying from 400kHz to 12MHz. Thefilter in Paper 3.2 (Sony) uses a charge-domain technique to provide gains from -17 to 30dB and passband frequencies varying from8 to 14MHz. Paper 3.3 (University of Freiburg, IMTEK) describes a 0.13μm CMOS field-programmable analog array of 55 tunable Gm-cells that does not use any switches in the signal path and can implement gains between -15.6 and +15.6dB as well as a wide varietyof continuous-time filter functions with passband frequencies from 15 to 130MHz. The 6th-order 280MHz filter described in Paper 3.4(U Salento) is a low-power benchmark, drawing only 100μA from a 1.2V supply.

The first two amplifiers in the second part of the session feature very low offset and drift. The instrumentation amplifier described inPaper 3.5 (TU Delft) is optimized for high-side current sensing applications. It uses a 0.8μm BiCMOS process with high-voltage CMOSdevices to achieve an input voltage range from 1.9 to 30V. Chopping and auto zeroing are used together to yield an offset voltage lessthan 5μV. Paper 3.4 describes a cost-effective room-temperature-only trim technique that reduces both the offset and offset temper-ature drift of a MOS input operational amplifier. Offset drift in Paper 3.6 (TU Delft) is reduced by a factor of three, to 0.33μV/ºC. Thefinal paper, Paper 3.7 (TU Vienna) describes a 0.35μm SiGe BiCMOS transimpedance amplifier for optical signals that achieves a 130dBdynamic range using a two-stage compression scheme.


Session 4 Overview / High-Performance Digital [AP18]

MicroprocessorsChair: Don Draper, Rambus, Los Altos, CA Associate Chair: Ana Sonia Leon, Sun Microsystems, Santa Clara, CA

High-performance microprocessors are having an ever-larger economic impact not only in servers, high-performance computing, andenterprise and data centers, but also in gaming and digital multimedia applications. In addition to the ongoing need for higher per-formance and lower cost, these markets also require power management, high reliability, and fault protection. This session’s papersdescribe innovative architectural and circuit techniques are that make great strides in delivering on these needs. There are numerouschallenges including variability increases that result from nanometer process scaling, power consumption limits and architectural bar-riers to performance scaling.

Papers 4.1 and 4.2 (Sun Microsystems) describe a 16-core, 32-thread processor running at 2.3GHz in a 396mm2 65nm chip. The de-sign presents a significant advance in the effort to provide great performance for both throughput and single-threaded applications.Deep speculation modes enable high-level parallelism. Scout threads speculatively pre-fetch locks, critical code and data to improvesingle-threaded performance. Transactional memory allows atomic instruction execution to enable more efficient multi-threaded exe-cution. Dual high-bandwidth 5´5 networking switches connect the 16 cores, together sharing four 32kB instruction caches and eightL2 cache banks. The 96 transmit and 160 receive channels provide 680Gb/s throughput.

The migration in Paper 4.3 (IBM) of the 65nm SOI Cell Broadband Engine™ to 45nm SOI uses a mostly automated approach preserv-ing cycle-by-cycle behavior. The design demonstrates the value to design efficiency and performance provided by improved processtechnologies. Power is reduced by 40% and area by 34%. The SRAM has a separate power supply to preserve cell stability, which over-comes one of the most troublesome aspects of process scaling. Extensive design for manufacturability techniques address increasedvariability in 45nm.

The 90nm TILE64™ processor in Paper 4.4 (Tilera) integrates an astounding 64 cores, representing the largest number of general-pur-pose cores integrated on a commercial processor. The chip interconnects 16 cores with a dimensionally-constrained mesh network.The chip is optimized for networking and digital multimedia. Power varies from 170 to 300mW per tile. L2 cache sharing provides upto 4MB L3 cache.

Paper 4.5 (Renesas, Hitachi, Waseda U)) describes an SoC with eight cores in separate power domains, which achieves 8640MIPS and33.6GFLOPS. A parallelizing compiler assigns tasks to each core and optimizes power loading. Integrated power gating allows individualturn-off for each of the 8 cores, enabling much lower average operating power.

The 65nm Itanium® processor in Paper 4.6 (Intel) implements four dual-threaded cores with the largest number of transistors ever an-nounced for a microprocessor: 2.05 billion. The chip measures 21.5´32.5mm2 and dissipates 170W. It includes 30MB cache, has a peakmemory bandwidth of 34GB/s and limits power consumption using voltage-frequency scaling, which is increasingly common for thisclass of server processors. Soft-error-hardened latches and ECC-protected caches and register files are implemented to improve reli-ability, which is a challenging goal for a server chip with this level of integration in Paper 4.7 (Intel).

In summary, these processors present significant advances, not only in integration of more components, and increased performance,but with innovative ways of dealing with the challenges of scaling, power consumption and architectural performance limits.


Session 5 Overview / Wireline [AP22]

High-Speed TransceiversChair: Hui Pan, Broadcom, Irvine, CAAssociate Chair: Hong-June Park, POSTECH, Pohang, Korea

The market for high-bandwidth communication continues to drive the demand for higher speed transceivers. In the wireline arena,10Gb/s data transmission over copper channels (backplane PCB, UTP cable, etc.) for enterprise networking and data-center applica-tions is reaching maturity and commercialization using low-cost CMOS transceivers. At the same time, up to 40Gb/s data transmis-sion is being demonstrated over short channels. This trend is evident in the papers of this session.

The latest CMOS technology along with advances in design techniques has enabled us to continue to push the speed envelope. In ad-dition to integrating more powerful signal-processing functionality, such as FFE and DFE, on chip, innovative coding and circuit tech-niques help to overcome bandwidth limitations, adapt to channel variation, and tolerate PVT variations while lowering powerconsumption and cost.

Paper 5.1 (Hitachi) presents an 8Gb/s 90nm CMOS transceiver that uses a 5-Tap TX FFE and a 2-Tap RX DFE to equalize a 160cm back-plane channel with -36.8dB loss at 4GHz. The sampling clock is aligned directly to the center of data eye opening to avoid phase mis-alignment arising from the asymmetric jitter distribution when the quadrature clock is locked to the eye zero-crossing as withconventional CDR circuits. Paper 5.2 (National Taiwan U) demonstrates a 40Gb/s receiver in 90nm CMOS. A single-loop adaptive equal-izer and full-rate CDR circuit compensates for 10dB cable loss. Paper 5.3 (National Taiwan U) presents a 20Gb/s duobinary transceiverin 90nm CMOS for backplane application. The receiver recovers the 3-level duobinary data without the need to extract the clock andgenerate the two threshold voltages.

Paper 5.4 (Renesas) presents a 6Gb/s receiver that achieves low power consumption by using an efficient adaptive equalization circuitthat automatically drives low- and high-frequency amplitudes to the same level. Paper 5.5 (Teranetics) describes an all-CMOS 10Gb/sEthernet transceiver implemented in a 25×25mm2 BGA package that operates over 100m of UTP cable.

Paper 5.6 (Aeluros) presents a 10Gb/s transmitter in 0.13μm CMOS that supports multiple standards such as SFP+ and 10G BASE-KR without using passive inductors. Paper 5.7 (IBM Research) presents a high-swing 8.5Gb/s source-series-terminated transmitter in65nm CMOS. The 5b 2-tap FIR filter, the output impedance and the output swing can be programmed independently. It uses a 40×40μm2

T-coil to compensate the ESD parasitic capacitance and achieve a return loss of better than -16dB up to 10GHz. Paper 5.8 (POSTECH;Samsung) presents a 3.2Gb/s 2-drop single-ended DFE receiver in 0.18μm CMOS for DRAM interface. It includes internal reference-voltage generation and the LMS algorithm is used to compute the equalization coefficient.


Session 6 Overview / Wireless [AP24]

UWB PotpourriChair: Mark Ingels, IMEC, Leuven, BelgiumAssociate Chair: Domine Leenaerts, NXP Semiconductors, Eindhoven, Netherlands

Since the FCC opened the frequency spectrum from 3-to-10GHz allowing ultra-wide-band (UWB) operation, two main flavors havebeen proposed, namely multi-band OFDM UWB and impulse-radio (IR) UWB. WiMedia has embraced multi-band OFDM UWB as thecommunication protocol to achieve robust high data rates up to 480Mb/s over moderate distances. This protocol targets applicationslike wireless USB. On the other hand, IEEE 802.15.4a has specified a UWB PHY for low-data-rate communication with ranging capa-bilities, based on IR UWB. Applications are in wireless personal area (WPAN) and sensor networks, where battery longevity is of crit-ical importance but the distances are short.

UWB inherently features wide-band signal processing at RF and IF/BB of at least 500MHz. In IR-UWB systems, the challenge in the re-ceiver is to come up with architectures able to detect the very-short low-energy pulses with a minimum power consumption. At thetransmitter side the generated pulse shape must fulfill the FCC spectral mask. One of the major challenges for OFDM-based UWB isthe realization of a fast-hopping frequency generator.

The session begins with two designs that focus on CMOS IR UWB. Paper 6.1 (UC Davis) demonstrates a 1.8Gpulse/s UWB transmit-ter in 90nm CMOS. The transmitter uses an FIR pulse generator for accurate pulse shaping and spectrum control. Paper 6.2 (Instituteof Microelectronics) presents a 12-channel UWB transceiver with ranging capability in 0.18μm CMOS.

UWB techniques are applicable to more than just data communications. Paper 6.3 (USC) presents a UWB imaging camera. The CMOSchip interfaces 2×2 antennas to a 7×7 simultaneous pixel array achieving 10º spatial resolution.

The next 4 papers are OFDM UWB based. Paper 6.4 (Alereon) demonstrates a fully integrated RF transceiver in SiGe BiCMOS technology.The packaged transceiver includes the T/R switch and RF balun. Paper 6.5 (U Padova; Infineon) addresses the fast hopping frequencyrequirements by applying a sub-harmonic injection locking technique, resulting in a hop time smaller than 4ns. Paper 6.6 (NationalChiao-Tung U) uses a single PLL and 3 single-side-band mixers to hop over all 14 frequency bands. Paper 6.7 (NXP Semiconductors)demonstrates a receiver front-end up to 10GHz in 45nm CMOS. The demonstrated performance confirms that the latest CMOS tech-nology node is capable to cover the whole UWB frequency range with a single receiver chain.

At even higher frequencies, the 60GHz band offers a wide unlicensed spectrum allowing extremely high-data-rate multi-Gb/s commu-nication systems. This is demonstrated in Paper 6.8 (Georgia Tech) with a 90nm CMOS receiver and transmitter chipset enabling a datathroughput exceeding 7Gb/s.

When the sensor network uses the human body as transmission channel, even UWB is not sufficiently energy efficient. A very power-efficient transceiver for body area networks (BAN) is presented in Paper 6.9 (KAIST). The 0.18μm CMOS transceiver consumes only0.37nJ/b and attains a data rate up to 10Mb/s.


Session 7 Overview / Technology Directions [AP26]

TD: Electronics for Life SciencesChair: Chris Van Hoof, IMEC, Leuven, BelgiumAssociate Chair: Satoshi Shigematsu, NTT, Atsugi, Japan

Emerging nanoelectronics is having impact well beyond current ICT applications. Silicon circuits are starting to enable new medical andhealthcare applications. This non-scaling driven nanoelectronics domain is called “More than Moore technology” and is characterizedby a very high degree of multidisciplinarity. It combines nanoelectronics, biotechnology, information technology and cognitive sci-ences, and therefore literally has been called a big BANG combination of Bits, Atoms, Neurons and Genes.

In these lifescience applications, silicon is meeting carbon (the human body) on a level not witnessed before. Gradually, a more intri-cate interaction between humans and silicon circuits is emerging, by restoring functionalities such as hearing or vision. With increasedpenetration of these wearable and implantable circuits and systems, healthcare will be able to shift from its present reactive approachto a proactive and more integrated and individualized approach.

The eight papers in this session will present dramatic improvements in wearable and implantable circuit and device technology for healthmonitoring applications and one paper even opens a new paradigm that could be called “social electronics”.

Three papers address wearable monitoring applications. A wireless sensor network consisting of 30cm3 nodes with 3-year battery life,that has been realized and used to study human activity and interaction between people, is presented in Paper 7.1 (Hitachi). The longbattery life has been achieved by dramatic data reduction from 100kb to 32b. Apart from regular monitoring applications, analysis ofthe thermal data is used to study social dynamics and team activity. A 16mm2 complete wireless sensor node SoC in 0.13μm CMOSfor disposable smart bandaids is used for vital-sign monitoring in body area network applications in Paper 7.2 (Toumaz Technologyand Future Waves). A healthcare monitoring chip controller in 0.25μm CMOS has been integrated into textiles using a “fashionable”circuit board technology in Paper 7.8 (KAIST).

Three papers in the session present enabling circuits and systems for implantable applications. The first imager (1.1x1.5mm2) ever im-planted into a human eye for partially restoring vision to a blind patient was realized in 0.25μm CMOS. This same paper presents a 90%fill-factor miniature endoscope imager using thin-film-on-CMOS is able to detect 0.1 lux in Paper 7.4 (IMS Chips). A second-genera-tion subretinal stimulation chip in 0.35μm CMOS achieves 4V stimulation peak-to-peak and is DC-free in Paper 7.5 (U Ulm, NMI andRetina Implant). A single-chip complete wireless neural recording system to be used for neural prostheses, and realized in 0.35μmCMOS, consumes only 6mW in Paper 7.6 (UC Santa Cruz, U Newcastle; National Chiao-Tung U).

Paper 7.7 (Columbia U) achieves the highest density stimulation array (256x256 stimulation sites on 4x4mm2) for stimulation of acutebrain slices. The circuit is realized in 0.25μm CMOS. The effect of the stimulation is detected by Calcium-ion fluorescence indicators.

The smallest Nuclear Magnetic Resonance (NMR) system (2500cm3) used for detection of biomolecules is presented in Paper 7.3(Harvard U; Mass General). The RF transceiver is realized in 0.18μm CMOS.



Medical & DisplaysChair: Reid Harrison, University of Utah, Salt Lake City, UTAssociate Chair: Oh-Kyong Kwon, Hanyang University, Seoul, Korea

Advances in circuit and sensor miniaturization have led to a wide variety of small medical diagnostic sensors for applications rangingfrom EEG detection in the brain to DNA detection on a chip. Circuits designed for these applications must address the issues of powerdissipation, sensitivity and specificity. This session begins with recent advances in brain sensing, with particular emphasis on systemstargeting chronic measurement and efficient diagnosis of disease.

Paper 8.1 (Medtronic; MIT) presents a low-power architecture for analyzing microvolt-level neuronal signals and extracting key bio-markers. The circuit is designed to be ‘tuned’ for tracking a variety of disease states. Paper 8.2 (IMEC; KU Leuven) discusses a fully-integrated ambulatory monitor for EEG. The sub-microvolt sensitivity and microwatt operation set a new standard for noise performancein bioinstrumentation.

The detection of tiny amounts of chemical compounds is a key issue in biological sciences and medicine, and new approaches pro-viding better sensitivity and reduced cost are needed. Paper 8.3 (U Edinburgh; U Strathclyde; Eade Polytechnique Federale) describesa system for time-resolved fluorescence analysis based on a 16×4 single-photon avalanche diode array with time resolution of 400ps.Paper 8.4 (ETH Zurich; Georgia Institute of Technology) presents a 576-location DNA detection array based on cyclic voltammetry. Itexploits the electrode-electrolyte interface as part of the ΔΣ converter, achieving linearity and SNR of 11b. Its characteristics are demon-strated on several short DNA sequences.

Medical sensors can be applied in more general consumer applications. Paper 8.5 (NTT) presents a fingerprint scanner that verifiesthat the tissue impedance falls in an expected range to prevent fraud.

The flat panel industry continues to grow and extend application products. In display technology, advances in digital-to-analog con-verters and driving circuits for mobile and AMOLED displays must achieve higher image quality with reduced cost and power.

Paper 8.6 (Analog Devices; UC Berkeley) describes a 10b CMOS scanning display driver with 75ns settling time and better than 3mVaccuracy for 3-inch QVGA LTPS LCDs. Paper 8.7 (KAIST) proposes a direct current driving circuit with a fast feedback method formedium- and large-sized AMOLED displays. A small, low-power cyclic capacitor-DAC architecture is proposed in Paper 8.8 (Samsung)for mobile TFT-LCD driver integrated circuits.


Session 9 Overview / RF [AP34]

mm-Wave and Phased Arrays

Chair: Ali Hajimiri, California Institute of Technology, Pasadena, CAAssociate Chair: Kari Halonen, Helsinki University of Technology, Espoo, Finland

Silicon IC implementations of systems operating at millimeter-wave frequencies (such as 24GHz, 60GHz, 77GHz, and 94GHz) have ap-peared over the last several years. They provide numerous opportunities and challenges for gigabit wireless communications, radar,remote sensing, imaging, and secure communication links using mm-waves.

On the communications side, the ever-increasing demand for bandwidth has made mm-waves a serious contender for gigabit wirelesscommunications. Such systems can be used in a variety of applications, such as short-range distribution of broadband high-qualityvideo and audio applications, as well as high-speed home and enterprise networking. The smaller wavelengths which characterize mm-waves make it possible to use a fusion of electromagnetic and antenna techniques along with the practically unlimited number of reli-able transistors in a silicon IC, to crease new methods for modulation and encoding of the data that allow for secure communicationsand concurrent transmission of various independent data streams in different spatial directions. It is also possible to use the siliconCMOS technology in very-large-scale phased arrays as a low-cost integrated solution to create scalable tunable multi-band multi-beamphased arrays for a variety of applications.

This session explores the most recent developments in mm-wave applications of silicon, and offers a broad set of solutions for com-munications, radar, imaging, concurrency, and security needs in this quickly emerging and exciting area of integrated-circuit design.

The session starts with Paper 9.1 (U Toronto; STMicroelectronics), which describes a mm-wave receiver in 65nm CMOS operating be-tween 76- and 95GHz consuming 206mW and operational up to 100ºC with a conversion gain of 12.5dB and a NF of 7dB.

Paper 9.2 (UC Berkeley) demonstrates a low-power mm-wave receiver in 90nm CMOS with a NF of 6.2dB that dissipates 24mW froma 1V supply. It shows an RF-to-IF conversion gain of 18dB and an overall tunable gain from 0dB to 55dB with a robust design strategyresulting in a close agreement between simulations and measurements.

A 52GHz two-element phased-array receiver front-end in 90nm CMOS is demonstrated next in Paper 9.3 (IMEC; Vrije Brussel). It usesa QVCO to generate the necessary in-phase and quadrature LO signals for beam-forming and steering. Each path has a gain of 30dBand a NF of 7.1dB. The receiver has a total power consumption of 65mW and occupies a small area of 0.1mm2.

The concept of phased arrays is taken to a very large scale array in Paper 9.4 (Caltech) where a concurrent dual-band quad-beam re-ceiver element tunable between 6 and 18GHz is implemented in a standard 0.13μm CMOS process. It can form four beams at two dif-ferent frequencies between 6 and 18GHz and can be used as the basic building block of a million-element phased array.

Paper 9.5 (Caltech) shows a novel modulation technique based on changing the effective length and shape of on-chip antenna reflec-tors. This new approach makes it possible to generate arbitrary signal constellations using a constant envelope PA. Furthermore, it en-ables transmission of multiple data streams simultaneously in different directions using a single transmitter or to create a securecommunication link.

Paper 9.6 (UCLA) demonstrates a technique to reuse the same LO frequency twice to down-convert from 60GHz to baseband using adouble quadrature down-converter with a 30GHz LO. The receiver fabricated in 90nm CMOS has an in-band gain of 18dB to 22dB anda NF between 5.7dB and 8.8dB on 36mW of power.

Three high-frequency amplifiers are presented next: Paper 9.7 (Ruhr U) demonstrates a 60GHz LNA in 65nm CMOS process with a NFof 6.1dB with a 3dB bandwidth of 7.7GHz using a balun and a transformer consuming 35mW. An ESD-protected LNA operating at18GHz is shown in Paper 9.8 (Infineon; U Paderborn) with a NF of 4dB and a gain of 20dB in 0.13μm CMOS. Finally, Paper 9.9 (UCBerkeley) demonstrates a 90nm CMOS distributed amplifier with a gain-bandwidth product as high as 660GHz for ultra-fast links op-erating at 100Gb/s.



Cellular TransceiversChair: Tony Montalvo, Analog Devices, Raleigh, NCAssociate Chair: Aarno Pärssinen, Nokia, Helsinki, Finland

Continued growth of the more than 1-billion unit-per-year cellular phone industry is driven in part by the continued cost reduction andminiaturization of the underlying technology. The remarkable evolution of cellular phone technology over the last two decades beganwith migration from III-V technology to bipolar/BiCMOS silicon processes and continued with the development of direct-conversionand low-IF architectures that eliminate passive components not amenable to integration. In Recent years architectures enabling im-plementations in pure digital CMOS processes have emerged. Once the radio is implemented in digital CMOS and non-integratable com-ponents are eliminated, the evident next step is to integrate the radio with the digital baseband. The papers in this session providebenchmarking results of the latest developments in this area. In particular, ICs addressing standards at two phases of the integrationlife cycle are presented. In the 3G/WCDMA world, eliminating SAW filters is the current challenge. GSM suppliers have reached the nextphase and, in addition to integrating the digital baseband, include the applications processor.

Paper 10.1 (MediaTek) presents an all-digital PLL that is made amenable to integration in digital CMOS by eliminating analog compo-nents such as the charge pump and the loop filter.

Papers 10.2, 10.3 and 10.7 are examples of techniques that eliminate external components in WCDMA handsets. WCDMA is a full du-plex standard – that is, WCDMA phones transmit and receive simultaneously. A duplex filter cannot completely eliminate the transmitsignal from the receiver’s input. Two problems result. First, the receiver can be desensitized as a result of transmitter noise that fallsin the receive band. Second, the large TX-frequency component combined with other interfering signals can create intermodulation prod-ucts that corrupt the possibly small desired signal. Traditionally, this problem has been addressed by including SAW filters in both thetransmit and receive paths. The transmit-path filter is intended to attenuate the receive-band noise. The receive-path filter, usuallyplaced between the LNA and the mixer, is intended to attenuate the transmit signal to reduce the linearity requirement of the mixer.

Paper 10.2 (Analog Devices; Federico Beffa Engineering) presents a transceiver that eliminates both receive and transmit filters. Fo-cusing on the receive path, the typically required inter-stage SAW filter is eliminated by notching out the transmit signal and by im-plementing a highly linear mixer. Paper 10.3 (Caltech) addresses the same problem but instead of filtering and linearizing opts to cancelthe distortion. Paper 10.7 (Broadcom) presents a technique that eliminates the transmit path SAW filter using a feedback technique inwhich the transmitter’s noise is cancelled over a narrow bandwidth.

Papers 10.4, 10.5 and 10.6 are benchmarks of GSM/EDGE integration that take three different approaches. The first, Paper 10.4 (Broad-com) is a GSM/EDGE transceiver that implements the dig-RF interface which integrates all analog and mixed-signal components of theradio on the RF die and therefore allows a digital-only die to be used for the modem and applications processor. Paper 10.5 (Texas In-struments) is an example of a single-chip GSM radio in 90nm digital CMOS that also includes the applications processor. The only miss-ing components are power management and flash memory. Paper 10.6 (Infineon) uses 0.13μm CMOS technology and, in addition tothe functionality in Paper 10.5, includes a power management die in the same package.

Paper 10.8 (Toshiba), while not directly targeting the cellular market, describes technology that could enable new features in cellularphones of the future. In this paper, a transceiver that can be tuned between 200MHz and 6.3GHz is presented. A wide RF tuning rangein increasingly important as frequency bands are re-allocated and markets demand swift deployment.

The session closes with something completely different! Paper 10.9 (U Modena & Reggio Emilia; U Pavia; STMicroelectronics) describesa 24GHz receiver front end in 65nm CMOS. Applications for this receiver include broadband communications and radar.



Optical CommunicationChair: Larry DeVito, Analog Devices, Wilmington, MAAssociate Chair: Miki Moyal, Intel, Haifa, Israel

Communication using light signals over optical fiber holds great promise. Speed increase over legacy long distance puts enormous de-sign challenges of equalization both in transmitter and receiver designs. Several advances in the practical art of sending and receivingoptical signals are presented. Inevitably, such advances will lead to exciting data-transfer speeds of 10Gb/s and beyond.

Paper 11.1 (Ghent U; FWO Vlaanderen; IWT Vlaanderen; Centre for Integrated Photonics) describes a high-speed 9.8Gb/s burst-modeTIA that is implemented in a 0.25μm BiCMOS/2.7V process. It uses a simple fast gain-locking mechanism to select the desired gainfrom a choice of two values within 4.5ns. At a BER of 10-10, the receiver has a sensitivity of -14.0dBm.

The authors of Paper 11.2 (National Chaio Tung U) present a laser driver with 60mA modulation current and active back-terminationimplemented by a diode-connected NMOS transistor. Compared to the previous publications, this circuit topology provides greater de-sign flexibilities. The return loss for a 25Ω system is better than 8dB for the DC-to-8GHz frequency range. The IC consumes 240mWfrom a 1.8V supply.

Next two papers introduce burst-mode 10Gb/s clock- and data-recovery (CDR) circuits. The authors of Paper 11.3 (National Taiwan U)present a 20/10/5/2.5Gb/s multi-band burst-mode CDR circuit realized in 90nm CMOS technology, which can scale power with datarate. A 10.3125Gb/s burst-mode CDR circuit is designed for 10G-EPON systems in Paper 11.4 (NTT). A single-gated VCO and ΔΣmodulator reduces VCO center-frequency error to less than 2MHz and eliminates external devices. Consecutive-identical-digit toleranceof 160 bits, and jitter tolerance of over 0.27UIpp.

In Paper 11.5 (NEC) a 40Gb/s CDR circuit is presented that uses an eye-opening monitor to enable adaptive control of the data deci-sion point. The adaptive feedback acquired through 2D eye-monitoring improves BER performance down to 10-12 as compared to 2×10-

7 with no adaptive control.

Paper 11.6 (Arizona State U; Arete Associates) shows an array of optical transceivers with aggregate throughput of 96Gb/s for high-density short-distance bus links. The chip is implemented in a 0.35μm SiGe BiCMOS process. The circuits are both area- and power-efficient; both 75μm inter-channel pitch and 21.3mW/Gb/s, achieved by this design, are the lowest reported to date for a 64-channeltransceiver. Crosstalk from electrical and substrate effects is below -40dB.

Finally, the last 2 papers show recent advances in DSP-based optical receivers. Paper 11.7 (ClariPhy) addresses, for the first time, 10GBASE-T Ethernet over multi-mode fiber (MMF) links using electronic dispersion compensation; a 6-bit 10GS/s ADC is used at the ana-log-front-end that feeds a parallel-processing DSP receiver. Then, the authors of Paper 11.8 (Finisar; UI Urbana) introduce a 10Gb/sMLSE receiver with fast power-transient management for optical add/drop multiplexer-based WDM networks in single-mode fiber. Thereceiver has a VGA with a fast automatic gain control and a high-bandwidth offset-cancellation loop. The receiver IC tolerates a10dB/10μs optical power transient with 72 consecutive identical digits with no BER impact, and offers a 100-fold improvement over astandard CDR circuit in tracking an 8dB sinusoidal power transient at a BER of 10-4.


Session 12 Overview / Data Converters [AP40]

High-Efficiency Data Converters

Chair: Gabriele Manganaro, National Semiconductor, Salem, NHAssociate Chair: Tatsuji Matsuura, Renesas Technology, Gunma, Japan

The design of energy-efficient data converters has established itself as a clear technology trend for many years. Although, the relent-less drop in supply voltages has been beneficial to power savings in digital circuits while it has brought many challenges to analog de-signers. Nonetheless, skilled designers have successfully introduced new architectures and techniques for power-efficientanalog-to-digital conversion in deep submicron technologies. Such converters enable new applications especially in the sensors, mo-bile communication and computing areas.

Successive approximation and pipelined ADCs have been among the most popular architectures of choice for moderate-resolution ap-plications. The increased availability of complex on-chip digital processing has spurred the development of sophisticated digital cali-bration techniques. This, in turn, has also allowed the practical implementation of time-interleaving as an effective way to lower powerconsumption at the expenses of area and complexity.

However, easy access to inexpensive digital processing capabilities is not the only answer to all problems. Pure analog innovation con-tinues to offer very effective and exciting solutions. For instance, many valid energy-saving alternatives are presented for classic build-ing blocks, such as resistor ladders in reference circuits or operational amplifiers in switched-capacitor circuits, that draw static current.

The first five papers in this session describe moderate-to-low resolution/speed analog-to-digital converters by applying the principleof successive approximation in various forms to dramatically reduce power consumption.

Paper 12.1 (IMEC; U Salento) presents a 9b 40MS/s charge-sharing SAR ADC using a high-noise/low-power comparator during mostof the conversion process, subsequently lowering its noise (at increased power consumption) and correcting for possible errors on afinal extra step. This ADC consumes less than 1mW at 1V supply on a 90nm CMOS process. A highly time-interleaved SAR array ispresented in Paper 12.2 (TI; MIT) to realize a 5b 250MS/s ADC in 65nm at 0.8V supply. Redundant SAR sub-ADCs are selected to re-place the worst channels and counter yield loss due to large mismatches in the array. Offset mismatches are digitally corrected whilea hierarchical top-plate sampling technique minimizes sampling time-skew errors. Paper 12.3 (IMEC; VUB) describes a 90nm 1V 7b150MS/s two-step ADC that after a 1b coarse step, determines the remaining 6b through an asynchronous binary-search comparatorarray activating only 1 comparator per resolved bit. The implementation is made even more power efficient by the systematic avoid-ance of any block drawing static current. Static power consumption is also carefully avoided in Paper 12.4 (U Twente; Philips). Thisdescribes a 10b 1MS/s charge-redistribution SAR ADC where further energy saving is also achieved as the voltage on the capacitorsis increased in steps, rather than all at once. This design is also using a dynamic comparator and a delay line to generate all clocks whileconsuming less than 2μW from a 1V supply in 65nm. A new kind of SAR ADC is introduced in Paper 12.5 (U Pavia). Here, both theinput and the reference voltages are transformed into properly long pulses and their duration is compared with minimum power con-sumption. This 10b 1kS/s ADC consumes less than 4μW at 1V in a 0.18μm CMOS process.

Sampling rate and resolution is higher in the next 3 papers in the session. Two pipelined ADCs and a folding flash ADC demonstratehow energy efficiency can be achieved at higher sample rates.

The 14b 100MS/s pipelined ADC reported in Paper 12.6 (U Texas; National Semiconductor) achieves dramatic power saving by merg-ing the sample-and-hold with the first pipeline stage. Neither the sampling speed nor the accuracy are sacrificed thanks to a carefulsequence of switch-capacitor processing phases. This 0.18μm CMOS ADC achieves about 72dB SNR and 88dB SFDR at Nyquist fre-quency while consuming 230mW from a 3V supply. Another very power-efficient high-speed pipeline ADC is presented in Paper 12.7(STMicroelectronics). A 10b 100MS/s ADC consumes 4.5mW from a 1.2V supply on a 65nm CMOS process. Finally, a new 5b 1.72GS/sfolding flash ADC is described in Paper 12.8 (IMEC; VUB). It consumes 2.2mW from a 1V supply by avoiding amplifiers and static cur-rent consumption in a 90nm CMOS process.


Session 13 Overview / Low-Power Digital [AP42]

Mobile ProcessingChair: Alice Wang, Texas Instruments, Dallas, TexasAssociate Chair: Kazotami Arimoto, Renesas Technology, Hyogo, Japan

This year’s Mobile Processing session proves that Moore’s Law is alive and kicking with submissions showing the highest level of in-tegration in the most advanced process technologies and using low-power techniques. Deep sub-micron technologies allow the proces-sor’s clock frequencies to soar and new functions to be added. Doubling transistor counts on a die allows integration of both multipleheterogeneous and homogeneous processors onto one System-on-Chip (SoC). Multi-core solutions moving into the mobile space be-comes a viable way to demonstrate the next generation communication standards and multimedia applications. In turn, these newfunctions open up the consumer electronic space for advanced mobile internet and cellular devices. However, because mobiles are bat-tery operated, smaller transistors, new and faster functions, and multi-core architectures conflict with the requirement to lower powerconsumption for long battery lifetimes. Thus innovative low-power techniques, both circuit and architectural, increasingly are neces-sary to allow Moore’s law to continue. The six papers introduced in this session highlight the most advanced low-power and high-per-formance circuit techniques introduced for mobile processing.

Novel architectures take advantage of SoC integration in the most advanced CMOS process technologies and introduce new low-powercircuits. An Intel Architecture processor in 45nm CMOS technology with sub 2W power dissipation is presented in Paper 13.1 (Intel).This microprocessor is designed with a new micro-architecture and power-efficient algorithms to make it suitable for mobile internetdevices and ultra-mobile PCs. Two papers report the progress on application and baseband processors combined to a single-chip so-lution. Paper 13.2 (Texas Instruments) shows the world’s first 3.5G baseband and multimedia application processor in 45nm CMOStechnology. The SoC uses a full suite of low-power and high-performance circuit techniques including adaptive body-biasing. In Paper13.3, (Renesas; NTT DoCoMo; Fujitsu; Mitsubishi; Sharp; Sony; Ericsson) a 65nm CMOS technology is used for the implementationof a single chip application and dual-mode baseband processor. It features 3 CPU cores, 21 separate power domains, and achieves lowpower through partial clock activation.

Communication/multimedia power-optimized co-processors demonstrate the lowest reported power due to innovations in architectureand low-power circuits. A multimedia processor featuring power-efficient H.264 decoding is presented in Paper 13.4 (Toshiba). Throughoptimization at different levels of abstraction, low power for an HSDPA turbo decoder is achieved in Paper 13.5 (ETH Zurich; ACP).

Finally, combining both programmable cores and configurable accelerators to combat the rapid proliferation and evolution of wirelessstandards indicates that the Software Defined Radio is close to becoming a commercial reality. A fully programmable Software DefinedRadio (SDR) for next generation wireless standards such as WiMAX and DVB-T/H in 0.12μm CMOS technology in Paper 13.6 (LinköpingU).


Session 14 Overview / Memory [AP44]

Embedded and Graphics DRAMsChair: Katsuyuki Sato, TSMC, Hsinchu, TaiwanAssociate Chair: Joo Sun Choi, Samsung Electronics, Hwasung, Korea

Historically, the DRAM industry focuses on increasing density for commodity devices with advances measured by the constant rise inthe number of bits per chip. This trend is reaching a roadblock and research and development interest is shifting towards improvingperformance for multimedia applications. This change is also driven by the rising importance of embedded and high-speed graphicsapplications. In these applications, bandwidth is king both within and between dice. In response, on-die embedded macros are push-ing performance, bu this in itself is not adequate. The power and cost budgets pose constant challenges for the eDRAM designer whentrying to satisfy consumer demands. Addressing these requirements; embedded DRAM-macros are at the center-stage of the first halfof today’s session. The presentations showcase interesting new developments that promise to open up new applications for eDRAMs.

Last year, the 500MHz random-cycle hurdle was surpassed in a high-performance SOI process. This year, higher benchmarks areachieved in a conventional bulk process in Paper 14.1 (TSMC). Reaching performance targets in bulk on lower cost foundry processespromises the ability to use these macros for a broader range of consumer products.

Paper 14.2 (United Memories; Sony) addresses the burning problem of power dissipation in high-bandwidth macros. Since the highbandwidth of the macro is achieved by pre-fetching more data from the eDRAM core, the number of internal data lines is growing. Thepower problem in this macro is alleviated by limited-swing signalling and charge recycling.

Improved performance is also required for on-die processor caches. Here, the area advantage of the eDRAM cell promises to betteroverall performance if the performance of the eDRAM cell improves to compete with the conventional eSRAM. Continuing the trendfrom last year, further advances are reported in Paper 14.3 (Intel). Again, the move from SOI to bulk was successful in keeping ran-dom access cycle, while increasing clock frequency to 2GHz.

The last paper in this group, Paper 14.4 (Toshiba) presents a memory macro for embedded graphics applications. A special pseudo-two-port operation and specifically adapted redundancy optimize the macro for multimedia while keeping the area requirement low.

The second part of the Session features advances in stand-alone graphics DRAMs. It starts with a first insight in Paper 14.5 (Samsung)into the new GDDR5-standard for stand-alone graphics DRAMs. GDDR5 follows in the footsteps of GDDR4, which was presented inlast year’s conference, but deviates from many established DDR-approaches, needs many new solutions for the years to come.

At present, GDDR3 is the universal standard for graphics subsystems. Due to wide market penetration, improving these devices re-main of high importance. Papers 14.6 and 14.7 describe recent advances in this direction enabling safe 3Gb/s pin operation. Paper 14.6(Hynix) emphasizes optimization of the output driver circuitry through a programmable slew-rate and a flexible programming of thedrive strength. A simple adaptation to different environments is possible, enabling reliable usage for the consumer. Paper 14.7 (Hynix)presents an improved duty-cycle-correction method, clock receiver and power-reduction to generate a stable on-chip clock.



TD: Trends in Power and Signal TransmissionChair: Bill Bidermann, BK Associates, San Diego, CAAssociate Chair: Ken Shepard, Columbia University, New York, NY

This session examines emerging trends in RFID tags, contactless data transmission through capacitive, inductive, and optical coupling,high-voltage electronics, and energy harvesting. Collectively, these applications push new circuit techniques in power and signal trans-mission including power electronics and low-power transceivers.

RFID tags for remote sensing continue to push requirements on data bandwidth, cost, adaptability to multiple data transmission fre-quencies and standards, and low-power consumption to enable remote-powered operation. Paper 15.1 (CEA-LETI) presents a re-mote-powered pressure sensor tag with a bandwidth of over 100Hz operating at a 2.45GHz carrier while keeping power consumptionto less than 30μW. Paper 15.2 (Graz; Infineon) describes an RFID with triple-band adaptability, supporting signal carriers from 1MHzto 2.45GHz including the EPC UHF and HF RFID standards. Cost continues to be an important factor in RFID design. Paper 15.3(IMEC; KU Leuven; Polymer Vision; TNO Science and Industry) examines the potential of RFID fabricated with organic semiconduc-tors on foil.

Contactless data transmission through capacitive and inductive coupling remains an important trend for chip stacking applications aswell as contactless test and measurement. Paper 15.4 (U Tokyo; Keio U0 describes objects powered and communicating point-to-pointthrough a large-area contactless sheet capacitively coupling to the transceivers. 100kb/s data transmission is demonstrated at 107pJ/b.Paper 15.5 (IBM) describes a 2-D array of VCSELs and photodiodes integrated into the sample CMOS chip and operating at channelrates of 10Gb/s. Paper 15.7 (Keio; Tokyo U) presents an 11Gb/s inductive coupling link that supports communications distances ofmore than 30μm.

Paper 15.6 (AMI Semiconductor) presents technology trends in high-voltage circuits supporting power transmission and switching upto 100V and 10A and defines safe operating areas for these circuits.

At the other end of the power spectrum, generating sufficient DC voltages to drive ultra-low-power integrated circuits from energy-harvesting sources remains an important topic of research. Paper 15.8 (IMEC; KU Leuven; R.M.A.) describes the design of a high-ef-ficiency DC-DC converter to harvest energy from the body with thermocouples. Paper 15.9 (UC Davis) describes the circuitry forenergy scavenging from piezoelectric generators, in particular, a rectifier with greater than 98% efficiency.


Session 16 Overview / Low-Power Digital [AP48]

Low-Power DigitalChair: Rajeevan Amirtharajah, University of California, Davis, CAAssociate Chair: Holger Orup, Texas Instruments, Copenhagen, Denmark

Power consumption continues to be a critical challenge in implementing digital integrated circuits, especially as technologies scale to65nm and beyond. This session includes a diverse set of papers, from industry and academia, which embody current trends in imageunderstanding, coding for communications, video processing, and ultra-low voltage circuit design. Image understanding adds higher-level functions, such as object recognition, to traditional image processing that can enable new applications such as intelligent vehi-cle control and smart video surveillance. Researchers are looking to the human brain to inspire new vision processing architectures.Low-power implementations of error-correcting codecs and video encoders will allow high-definition television to be incorporated intofuture portable devices. This session demonstrates that techniques such as clock and power gating, low voltage circuits, and method-ologies for coping with variability in deep submicron processes are necessary across these varied application domains to address thepower challenge.

Papers 16.1 and 16.2 represent a new trend toward image understanding architectures, which complement traditional image pro-cessing with functions such as object recognition. Paper 16.1 (National Taiwan U; UMC) presents an SoC solution that integrates asmall image sensor, A/D conversion, and an image processing pipeline to achieve 76.8 GOPS at 374mW. A special processor enablessingle-cycle feature extraction to improve average throughput.

Paper 16.2 (KAIST) presents a 125 GOPS 583mW parallel processor connected through a network-on-chip. A hardware acceleratorinspired by the visual attention engine of the human brain reduces the image data size by pre-selecting objects for subsequent pro-cessing.

Satellite transmitted HDTV decoding is the subject of Paper 16.3 (STMicroelectronics). The paper features a 64800b LDPC codec thatrealizes error-free reception at 135Mb/s while dissipating 120mW. Signal routability is enhanced by modifying the power and grounddistribution in the large memory blocks, resulting in decreased interconnect power for this wire-dominated design.

Image processing for 1080p HDTV is the focus of Papers 16.4 and 16.5. Paper 16.4 (Sony) presents a 512 GOPS architecture thatprocesses a 60fps HD video stream on 256 processing elements. Integrated multiport memories, power gating, and adaptive body bi-asing minimize power consumption for this fully programmable image processor. Paper 16.5 (National Chiao-Tung U) describes a242mW H.264 encoder that exploits heuristic algorithms for motion vector search that reduce hardware complexity while achievingonly 0.1dB PSNR loss in image quality.

The final two papers reflect a trend toward exploiting subthreshold circuit operation in deep submicron processes. Paper 16.6 (Intel)presents circuit techniques demonstrated in an accelerator for video motion estimation that enables scalable performance over two or-ders of magnitude, from 4.3MHz to 2.4GHz, with supply voltages ranging from 230mV to 1.4V. A novel level shifter circuit lowers thepower penalty for signals crossing voltage domains by reducing contention currents.

Paper 16.7 (MIT; TI) demonstrates the next step in integration for subthreshold designs by combining a microcontroller, SRAM, anda switched-capacitor DC/DC converter on a single die. A custom timing closure method is developed to address the large delay vari-ability in the subthreshold region, enabling operation down to 0.3V. The chip’s idle power consumption, which is critical for many em-bedded applications, is reduced to 1μW at minimum Vdd using power and clock gating.



Wideband ReceiversChair: Jan Craninckx, IMEC, Leuven, BelgiumAssociate Chair: David Ngo, RFMD, Chandler, AZ

Wireless communication is evolving towards multi-standard terminals, handling several standards and modes, such as broadcasting,cellular, WLAN, WPAN, etc. These applications are spread over a wide range of carrier frequencies, and require wideband, reconfig-urable RF front-ends. A major enabler in this large technological challenge will be the availability of broadband receivers coveringthese frequencies, with sufficient noise and linearity, which is the focus of this session. Low-cost implementation in CMOS is a must,of course, as well as emphasis on low area.

This session begins with Paper 17.1 (U Twente), describing a discrete-time mixer architecture that uses 8× oversampling and harmonicrejection. It operates over the broad frequency range from 200 to 900MHz and is implemented in 65nm CMOS. The IC includes clockgeneration, a high-speed sampler, I/Q mixers and, an IIR filter.

Paper 17.2 (IMEC; VUB) deals with the wide-frequency-generation requirement for wideband receivers. A single inductor is used in adual-band VCO that oscillates at center frequencies of 3.5 and 10GHz. By proper frequency division all important RF bands are cov-ered. The IC also includes a DC-to-5.6GHz LNA and a wideband mixer to create a full receiver front-end, achieving a minimum NF of4.5dB while consuming less than 60mW.

Noise and distortion cancelling is applied in Paper 17.3 (U Twente; NXP). The paper describes a receiver front-end that stacks a balun,an inductor-less LNA, and an I/Q mixer in one block. The design is implemented in 65nm CMOS and achieves less than 5.5dB NF and-3dBm IIP3 over the frequency range of 500MHz to 7GHz.



TD: MOS MedleyChair: Glenn Gulak, University of Toronto, Toronto, CanadaAssociate Chair: Werner Weber, Infineon Technologies, Munich, Germany

The first paper in this session, Paper 18.1 (Seiko NPC) reports on a low-cost 64/256 thermopile infrared sensor chip that operates underatmospheric pressure conditions. The responsivity is 146 to 195V/W. The 64-element chip, fabricated in a Molybdenum-gate CMOSprocess with MEMS process is assembled in a compact TO-5 package with a Si-lens. Various applications in the home environment,such as refrigerators, air conditioners, microwave ovens and home security systems, can use this sensor advantageously.

The second, Paper 18.2 (CEA-Leti; STMicroelectronics; IEMN; E&FL) presents a nano-displacement sensor based on an in-plane sus-pended-Gate MOSFET (SGMOSFET) that is compatible with a front-end CMOS process and that shows 130zF/√Hz capacitance noise.The authors have integrated the first SGMOSFET as an initial step toward full integration with additional CMOS circuitry for measure-ment of NEMS displacement. Using a sophisticated test setup, the measured performance indicates that co-integration of electronicswith the NEMS offers significant improvement in measurement resolution, silicon area and power consumption. Furthermore, this ap-proach is of commercial interest because full integration on a single chip will lead to much lower system cost.

In Paper 18.3 (Institute for Microelectronics), a new technology for making thin bendable chips is described. This technique is an al-ternative to polymer electronics, which is often manufactured on flexible substrates. Here, 200nm cavities are formed beneath the sur-face. After CMOS device and interconnect integration, trenches along the sides of the chips down into the cavities are formed with smallanchors left in the corners. The thin chips are then broken off the wafer and assembled. The buried cavities are made by porous Sili-con formation and epitaxial overgrowth.

The last paper in this session, Paper 18.4 (U Toronto) reports on an integrated CMOS sensor for the rapid identification of bacteria inmedical diagnosis and food-safety inspection. The specificity of phages is utilized to develop a fast (< 10 minute) method to trigger anion cascade that is picked up by on-chip electrodes and amplified by an integrated low-noise amplifier. This is a promising low-costtechnique for realizing a portable low-power, disposable device for pathogen detection.



PLLs and OscillatorsChair: Adrian Maxim, Silicon Laboratories, Austin, TexasAssociate Chair: Changsik Yoo, Hanyang University, Seoul, Korea

Because of the aggressive scaling of CMOS processes, large numbers of digital gates are available at low additional cost to performadvanced calibration and tuning of analog circuits. Today’s trend toward digitally-enhanced analog circuits is fundamentally changingthe paradigms for PLL and oscillator design. Replacing the analog-intensive PLL building blocks, the VCO, charge-pump and loop fil-ter, with a DCO, time-to-digital converter (TDC) and digital loop filter, respectively, has resulted in all-digital-PLL architectures. Thesearchitectures are well suited for implementation in low-cost digital CMOS processes. Both phase noise and spurious-tones in PLLs canbe significantly reduced by taking advantage of digital signal-processing techniques. Digital compensation of the frequency drift in os-cillators due to process, temperature and bias variations is enabling silicon replacements for crystal oscillators, which are among thelast remaining external PLL components.

This session focuses on novel digital techniques aimed at improving the performance of PLLs and oscillators for the next generationof highly integrated mixed-signal SoC applications. It begins with four papers describing digitally enhanced PLLs, followed by threepapers that describe new oscillator architectures.

Paper 19.1(MIT) presents a 3.6GHz digital fractional-N PLL that employs a quantization-noise digital cancellation loop to allow wideloop bandwidth. The resolution of the digital phase detection is improved by a time-to-digital converter based on a gated ring-oscilla-tor.

Fractional-N PLLs with traditional ΔΣ modulation introduce fractional spurs when their quantization noise is subjected to the non-lin-earities of the PLL’s analog circuitry. These fractional spurs are often suppressed by a judicious choice of the reference frequency anda reduction in the loop bandwidth. Paper 19.2 (UC San Diego, and Next Wave Wireless) presents an alternative spur reduction tech-nique enabling a wider loop bandwidth and greater flexibility in choosing the reference frequency. The combined use of an offset chargepump, a sampled loop filter and a successive re-quantization suppresses the spurious tones by over 20dB.

To meet the challenging requirements on spurious tone suppression in modern wireless and wireline frequency synthesizers, the phasedetecting TDC in an all-digital PLL has to be very linear and provide fine quantization steps. Paper 19.3 (U Pavia; STMicroelectronics)introduces a TDC calibration technique and background mismatch algorithm that brings the in-band spurs below -45dBc.

Wide bandwidth fractional-N PLLs using ring-oscillator VCOs have difficulties filtering the high-frequency quantization noise comingfrom the ΔΣ modulator. Paper 19.4 (Tsinghua U) describes a discrete-time noise suppression technique that avoids the use of analogphase error cancellation.

Relaxation oscillators offer various advantages over ring oscillators, such as constant frequency-tuning gain and continuous readingof phase, but have been infrequently used in applications because of poor phase noise. By balancing the noise contributions fromcharge and discharge mechanisms, the relaxation oscillator described in Paper 19.5 (U Twente) achieves an FoM close to the theoret-ical limit and in-line with state-of-the-art ring oscillators.

Paper 19.6 (Mobius Microsystems and U Utah) presents a self-referenced CMOS oscillator intended as a silicon replacement of bulkyand costly off-chip crystal references. Digital temperature, bias and process compensation techniques make accurate free-running fre-quency trimming of the integrated LC-VCO possible.

High accuracy crystal oscillators use switched-capacitor arrays to compensate for variations. ΔΣmodulation has been used to improvetuning resolution that is limited by the minimum capacitor size. Paper 19.7 (Sirenza Microdevices) presents an alternative way of im-proving tuning resolution by changing two capacitor arrays in a Pierce oscillator in opposite directions, which avoids the switching en-ergy inherent in dithered-capacitor architectures.



WLAN/WPANChair: Arya Behzad, Broadcom, San Diego, CAAssociate Chair: Tadashi Maeda, NEC, Kawasaki, Japan

Over the past several years, wireless devices have evolved from relatively simple, high-cost, low-data-rate, single-function, single-mode, single-band components to highly integrated, low-cost, high-performance, multi-mode ICs. These changes have been driven bythe ever-increasing demand for higher throughput, higher spectral efficiency and more reliable communications which in turn owetheir growth to the consumer’s growing appetite for ubiquitous unfettered access to all their data at all times, and the need for in-creased productivity at work and data-intensive multimedia and gaming applications at home.

State-of-the-art WLAN and WPAN transceivers exemplifying one or more of the above attributes are presented in the papers in this ses-sion. These include a highly integrated 1×2 transceiver for 802.11a/g/n applications, a fully integrated 2×2 MIMO SoC, a digital trans-mitter for WiFi/WiMAX applications, a discrete-time WiFi/WiMAX receiver, a highly integrated BT EDR SoC, a very-low voltage RX forISM applications, a couple of very-low-power 802.15.4 WPAN front-end receivers, and a DDFS-driven mixing-DAC intended for SAW-less TV receiver front-ends.

Paper 20.1 (Intel) describes a highly integrated 1×2 multiband CMOS transceiver with integrated power amplifiers for 802.11a/b/g/n.A linear transmit power of 15.5dBm with a PA efficiency of 19% is achieved in the 2.4GHz band. The 5GHz band PA achieves 14.5dBmat 12% efficiency. The reliability of the all-CMOS PA is also discussed. On the receiver side, the transceiver achieves a sensitivity of -74dBm for 54Mb/s.

The first published 802.11n SoC is presented in Paper 20.2 (Atheros; Stanford U). This SoC integrates a dual-band 2x2 radio, as wellas the PHY and MAC and a PCI Express interface functions on a single 36mm2 in 0.13μm CMOS process. This SoC achieves a peakUDP throughput of 216Mb/s in the 2.4GHz band.

Paper 20.3 (STMicroelectronics) presents a fully digital 65nm CMOS transmitter. This transmitter can serve both WLAN and WiMAXapplications in the 2.4-to-2.7GHz band. The transmitter achieves a 2.1% EVM at a 2dBm transmit power, and offers a 64dB power con-trol range. A companion discrete-time receiver chip is also presented in Paper 20.4 (STMicroelectronics). This architecture utilizes atransconductance LNA along with a resistive attenuator and a single switch-capacitor channel select filter with built-in anti-alias capa-bility running at a high switching frequency.

Paper 20.5 (Atheros) describes a Bluetooth EDR SoC. This SoC, which is implemented in 0.13μm CMOS, occupies a total die area of9.2mm2 with the analog and RF section occupying only 3mm2. This small area is the result of incorporating a two-point polar modu-lator on the TX path, and also using a low-IF RX with a 1st-order LPF and a high dynamic range ΔΣ ADC.

An ultra-low-voltage highly integrated receiver intended for WPAN applications is presented in Paper 20.6 (Columbia U). This receiveris implemented in 90nm CMOS process and occupies 2.9mm2 and is capable of operating with a supply voltage as low as 0.6V. It canbe configured as a low-IF as well as a zero-IF receiver and consumes 32.5mW of power.

Paper 20.7 (STMicroelectronics; U Paul-Sabatier) presents a very-low-power 802.15.4 2.4GHz RX front-end implemented in 90nmCMOS. The receiver uses a 6MHz low-IF architecture with an inductor-less LNA. Including an input balun, the front-end occupies anarea of 0.23mm2 and consumes 5.4mW from a 1.35V supply.

Paper 20.8 (U Pavia) presents another very-low-power front-end for 802.15.4. This front-end is implemented in 90nm CMOS and oc-cupies 0.35mm2. This receiver also utilizes a low-IF architecture and achieves an image rejection of 35dB while consuming 3.6mW froma 1.2V supply.

Paper 20.9 (Silicon Labs) presents a DDFS-driven mixing-DAC with integrated image and harmonic rejection capability. This approacheliminates the need for SAW or LC-tracking filters which traditionally were required for wideband TV receivers. This mixer achieves anative image rejection of greater than 65dB and occupies 1.2mm2 of area in a 0.13μm CMOS process.



SRAM Chair: Hiroyuki Yamauchi, Fukuoka Institute of Technology, Fukuoka, JapanAssociate Chair: Peter Rickert, Texas Instruments, Dallas, TX

Technology scaling enabled by Moore’s Law drives an ever-increasing amount of embedded memory onto today’s microprocessors andembedded processor applications. SRAM scaling is a challenging area requiring design innovation due to critical issues such as tran-sistor mismatch, threshold-voltage variation, PVT variation and leakage reduction, all under low-voltage operation. Designers must ad-dress these issues to keep the scaling alive at 45nm and beyond. At the 45nm process generation, significant changes in processtechnology such as high-κ metal gates are being adopted, which must be incorporated into the innovation.

This session has an excellent cross-section of design innovations that address these challenges at our most advanced CMOS processnodes. These papers address the full spectrum of device operation, from several-GHz-class performance in CPU and ASIC applicationsto operation at low voltage for low-power consumer applications down into the subthreshold region. However, process and voltage scal-ing alone is not sufficient, in parallel with the high performance, designs must incorporate features to deal with the new problemsmentioned above.

Leading the charge is Paper 21.1 (Intel) where, for the first time, 45nm SRAM scaling challenges are addressed in high performancehigh-κ metal-gate technology, achieving 3.5GHz at 1.1V on the Core™ 2. Innovative solutions are introduced such as a forward-body-bias technique to enable low-voltage operation and also to deal with PVT variations. Next, in Paper 21.2 (IBM) presents another 45nmSRAM and addresses the 45nm SOI SRAM challenges with solutions for power reduction as well as leakage suppression for ASIC ap-plications with a 450ps access time. This session continues with a third 45nm paper, Paper 21.3 (MIT), that shows an innovativesense-amplifier circuit that improves access time by 34% at this advanced process technology node with a very high-density bit-cellfor low-power applications.

Consumer applications are also requiring high performance at lower operating voltages. Paper 21.4 (Toshiba) provides insight for thispart of the spectrum using a unique asymmetric SRAM cell with unity beta ratio and a fine bitline segmentation scheme in 45nm bulkCMOS that achieves 1GHz performance at 0.7V. Leakage control is one of the biggest challenges, especially for battery-operated ap-plications, and Paper 21.5 (Hitachi; Renesas) shows a novel scheme to measure systematic threshold-voltage variations in 65nm, andreduces these variations using NMOS and PMOS body-bias techniques, again addressing the PVT-variation problem that SRAMs areexperiencing.

Next this session transitions to a unique 3D SRAM implementation in Paper 21.6 (Samsung). Circuit solutions are introduced for im-proving yield with a new redundancy scheme and SRAM bit-cell biasing techniques to reduce the PVT variation. This circuit solutionimproves the performance, which is targeted at the commodity SRAM product space.

There is hope that someday operating circuits in the subthresold voltage regime will solve power challenges in consumer applications.Paper 21.7 (Purdue U; IBM) shows a 10T SRAM that delves into novel techniques to help both the read stability as well as circuit tech-niques to enable operation down to an extremely low VDD of 0.18V, while ensuring stable operation.

Finally, in Paper 21.8 (National Chung-Cheng U), a binary and ternary CAM is introduced with design solutions to reduce power by 48%and reduce transistor count by 40% in a 0.13μm implementation.


Session 22 Overview / High-Performance Digital [AP64]

Variation Compensation and MeasurementChair: David Money Harris, Harvey Mudd College, Claremont, CAAssociate Chair: Hugh Mair, Texas Instruments, Dallas, TX

Process and environmental variations present increasing challenges for digital circuit designers. At the 65 and 45nm technology nodesand beyond, random dopant fluctuations, changes in transistor channel length, and temperature and supply voltage variation, collec-tively degrade performance and power consumption by more than 30%. This session explores four strategies for dealing with varia-tion: tolerate, measure, reduce and exploit. Variation-tolerant circuits operate correctly despite potentially large changes in parameters.Variation measurement circuits provide parameter readouts, preferably in convenient digital form, giving insight into the nature of vari-ations. These measurements may also be provided to a feedback system that reduces the effect of the variations. Variation-exploitingcircuits take advantage of variations for purposes such as random number generation. The first four papers in this session tolerate vari-ability. The next three measure it. The eighth exploits time-variant trapping to produce random numbers and the ninth reduces powersupply voltage variations.

Designers conventionally leave margins to account for delay variations caused by voltage, temperature, manufacturing, and aging.These margins significantly reduce the performance of circuits. Alternatively, for the same performance, they require a higher nominalsupply voltage and greater power consumption. Worst-case variations occur infrequently, so these margins are often excessive. Pa-pers 22.1 (U Michigan; AMD; ARM) and 22.2 (Intel) describe innovative registers that detect timing errors with modest overhead.These allow the system to reduce the clock period or supply voltage until the circuit is at the edge of failure. Architectural replay mech-anisms flush the pipeline and repeat the operation less aggressively when timing failures occur. The same technique is also used todetect soft errors in the logic or registers.

Paper 22.3 (Harvard U) achieves most of the benefit of a continuously-adjustable supply by interpolating between two fixed supplies.Different supply voltages are selected for different pipeline stages. The pipeline employs a two-phase transparent latch-based clock-ing scheme that uses time borrowing to average the delays across the pipeline stages. The paper applies the technique to a floatingpoint unit and also demonstrates variable-latency operation.

Another trend is the increasing use of one-time programmable electronic fuses to configure chips after manufacturing and to activateredundant blocks to repair defects. This trend is creating demand for efficient arrays containing large numbers of fuses with high re-liability in the face of significant parameter variation. Paper 22.4 (IBM) details the design of a dense 64kb eFUSE array in 45nm SOI.Since the ability to compensate or cancel variation is limited, the designers resort to a strategy of tolerating the expected variations.

Process variation monitor structures are appearing on an increasing number of digital integrated circuits. These monitors facilitate in-circuit testing by producing digital readouts rather than analog voltages. Paper 22.5 (P.A. Semi) describes a way to directly measurecircuit characteristics including race margins, jitter, leakage, and across-die speed variations. Paper 22.6 (U of Michigan) explains howto monitor NBTI and oxide wear-out to control compensation circuits and to warn of impending failure. Paper 22.7 (IBM) shows howto measure the local random variations of transistor ON current.

Temporal variations can also be exploited. Paper 22.8 (Toshiba) presents a compact and temperature-independent random-number gen-erator that takes advantage of time-dependent electron trapping in a silicon nitride MOSFET. The circuit can be used to produce secureencryption keys for smart card applications.

Supply-voltage variation decreases circuit performance and increases clock jitter. Higher current densities and extensive clock gatingincrease the Ldi/dt noise. Brute-force solutions of ever-more supply bumps and passive decoupling capacitors are increasingly ex-pensive. Active decoupling is of growing interest as an inexpensive method of reducing supply noise. Paper 22.9 (U of Michigan)shows how to deliver more charge than any previously published active decoupling circuit using only nominal voltage supplies.



Non-Volatile MemoryChair: Giulio Casagrande, STMicroelectronics, Milan, ItalyAssociate Chair: Shine Chung, TSMC, Hsinchu, Taiwan

These are great and innovative times for the non-volatile industry as it is growing in revenues and in scaling faster than anything thesemiconductor industry has seen before. A great lineup of papers dealing with all aspects of non-volatile memories spans two sessionsthis year. NAND is now the dominant technology for semiconductor storage and is designed into a variety of mobile consumer appli-cations and it is even challenging hard disk drives. In the coming years, laptops will be based on solid-state drives instead of traditionalhard-disk drives. Of course, driving the cost lower is the key to success in both of those endeavors.

To help with this challenge, NAND designers are finding ways to reduce the cost per bit of the memory devices, even though fabrica-tion equipment makers have not kept up with the speed of scaling. In this session, several papers reduce cost by introducing very in-novative solutions. Paper 23.6 (Toshiba; Sandisk) describes a 16Gb device in 43nm technology that represents the traditional methodof lowering the cost by going to the next technology node. This paper reduces the die size a further 9% by the use of wider strings.Paper 23.2 (Saifun; SMIC) discusses techniques for storing 4 bits/cell in a nitride storage using two physically isolated pockets. The4 bit/cell in this 8Gb nitride-ROM (NROM) paper is achieved by storing two bits per nitride pocket, effectively lowering the cost per bitof that technology.

As NAND becomes the storage of choice in many different applications, cost is not the only parameter that people care about, per-formance is also required in these applications. Paper 23.4 (Micron; Intel) describes a very-high-performance single-level-cell devicewith 100MB/s program throughput and 200MB/s read-transfer rate using a DDR interface and featuring a significantly higher per-formance than any NAND devices in the market seen to date.

Pushing both cost and performance, Paper 23.1 (Sandisk; Toshiba) provides a higher write speed in a multi-level cell (MLC) by pro-gramming all bitlines simultaneously effectively improving the program rate of the lower cost MLC NAND devices. The paper describesa 16Gb MLC that achieves 34MB/s in MLC and 60MB/s in SLC.

In the area of code storage, which requires faster random access, Paper 23.3 (Intel) describes a 45nm MLC 1Gb NOR device achiev-ing a 5MB/s program speed with an impressively small die size by introducing for the first time a self-aligned-contact technology.

Phase-change memory promises to become the unified memory technology, combining the characteristics of flash with the fast readand write operation of RAM. Paper 23.5 (STMicroelectronics; Intel; U Pavia) demonstrates the feasibility of storing 2 bits/cell in aphase-change device.



Analog Power TechniquesChair: Doug Smith, SMSC, Austin TXAssociate Chair: Francesco Rezzi, Marvell Semiconductor, Pavia, Italy

Analog techniques for embedded circuits handling power with high efficiency are presented in this session. Two common applicationsare audio drivers for mobile applications and integrated power management. Reducing external bills of materials by using higher lev-els of integration continues to be a trend. Power converters aim for higher bandwidth for fast load switching and polar RF transmit-ters.

The session begins with advances in audio electronics. Paper 24.1 (Texas A&M U) presents a class-AB audio headphone driver madecapable of tolerating a wide range of load capacitance up to 22nF by using a load-capacitance-aware compensation scheme. Paper 24.2(Texas Instruments) presents a digital audio subsystem including dual-channel 5th-order DACs and closed-loop class-D drivers in 90nmCMOS capable of being directly connected to a battery, which avoids the cost and complexity of additional regulators and externalblocking capacitors.

Paper 24.3 (National Chiao Tung U; National Taiwan U) presents a new CMOS voltage reference architecture that does not use con-ventional diodes, but instead combines a ΔVGS voltage generated by switching between two positive-TC currents created by the dif-ference between MOS devices in saturation and subthreshold operation. The resulting reference has a temperature coefficient of16.9ppm/°C.

Paper 24.4 (HKUST) presents a buck converter that addresses the problem of driving light loads efficiently by using a clock-frequencyswitching scheme that maintains a predictable noise spectrum for SoC architects. Paper 24.5 (HKUST) presents an LDO circuit thatuses a new dynamic current mirror to significantly increase pass transistor gate drive capability during positive transients. This fastresponse time is made possible despite the low quiescent current of 4μA at no load. Paper 24.6 (U Pavis; National Semiconductor)presents a single-inductor four-output buck converter with gate-boosted NMOS drivers to improve efficiency and a novel controlscheme using linear combinations of the errors of all four outputs to independently regulate the output voltages. Paper 24.7 (KAIST;JDA Technology; LG Electronics) presents a DC-DC converter with a freewheeling current-feedback-based control method suitable forsingle-inductor multiple-output converters that improves output voltage regulation during heavy-to-light load transitions. Paper 24.8(Arizona State U) addresses the need for higher bandwidth by using a driver amplifier that combines a linear buffer and class-D regu-lator in parallel to provide an envelope-modulated supply voltage to a CDMA transmitter power amplifier. The resulting supply regu-lator tracks the envelope to within 0.2% with a maximum efficiency of 82%.


Session 25 Overview / Wireline [AP70]

Building Blocks for High-Speed TransceiversChair: Wolfgang Pribyl, Graz University of Technology, Graz, AustriaAssociate Chair: Jerry Lin, MStar Semiconductor, Hsinchu, Taiwan

The demand for more bandwidth in communication and computation is never satisfied. Thus the need for ever-increasing speed of theinterconnect circuits and channels drives the electronics industry to explore advanced design techniques in order to provide ever higherspeed at lower cost.

The rapid decrease in the line width of CMOS technologies down to 45nm has opened the door for low-cost and high-speed designs.That in turn has made building blocks for multi-GB/s transceivers a reality. Besides the high-speed operation – approaching 100GHzin two papers – also multiple lanes for high-speed memory to CPU interfaces leading to aggregate data rates exceeding 100Gb/s aregaining more and more interest. Innovative oscillator concepts are presented in this session as well as a highly integrated 90nm cir-cuit for powerline communications.

Three papers in this session demonstrate high-speed performance and low power consumption realized in advanced process tech-nologies. Paper 25.1 (Intel; U Washington) is one of the first receiver implementations in 45nm achieving a speed of 27Gb/s. Paper25.5 (IBM) uses a 65nm SOI CMOS process to implement a CML static divider working up to 94GHz, consuming only 15.8mW per flip-flop at 82.4GHz. Paper 25.8 (National Taiwan U) implements low-power injection-locked frequency dividers for frequency ranges of 85.1to 96.3GHz and 98.9 to 105.2GHz, respectively.

There are three papers that deal with advanced concepts of clock generation and data retiming. Paper 25.2 (Conexant) combines thelow spur of a PLL with the low phase noise of a recirculating DLL at 800MHz. In Paper 25.3 (NTT; Gunma U) a 0.25μm BiCMOS tech-nology is used to implement a data-timing generator, an important building block for adjusting delay in parallel optical paths. It sup-presses the effects of group delay for data streams up to 11Gb/s. A 65nm open-loop quadrature clock generator for a 370MHz to2.5GHz range is presented in Paper 25.4 (IBM).

Two papers show designs for high data throughput architectures: Paper 25.6 (Diablo Technologies) reports a 115Gb/s serial link basedon 4.8Gb/s transceivers in 90nm CMOS and Paper 25.9 (Harvard U; Oregon U) describes an 8x3.2Gb/s parallel receiver in 0.13μm CMOSincorporating a global timing- recovery block for timing-error correction and jitter-tolerance bandwidth enhancement.

Finally, Paper 25.7 (Gigle Semiconductor; U Edinburgh} presents an analog front-end for powerline communication implemented in90nm CMOS, suitable for integration into a single chip powerline modem. It achieves a data rate of 200Mb/s and is scalable towardsthe Gb/s range by using 2 bands and advanced modulation schemes.



Wireless Frequency GenerationChair: Nikolaus Klemmer, Ericsson Mobile Platforms, Research Triangle Park, NCAssociate Chair: Chris Rudell, Intel, Santa Clara, CA

Aggressive scaling in digital CMOS technologies has led to the availability of MOS devices with minimum feature size of 45nm and unitygain frequencies in excess of 200GHz. This session focuses on advances in frequency generation building blocks which exploit thesedevices to realize CMOS circuits operating, for the first time, in the THz range. In particular, we see several implementations of signalsources at record frequencies, previously only attainable with costly niche technologies, such as III-V compound semiconductors. Uti-lization of the frequency generators presented in this session paves the way towards development of future highly integrated high-data-rate receivers and transmitters.

The improved operation of CMOS circuits at mm-wave frequencies opens up an avenue for low-cost implementation of communica-tion systems in the unlicensed 60GHz ISM band, automotive radars at 77GHz, remote object sensing, detection and analysis as wellas biological/chemical agent detection.

This Session begins with Paper 26.1 (U Florida) that describes a 410GHz frequency generator in 45nm CMOS. This device uses the2nd-harmonic of a 205GHz fundamental frequency oscillator, which breaks the previous record for highest oscillation frequency inCMOS, and most notably suggests the feasibility of low-power THz in CMOS. Paper 26.2 (U Modena & Reggio Emilia; Lund U) de-scribes a novel insight into the low-noise design of class-C LC oscillators and shows a 5GHz implementation in 0.13μm CMOS with anFoM of 195dBc/Hz, without the use of additional noise filtering components.

Paper 26.3 (UCLA; JPL) describes another impressive CMOS frequency generator that uses an 81GHz quadrature VCO in 90nm CMOStogether with a frequency quadrupling circuit to generate a 324GHz signal.

Using a bulk acoustic wave (BAW) resonator, Paper 26.4 (CEA-LETI/MINATEC) describes a 2.2 GHz oscillator, using a novel way to pushthe traditionally narrow tuning range in piezoelectric resonators to 10%, more than a factor of five larger than prior art. This is followedby Paper 26.5 (TU Delft; IBM) that describes a ring-oscillator-based frequency tripler at 60GHz with 8GHz tuning range in 90nm bulkCMOS and near-ideal phase-noise characteristics, relaxing the requirements for fundamental frequency oscillators. Paper 26.6 (Hitachi)highlights a 28GHz VCO in 0.13μm with record FoM for oscillators above 20GHz, applying a similar insight as Paper 26.2 for noise re-duction.

Finally, Paper 26.7 (Intel; TI; Georgia Tech) shows a 40GHz fractional-N PLL in 90nm CMOS that uses a digitally calibrated injection-locked divide-by-four as a low-power prescaler.



ΔΣ Data ConvertersChair: Zhongyuan Chang, IDT Technology, Shanghai, ChinaAssociate Chair: Yiannos Manoli, University of Freiburg, Freiburg, Germany

While ΔΣ data converters have been with us for over 20 years now, new developments are driving the technology to new achievemtsin various directions like wider bandwidths, higher resolutions and lower power. As the papers in this session show, new techniquesas well as advanced processes make these accomplishments possible.

The authors of Paper 27.1 (Analog Devices) present a ΔΣ audio DAC that uses a three-level dynamic element matching (DEM) schemeto reduce noise and power consumption. An output stage with low inter-symbol interference achieves 108dB SNR. Power dissipationis at 1.1mW per channel from a 1.8V supply in a 0.18μm CMOS process.

The next two papers present the idea of implementing the analog filter using an inverter-based integrator. Paper 27.2 (Yonsei Univer-sity) is a 20kHz audio ΔΣ ADC, which operates at a low voltage of 0.7V while dissipating an ultra-low power of 36μW in a 0.18μmprocess. It achieves these figures by using a class-C inverter-based integrator in a 3rd-order discrete-time feed-forward modulator.

Paper 27.3 (NXP) carries on the inverter idea to a time-continuous implementation of the integrator. This digital-analog hybrid ΔΣmodulator takes advantage of the area scaling of digital circuits in a 65nm process by implementing part of the loop filter in the digi-tal domain. The first integrator and the comparators of a 5-bit quantizer are implemented using inverter circuits while a second-orderfilter with a 1-bit quantizer are digital. With an area of only 0.03mm2 and a power consumption of 950μW, the modulator achieves anSNR of 77dB in a bandwidth of 200kHz.

The next Paper 27.4 (Oregon State U; Asahi Kasei) uses time interleaving in a two-channel modulator to double the effective samplingrate to 200MHz with a 100MHz clock. Noise coupling between the two channels by injecting the quantization noise of one loop into theother raises the effective order of both noise-shaping loops from two to three. This method leads to a low THD of -98dB and a SFDRof over 100dB in a 4.2MHz bandwidth.

The authors of Paper 27.5 (Intel; Cornell U; Georgia Tech) present a modulator employing a digital signal analyzer for the choice of loop-filter configuration in a MASH 2-2 ΔΣ. Intended for WiMAx receivers. It uses a feed-forward path that eliminates analog-summing andsimultaneously provides the spectrum-sensing function.Paper 27.6 (Analog Devices) describes a single-loop 5th-order CT modulator that uses a combination of feed-forward and feedback pathswhich allow more aggressive NTF scaling and result in a power consumption of 100mW for a signal bandwidth of 10 MHz and a clockrate of 640MHz. It achieves a dynamic range of 87dB and a SNDR of 82dB.

Continuous-time modulators suffer from variations of the time constants in the loop filter. A method to auto-tune these coefficients byinjecting a tone at the quantizer is presented in Paper 27.7 (UC San Diego; Conexant). A servo feedback loop trims the integrator ca-pacitors so as to match a zero in the NTF to this tone. This method is demonstrated by a 65nm 3rd-order modulator with an 8 MHz band-width and 81dB DR.

The last paper, Paper 27.8 (Infineon) presents the implementation of a ΔΣ modulator in 45nm for the first time. This voice-coding ADCachieves 86dB DR for a power consumption of 1.2mW over a 20kHz bandwidth.


Session 28 Overview / Memory/High-Performance Digital [AP26]

Non-Volatile Memory and Digital ClockingChair: Mark Bauer, Intel, Folsom, CAAssociate Chair: Suhwan Kim, Seoul National University, Seoul, Korea

The first three papers of this Session are a continuation of the morning session on non-volatile memory, with discussions on recentflash memory advancements in array structure, multi-bit storage and expanded endurance capability. These advancements expand thecapability of existing flash applications such as mp3 players, digital video, solid-state disks, automotive-engine control as well as newapplications that are in development. The next four papers deal with clocking, which is a critical component of high-performance mi-croprocessors due to the difficulty of generating and distributing a clock with low skew and jitter. A series of clock generation and dis-tribution techniques address issues such as process portability, power dissipation, low jitter, and skew.

In the flash memory multi-bit per storage arena, the first paper, Paper 28.1 (Sandisk; Toshiba) describes a NAND design capable of stor-ing 8 analog levels in each memory cell, equating to 3 digital bits of storage per memory cell. The current state of the art in NAND isstoring 2 bits per cell. This breakthrough chip stores 3 bits per physical cell in a 56nm NAND flash technology. Historically, increasingthe number of analog levels per cell severely reduces programming speed. Using a new approach, this design programs more simul-taneous user bits into the memory array compared with traditional approaches. This achieves a write throughput of 8MB/s, which iscomparable with the performance of 2 bit/cell designs previously reported at ISSCC.

Paper 28.2 (Renesas) reports an embedded flash memory module that uses a NOR flash to emulate the performance, endurance andretention characteristics of a traditional EEPROM monolithic memory. This work targets automotive applications that require non-volatile memory supporting frequent writes and long data-retention times. Embedding the EEPROM function reduces overall systemcost. The paper reports a new NOR flash cell that has separate read and write channels. This channel separation ensures the wear-outmechanisms of a write operation do not degrade the read operation, allowing 1 million program/erase cycles on every memory cell ona 0.13μm NOR flash process.

As real estate becomes scarce in parts of the world, people build multi-story dwellings. Using the same approach, the final memorypaper, Paper 28.3 (Samsung) proposes building memory array cores on top of each other, increasing the bit density per unit area. Thepaper describes two memory arrays stacked on top of each other and connecting to one level of peripheral devices through metallines. The design takes advantage of a 3D array of 43nm NAND flash and 2 bit/cell storage to achieve 0.0021μm2/bit. The design fea-tures a 2.5MB/s write-throughput time, which is comparable to previously reported traditional planar NAND flash arrays.

Distributing high-speed clocks in large microprocessors is always challenging. Two papers in this Session implement clock distribu-tion using LC-resonant techniques. Paper 28.4 (IBM) is the first demonstration of a resonant full global clock grid. The paper describesthe transformation of the legacy global clock-distribution network of this 90nm Cell processor into a resonant clock operating up to5GHz. An additional 1.2μm-thick copper metal layer implements the spiral inductors. Real workloads show a power savings of about5% over the traditional clock distribution method. Paper 28.7 (Hiroshima U) demonstrates additional refinement of these techniqueswith a 9.5GHz LC-clock distribution network with low skew and jitter implemented in 6M 0.18μm CMOS. Twelve inductively-loadedstanding-wave oscillators are cascaded to form a continuous structure that completely fills a 4.84mm2 chip area. The total power is60% of conventional CMOS clock buffers and provides promise for further improvements of this method for mainstream processors.

Paper 28.5 (National Taiwan U) describes a multiphase DLL that helps solve one of the challenges of generating clock edges for I/Odrivers and timing applications that need equally spaced clocks within a cycle. These I/O-clock edges are typically subject to the vari-ations of the intermediate buffer states, but this design uses multiple phase detectors to improve phase accuracy and jitter perform-ance by locking the intermediate edges. The DLL is fabricated in 90nm operates from 8 to 10 GHz.

Paper 28.6 (IBM; Texas A&M U) demonstrates two digital PLLs that build on the advances in this area first demonstrated at ISSCC 2007.One PLL uses a digitally-controlled ring oscillator (1 to 2 GHz) and one uses an LC tank oscillator (24 to 32 GHz). Both PLLs use sim-ilar standard-cell-based control circuits, implementing a proportional-integral loop filter. These approaches show performance com-parable to traditional analog approaches, but promise lower design effort, power consumption and easier debug and bring-up.



TD: Trends in Communication Circuits & SystemsChair: Koji Kotani, Tohoku University, Sendai, JapanAssociate Chair: Christian Enz, CSEM, Neuchâtel, Switzerland

Watching TV or surfing the internet, anytime, and anywhere, is driving the needs for communication systems with increased portabilityand higher data rates. Moreover, new sensor network applications will demand ultra-low-power and more flexible communicationprotocols. Solutions for this nomadic life style and ubiquitous intelligence will be enabled to a large extent by innovations in integratedcircuits and systems. These systems will have to be highly integrated, energy efficient and very low-cost. They will also have to providehigher bandwidth and be adaptive to make an efficient use of the spectrum resource.

The eight papers in this session present cutting-edge solutions leveraging MEMS-based radio, 45nm CMOS circuits, multi-gate devicesand cognitive radio techniques to address these challenges.

The first two papers present two ways to reduce the power consumption of radios. Paper 29.1 (CSEM) describes a 2.4GHz MEMS-basedtransceiver taking advantage of high-Q BAW resonators for RF filtering and RF frequency synthesis, combined with a temperature-com-pensated silicon resonator. The poor frequency-tunability of BAW resonators is circumvented by a new heterodyne architecture, wherethe IF is derived from the fixed RF carrier by open-loop frequency division. The radio is implemented in a 0.18μm CMOS process andexhibits a -80dBm sensitivity at 37.5kb/s with a 10-3 BER while consuming 7.5mA. Another way to significantly reduce power con-sumption is to use an ultra-low-power wake-up radio combined with a full-featured radio. Such an ultra-low-power wake-up radio forwireless sensor network applications is described in Paper 29.2 (UC Berkeley). The heterodyne receiver uses a high-Q BAW resonatorRF filter in the front-end, followed by a mixer, broadband IF amplifier and power detector. The LO is generated by a digitally-calibratedring oscillator and the inaccuracy of the IF is handled by the wideband IF amplifier chain. The radio is implemented in a 90nm CMOStechnology, operates at 2GHz, and achieves a -72dBm sensitivity at 100kb/s while consuming only 52μW from a 0.5V supply.

In order to better use the frequency spectrum resources, Paper 29.3 (Georgia Tech; Samsung; Hanbat National U) presents a UHF re-ceiver including a spectrum sensing capability with arbitrary detection bandwidth. The multi-resolution detection is based on a digitalwindow generator combined with an analog correlator. The radio is implemented in a 0.18μm CMOS technology and achieves a -60dBm sensitivity with 30dB dynamic range, consuming 180mW from a 1.8V supply.

The next two papers discuss device and circuit techniques for future communication systems. Paper 29.4 (IMEC) evaluates the effectsof the different technology options that are foreseen for further CMOS downscaling beyond 45nm. Measurements made on basic build-ing blocks such as comparators, opamps and mm-wave VCOs show that planar bulk-strained CMOS offers a speed advantage com-pared to multigate FinFET technology, which achieves better low-frequency analog performance. Paper 29.5 (U Twente) explores theuse of redundant devices to extend the lifetime of power circuits subject to oxide breakdown. The technique, based on gate voltage sens-ing, is validated on a RF power amplifier (PA) implemented in a 90nm CMOS technology and operates from a 1.2V supply. A typicallifetime extension by a factor of 2.6 can be achieved.

Paper 29.6 (International Superconductivity Technology Center; Japan Science and Technology Agency; Yokohama National U; Na-tional Institute of Information and Communications Technology; Nagoya U) presents a superconductive switch system achieving a40Gb/s data rate. The superconductive single-flux-quantum switch chip together with a superconductive amplifier chip is cooled to4K enabling a switching time <25ps for a power consumption of 0.51mW.

Paper 29.7 (NEC) presents a low-power dual-band transceiver for sensor network applications. An asymmetric full-duplex link usingtwo different frequency bands and a vine-tree network topology realize a low-power ad-hoc multi-hop network. The UHF channel runsat 433MHz and offers a 2.4kb/s data rate, whereas the 2.4GHz WLAN band provides a 6.1Mb/s link.

The last paper 29.8 (IMEC; VUB) reports a 4.7-6.4GHz very low power VCO implemented in a 45nm bulk CMOS process using anabove-IC high-Q inductor. The circuit is placed directly below the inductor, shielded by top metal layers and slightly offset to reducethe EM coupling. The reuse of the silicon beneath the inductor leads to a 28% area reduction. The VCO achieves a 185dB FoM with apower consumption of only 400μW.



Data-Converter TechniquesChair: Michael Flynn, University of Michigan, Ann Arbor, MIAssociate Chair: Kunihiko Iizuka, Sharp, Nara, Japan

Defying predictions of facing a brick wall in converter performance, analog designers continue to develop new techniques to exploitthe speed and density of nanometer CMOS processes. The key challenges are the low power supply voltage and the poor analog be-havior of the standard transistors. New techniques presented in this session not only help deliver higher performance but also enableemerging applications such as time-to-digital conversion and clockless signal processing.

Parallelism is a recurring theme in the papers in this session. Much like a hybrid car which combines the best of two engines, ADC de-signers are configuring very energy-efficient successive approximation (SA) ADC cores in parallel time-interleaved arrays, sampled athigh data rates and operating at optimal energy efficiency. In this session, we see papers at two extremes of parallelism. The authorsof Paper 30.2 (U Texas; Analog Devices) present an example that uses two SA cores while in Paper 30.3 (Nortel; STMicroelectronics)parallel SA ADCs are combined to achieve a 24GS/s throughput.

Redundancy is another technique highlighted in the papers. Smaller feature size and higher transistor speeds, make redundancy prac-tical, both in terms of extra hardware and in the utilization of spare clock cycles. Paper 30.3 makes use of the spare time, created byparallelism, to self calibrate its core SA ADCs. Paper 30.2 uses redundant capacitor arrays to avoid dissipating static power in a resis-tive ladder while Paper 30.8 (MIT) uses redundant comparators in combination with calibrated selective power-down to increase pro-duction yield.

Calibration is becoming mainstream with digital post-processing being used to compensate for analog imperfections. Several of thepapers in the session use some form of calibration either in the background, as in Papers 30.3 and 30.4, or in the foreground (or atstartup) in Papers 30.5 (Infineon; TU Munich) and 30.8. Paper 30.4 (MediaTek) specifically addresses the convergence time of back-ground calibration, by using a parallel coarse estimate of the signal to give substantial aid in de-correlating the signal from the randomcalibration sequence.

The authors of Paper 30.1 (Oregon State U) present a circuit technique that uses correlated level shift to increase amplifier loop gain.Aside from enabling rail-to-rail operation, this technique also eases the gain requirement of the residue amplifiers, effectively squar-ing loop gain and allowing low gain amplifiers to achieve high-accuracy settling. Paper 30.7 describes a technique to implement time-skewed interleaving, enabling the same comparator to be used twice on alternate clock cycles in a flash ADC.

An innovative technique based on an activity-dependent ADC is presented in Paper 30.6 {from Columbia U}. This technique does notsuffer from traditional quantization error or aliasing. A complete sub-system is implemented comprising a level-dependant ADC, anon-uniform sampling data filter, and a DAC.



RF & mm-Wave Power AmplifierChair: Satoshi Tanaka, Renesas Technology, Komoro, JapanAssociate Chair: Andreas Kaiser, IEMN-ISEN, Lille, France

Process technology evolution allows circuit design engineers to apply sophisticated methods to power amplifiers, and achieve lagerintegration levels and higher operating frequencies. It also extends the applicable frequency range to mm-wave band.

Some sophisticated power amplifier architectures such as envelope elimination and restoration (EER) or outphasing amplifiers havebeen known for a long time. Those methods have been theoretically promising, however, because they require high integration levelsand fast operating frequencies, it was difficult to use these techniques in mobile communication terminals. With advanced technology,those sophisticated methods are becoming reality.

The circuits for mm-wave applications have been rather costly. With progress of technology, low-cost CMOS mm-wave solution havebecome realistic and this situation has stimulated activities in mm-wave CMOS PAs especially in the consumer electronics area. Oneof the most important challenges is the design of power amplifiers able to provide both gain and power up to the mm-wave band.

This session focuses on the above areas and 8 novel designs will be presented. The session consists of presentations on an mm-wavetransceiver, 2 mm-wave Pas, followed by 5 PAs for mobile communication terminals.

The session begins with three 90nm CMOS mm-wave transceiver and power amplifiers. Paper 31.1 (NEC) demonstrates complete di-rect-conversion transceiver with a PA achieving an output power of 8.4dBm with power added efficiency of 7.0%. Paper 31.2 (UCBerkeley) presents a differential 12.3dBm output power PA with transformer inter-stage matching circuits. Paper 31.3 (Fujitsu) showsPAs with short stub matching circuits at 60GHz and 77GHz which achieve 10.6dBm and 6.3dBm output power, respectively.

Three power amplifiers with EER, PWM, and LINC algorithms follow in the session. Paper 31.4 (STMicroelectronics) presents a sin-gle chip WCDMA envelope-restoration-type 27dBm 46% PAE PA with 130MHz operation switched mode power supply circuits. Paper31.5 (U Washington; Intel) demonstrates 28.6dBm class-E PA with a pulse-width and pulse-position modulator. Paper 31.6 (UCLA; Mat-sushita) presents 20dBm output power adaptive load controlled out-phasing type PA for software-defined radio. It is tested for GSM,EDGE and WCDMA signals.

Paper 31.7 (Axiom) presents a fully integrated quad-band PA for GSM/GPRS with standard 0.13μm CMOS. The final paper of the ses-sion, Paper 31.8 (STMicroelectronics) describes a multi-mode multi-band balanced SiGe PA module for GSM/EDGE/WCDMA.



MEMS and SensorsChair: Farrokh Ayazi, Georgia Institute of Technology, Atlanta, GAAssociate Chair: Christoph Hagleitner, IBM, Ruschlikon, Switzerland

Low-power precision microsensors are increasingly used in consumer and industrial electronics. Realizing reliable low-noise and low-offset silicon sensors in a power- and cost-efficient way has remained a challenging task and is the subject of much of this session,which deals with a variety of sensors and actuators.

The first paper of the Session, Paper 32.1 (TU Delft) presents a new approach to temperature sensing using the phase shift of an on-chip electro-thermal filter. The untrimmed inaccuracy of 0.5°C achieved in this work is equivalent to the performance of state-of-the-art BJT-based temperature sensors. Paper 32.2 (TU Helsinki) reports on an ultra-low-power interface IC for capacitive three-axisaccelerometers with applications in handsets, gaming and medical fields. Paper 32.3 (UC Berkeley) demonstrates mode-matching ofa capacitive MEMS gyroscope in a closed-loop system with low power consumption. The mode-matching algorithm is based on ap-plying a pilot tone to the vibrating micromechanical sensor. The sensor achieves a noise floor of 0.004°/s/√Hz in 50Hz bandwidth at1mW.

Paper 32.4 (Toshiba) reports on a driver IC for an RF MEMS variable switched capacitor that substantially improves the lifetime andreliability of the switch. The bipolar actuation architecture is based on detecting the onset of stiction caused by dielectric charging andadjusting the polarity of the actuation voltage accordingly to prevent failure. Such devices can find application in reconfigurable RF front-ends. Paper 32.5 (Georgia Tech) demonstrates a chopped interface IC for capacitive accelerometers that uses lateral-BJT input tran-sistors in a 0.6μm CMOS process to reduce flicker noise at near-DC frequencies. The interface circuit attached to the accelerometerachieves an output noise floor of -118dBV/√Hz at 3Hz with a bias instability of 24μg. When combined with precision micro-gyro-scopes, these devices can assemble into micro inertial measurement units for GPS-augmented and/or indoor short-range navigationin consumer products. Paper 32.6 (Microbridge Technologies) describes a CMOS chip to that electrically adjusts thermally-isolated on-chip resistors to cover a range of temperature coefficients of offset and sensitivity to compensate those of a resistive sensor.

Paper 32.7 (IRST) presents a low-power 64×128-pixel vision sensor intended for object recognition in battery-operated sensor networkapplications. The sensor performs visual feature extraction at lower energy than previously reported implementations. Paper 32.8 (UGlasgow) presents a 16×16 ion-sensitive field-effect-transistor (ISFET) array for direct imaging of hydrogen ion activity of cell cul-tures. The paper proposes techniques to alleviate the known instability of ISFET arrays.


NOTES

ISSCC 2008PRESS COPY

Press-Release Material

•Condition of Publications•Press Copy


CONDITIONS OF PUBLICATION

PREAMBLE

• The Session Overviews to follow serve to capture the context, highlights,and potential impact, of the papers to be presented in each Session atISSCC 2008 in February in San Francisco.

• OBTAINING COPYRIGHT to ISSCC press material is EASY !

• You are welcome to use this material, copyright- and royalty-free, with the following understanding:

� That you will maintain at least one reference to ISSCC 2008 in the bodyof your text, ideally retaining the date and location. For detail, see theFOOTNOTE below.

� That you will provide a courtesy FAX of your excerpted press piece andparticulars of its placement, to 416-971-2286, Attention ISSCC PressRelations.

FOOTNOTE

• From ISSCC’s point of view, the phraseology included in the box belowcaptures what we at ISSCC would like your readership to know about this,the 55th appearance of ISSCC, on February 3rd to 7th, in San Francisco.



TABLE OF FEATURED PAPERS Paper Number Subcommittee AP Page Press-Book Page Press-Copy Page

2.1 Imagers, MEMS, Medical and Display 162.2 Imagers, MEMS, Medical and Display 16 672.3 Imagers, MEMS, Medical and Display 162.4 Imagers, MEMS, Medical and Display 162.5 Imagers, MEMS, Medical and Display 16 682.6 Imagers, MEMS, Medical and Display 172.7 Imagers, MEMS, Medical and Display 172.8 Imagers, MEMS, Medical and Display 172.9 Imagers, MEMS, Medical and Display 172.10 Imagers, MEMS, Medical and Display 173.1 Analog 18 29 2033.2 Analog 18 29 2033.3 Analog 183.4 Analog 183.5 Analog 193.6 Analog 19 303.7 Analog 194.1 High-Performance Digital 20 54 2044.2 High-Performance Digital 20 54 2044.3 High-Performance Digital 204.4 High-Performance Digital 214.5 High-Performance Digital 214.6 High-Performance Digital 21 55 2054.7 High-Performance Digital 21 55 2055.1 Wireline 22 2065.2 Wireline 22 155 2065.3 Wireline 225.4 Wireline 225.5 Wireline 23 155 2065.6 Wireline 235.7 Wireline 235.8 Wireline 236.1 Wireless 246.2 Wireless 24 2076.3 Wireless 246.4 Wireless 24 140 2076.5 Wireless 256.6 Wireless 256.7 Wireless 25 1406.8 Wireless 25 2076.9 Wireless 25 2077.1 Technology Directions 26 125 2087.2 Technology Directions 26 125 2097.3 Technology Directions 267.4 Technology Directions 26 126 2107.5 Technology Directions 27 126 2107.6 Technology Directions 27 126 2117.7 Technology Directions 27 2117.8 Technology Directions 27 1258.1 Imagers, MEMS, Medical and Display 32 698.2 Imagers, MEMS, Medical and Display 32 698.3 Imagers, MEMS, Medical and Display 328.4 Imagers, MEMS, Medical and Display 328.5 Imagers, MEMS, Medical and Display 338.6 Imagers, MEMS, Medical and Display 33 708.7 Imagers, MEMS, Medical and Display 33 708.8 Imagers, MEMS, Medical and Display 339.1 RF 349.2 RF 34 1079.3 RF 34 1089.4 RF 349.5 RF 35 1089.6 RF 35 1079.7 RF 359.8 RF 359.9 RF 35



10.1 Wireless 3610.2 Wireless 36 14210.3 Wireless 3610.4 Wireless 36 142 21310.5 Wireless 37 142 21310.6 Wireless 37 142 21310.7 Wireless 3710.8 Wireless 3710.9 Wireless 3711.1 Wireline 38 15611.2 Wireline 3811.3 Wireline 3811.4 Wireline 38 15611.5 Wireline 3911.6 Wireline 3911.7 Wireline 39 15611.8 Wireline 3912.1 Data Converters 40 215, 21812.2 Data Converters 40 215, 217, 21812.3 Data Converters 40 43 215, 21812.4 Data Converters 41 43 215, 216, 21812.5 Data Converters 41 215, 21812.6 Data Converters 41 215, 21812.7 Data Converters 41 215, 21812.8 Data Converters 41 215, 21813.1 Low-Power Digital 42 84 21913.2 Low-Power Digital 42 84 22013 3 Low-Power Digital 4213.3 Low Power Digital 4213.4 Low-Power Digital 4313.5 Low-Power Digital 4313.6 Low-Power Digital 4314.1 Memory 44 9314.2 Memory 4414.3 Memory 4414.4 Memory 4414.5 Memory 45 94 22114.6 Memory 4514.7 Memory 4515.1 Technology Directions 46 12715.2 Technology Directions 46 12715.3 Technology Directions 46 12715.4 Technology Directions 46 22215.5 Technology Directions 4715.6 Technology Directions 4715.7 Technology Directions 4715.8 Technology Directions 4715.9 Technology Directions 4716.1 Low-Power Digital 48 86 22316.2 Low-Power Digital 48 86 22316.3 Low-Power Digital 4816.4 Low-Power Digital 4916.5 Low-Power Digital 4916.6 Low-Power Digital 49 87 22416.7 Low-Power Digital 49 22417.1 RF 50 22517.2 RF 50 22517.3 RF 50 22518.1 Technology Directions 51 12918.2 Technology Directions 5118.3 Technology Directions 5118.4 Technology Directions 51 226



19.1 Analog 52 31 22719.2 Analog 52 22719.3 Analog 52 22719.4 Analog 52 22719.5 Analog 53 22719.6 Analog 53 31 22719.7 Analog 53 22720.1 Wireless 5420.2 Wireless 54 144 22820.3 Wireless 5420.4 Wireless 54 144 22820.5 Wireless 5520.6 Wireless 5520.7 Wireless 5520.8 Wireless 5520.9 Wireless 5521.1 Memory 56 95 22921.2 Memory 56 9621.3 Memory 5621.4 Memory 5621.5 Memory 5721.6 Memory 5721.7 Memory 5721.8 Memory 5722.1 High-Performance Digital 64 56 23022.2 High-Performance Digital 64 56 23022.3 High-Performance Digital 6422.4 High-Performance Digital 6422 5 High-Performance Digital 64 57 23122.5 High Performance Digital 64 57 23122.6 High-Performance Digital 65 57 23122.7 High-Performance Digital 65 57 23122.8 High-Performance Digital 6522.9 High-Performance Digital 6523.1 Memory 66 9723.2 Memory 6623.3 Memory 6623.4 Memory 67 9723.5 Memory 67 9823.6 Memory 6724.1 Analog 6824.2 Analog 6824.3 Analog 6824.4 Analog 68 32 23224.5 Analog 6924.6 Analog 6924.7 Analog 6924.8 Analog 69 32 23225.1 Wireline 70 157 23325.2 Wireline 70 15725.3 Wireline 7025.4 Wireline 7025.5 Wireline 7025.6 Wireline 7125.7 Wireline 7125.8 Wireline 7125.9 Wireline 71 23326.1 RF 72 109 23426.2 RF 72 23426.3 RF 72 109 23426.4 RF 72 23426.5 RF 73 23426.6 RF 73 23426.7 RF 73 234



27.1 Data Converters 7427.2 Data Converters 7427.3 Data Converters 7427.4 Data Converters 7427.5 Data Converters 7527.6 Data Converters 7527.7 Data Converters 7527.8 Data Converters 75 4528.1 Memory 76 97 23528.2 Memory 7628.3 Memory 76 9928.4 Memory 7728.5 Memory 7728.6 Memory 7728.7 Memory 7729.1 Technology Directions 78 130 23629.2 Technology Directions 78 13029.3 Technology Directions 7829.4 Technology Directions 7829.5 Technology Directions 7929 6 Technology Directions 7929.6 Technology Directions 7929.7 Technology Directions 7929.8 Technology Directions 7930.1 Data Converters 8030.2 Data Converters 8030.3 Data Converters 80 4430.4 Data Converters 8030.5 Data Converters 8130.6 Data Converters 8130.7 Data Converters 8130.8 Data Converters 8131.1 RF 82 23731.2 RF 82 23731.3 RF 82 23731.4 RF 82 23731.5 RF 83 110 23731.6 RF 83 110 23731.7 RF 83 111 23731.8 RF 83 23732.1 Imagers, MEMS, Medical and Display 84 7132.2 Imagers, MEMS, Medical and Display 84 7132.3 Imagers, MEMS, Medical and Display 8432.4 Imagers, MEMS, Medical and Display 8432.5 Imagers, MEMS, Medical and Display 8532.6 Imagers, MEMS, Medical and Display 8532.7 Imagers, MEMS, Medical and Display 8532.8 Imagers, MEMS, Medical and Display 85


Papers: 3.1, 3.2 [AP18] ANALOG

PPRREESSSS CCOOPPYYBreakthroughs in Filters for Cellphones

Today’s cellphones must work on more than one system platform, which requires filters tuned for different gainsand passband frequencies for optimum performance. An array of fixed-gain and fixed-frequency filters with ap-propriate switching can be used, but this is costly in terms of complexity, power, and area. In addition, the extraswitches can degrade performance.

This year, in February, at ISSCC 2008, researchers from NEC (Paper 3.1) and Sony (Paper 3.2), will describe tech-niques to achieve this needed flexibility within a single multi-system chip, while maintaining the required per-formance. Both aim to make highly-digitized radio architectures more efficient and easier to implement.Techniques described will reduce the power, cost, and size of future cellphones while dramatically increasing theirflexibility of use.



Papers: 4.1, 4.2 [AP20] HIGH-PERFORMANCE DIGITAL

PPRREESSSS CCOOPPYYNew Processors Push Both Multi-Threaded Throughput

and Single-Threaded Performance

Microprocessors continue to integrate more and more computational processors (cores) on a single chip, asprocess technology enables continually shrinking devices. This expansion has improved total throughput forhigh-end servers, since each multicore chip can simultaneously execute several programs from different clients.In addition, each of these cores has been increasingly multi-threaded, meaning that they can rapidly switch theirattention between different programs whenever the current program becomes stalled waiting for some long-la-tency off-chip event such as accessing the hard drive. So, a single chip can support a multitude of separate com-putation threads. However, for many computer applications, this multi-threading does not really helpperformance, since it is really the ability to execute one program as fast as possible that matters most. In fact,since decades of software development has focused on this kind of single-thread performance, processors thatintegrate many computation cores and threads still need to focus on good single-thread performance to addressthe market. This is a tough balancing act, since fast single-thread performance tends to result in large compu-tation cores and high power, which limits the number that can be integrated onto a single chip.

At ISSCC 2008, the processors session will feature a design by Sun Microsystems that attempts to address bothneeds by simultaneously optimizing for multi-threaded throughput and single-threaded performance. In order todo this, the traditional component blocks forming a “core” have been re-architected. A novel organization ofmicro-architecture components, such as an instruction cache that is shared across four pipelines, and a datacache and floating-point unit that are shared across two pipelines, results in a hierarchy of 16 micro-cores or-ganized as four core clusters, supporting 32 threads. This kind of sharing represents a new direction in proces-sor architecture, one that helps to break the stalemate between single- and multi-thread performance needs.Multi-threaded execution is also enhanced by the first-ever implementation of transactional memory on a proces-sor, which allows a set of instructions to complete atomically, thus simplifying the programmability of multiplethreads.

To enable high single-threaded performance, the processor also supports deep speculation-modes. These alloweach pipeline to continue executing instructions when it encounters a long-latency instruction such as a mem-ory load. All dependencies are propagated through dependency chains as the pipeline continues execution, andwhen the long-latency instruction becomes available, the pipeline restarts from an architectural checkpoint. Non-completed instructions are held in an efficient SRAM structure to minimize the power and area overhead of thisprocess.

This processor, from Sun Microsystems demonstrates several innovations in both multi-threaded integrationand single-threaded performance, leading to both substantial improvements in high-throughput computing andin individual applications.




PPRREESSSS CCOOPPYY

Processors Extend Integration and Reliability Limits

At ISSCC 2003, Gordon Moore, in his keynote address, admitted that “No Exponential is Forever,” pointing to lim-its on how many transistors can be packed into a single chip. These limits result partly from transistor and in-terconnect scaling, partly from power constraints, partly from design methodology and designer productivity, andpartly from the vulnerability of circuits to soft errors. High-end server products, however, would benefit frombreaking these limits, and integrating the maximum possible functionality on a chip, to continue the historicgrowth in performance.

At ISSCC 2008, the processor session will feature a four-core Itanium® processor from Intel that includes a num-ber of breakthroughs. It demonstrates the first-ever integration of two billion transistors in a single processor,whose power is managed by a dynamic and adaptive voltage- and frequency-control scheme. An on-chip con-troller counts architectural events and responds by either increasing or decreasing the power and performanceof the chip according to an on-chip lookup table. In addition, the core circuits were designed to support low-volt-age operation for further power reduction.

As can be imagined, the integration of 2 billion+ transistors on a processor chip in deep sub-micron process tech-nology presents a challenge to reliability if all of those transistors must operate correctly 100% of the time. Toimprove the reliability, and especially to deal with the issue of high-energy-particle strikes that can flip one of themany tiny memory cells in such a processor, the chip implements soft-error-immune storage elements in 99%of the system-interface latches, in 30% of the core latches, and in small register files. Large memories, such ascaches, are all protected by error-correction codes (ECC) to enable them to seamlessly deal with falsely-flippedbits.

Together, these advancements push the limits of integration and reliability for enterprise-level applications, whiledelivering the improved performance and scalability that the IT industry has come to expect.



Papers: 5.1, 5.2, 5.5 [AP22,23] WIRELINE

PPRREESSSS CCOOPPYYCMOS 10-to-40 Gb/s Transceivers Take a Lead

The generation and consumption of massive amounts of data has become commonplace in today’s industrial andconsumer environments. To meet the ever-increasing-speed demand, the maximum data rate of CMOS trans-ceivers is now pushed beyond 10Gb/s. At ISSCC 2008 in February at the San Francisco Marriott, presentationsat the High-Speed Transceivers session will describe the recent approaches.

In Paper 5.2, researchers from National Taiwan University will present a 40Gb/s receiver with adaptive equaliza-tion and a full-rate CDR in 90nm CMOS. Until now, the integration of equalizer and CDR on a single chip wasdemonstrated only up to 10Gb/s, a CMOS equalizer worked only up to 20Gb/s, and a CMOS CDR operated onlyup to 40Gb/s. Now, at ISSCC 2008, this presentation will describe the integration of a 40Gb/s equalizer and CDRon a single chip.

In Paper 5.5, researchers from a Silicon Valley company, Teranetics, will demonstrate a 10Gb/s BASE-T Ether-net transceiver for 100m UTP cables in 0.13µm CMOS. It includes a transmitter DAC, an echo-cancellation DAC,ADC, VGA and LC-tank PLL, with a power consumption of 10.5W. This design pushes the lineup of Ethernettransceivers from 1Gb/s to 10Gb/s.



Papers: 6.2, 6.4, 6.8, 6.9 [AP24,25] WIRELESS

PPRREESSSS CCOOPPYYUWB Expands Wireless Possibilities

Guglielmo Marconi would be proud of ultra-wideband radio. Although he could not have predicted all of the possibilities ignited by the simplicity of his spark-radio invention, UWB is steadily proving itself as a means ofachieving a wide array of applications, by making use of the tremendous spectrum available to wireless devices.

This year, at ISSCC 2008 in San Francisco in February, researchers from Alereon will address a fully-integratedWiMedia-compliant transceiver that has demonstrated seamless high-speed wireless connectivity. Researchersat Georgia Tech will set a new wireless speed record with their 60GHz radio capable of operating with data ratesup to 15Gb/s, that translates to downloading a movie in seconds. An ultra-low-power body network will be pre-sented by researchers from KAIST in Korea. This circuit technique will enable unprecedented battery life forportable devices. An 802.15.4a-compliant transceiver designed by researchers from the Institute of Microelec-tronics in Singapore will provide precise ranging and localization.

Overall, UWB promises to open exciting new applications for wireless technology, ones that will change the waywe interact with each other and with the world around us. Elimination of bulky cables between our laptops anddisplays, full-movie downloads in seconds, seamless connectivity to medical sensors for patient monitoring,through-the-wall imaging for firefighters, and interactive video communication on our PDAs, are just some of thepossibilities that this technology promises. The UWB circuits presented at ISSCC 2008 are a significant step for-ward in realizing these applications with compact low-cost implementations that are within the reach of the av-erage consumer.



Paper: 7.1 [AP26] TECHNOLOGY DIRECTIONS

PPRREESSSS CCOOPPYYWearable Electronic Badge for Life-Rhythm Monitoring

In the past, electronics has been used in computers and communication devices, increasing the productivity ofpeople, but, today, electronics is trying to penetrate more into the everyday human life of people. In this context,a new type of wearable electronic badge is introduced to provide in-depth information of human life and activi-ties by just wearing it [7.1]. Though several consumer products today monitor human activity by recording ac-celeration, the novel temperature monitoring approach presented in this paper leads to dramatic power, and costsavings over acceleration monitoring. “Life Thermoscope”, built from integrated circuits and electronic compo-nents can monitor its surrounding temperature in an extremely compact 30-cc badge.

In a study, a team of participants wore the badge continuously for four-months to record their temperaturerhythm. Using this sensed human-activity data, a life rhythm called “Thermo-Tapestry of Life” has been con-structed.

Ultra-low power consumption is the key to the realization of such a badge. Combining many circuit-level and sys-tem-level low-power techniques, the badge can operate for years without battery change, although it includeshigh-performance data processing and wireless networking capabilities.

We conclude that there will come a day, when all of us will wear the “Life Thermoscope”, recording our own liferhythm as a key to understanding. The badge introduced here, may be a forerunner of a new type of electronicdevice, essential as a wristwatch once was, and a cellphone now is!




PPRREESSSS CCOOPPYYRevolutionizing Health Care

With an aging population on the rise, continuous monitoring and health care automation are crucial for cost-ef-ficient quality patient care. Today, vital sign monitoring occurs only after the patient reaches the clinic. For a sen-ior citizen, the stress of getting to a clinic itself, has the potential to affect the outcome of the monitored variables.This is not only expensive, but could lead to an erroneous incomplete diagnosis. It is apparent that continuousmonitoring of patients at risk would provide superior diagnostic information. For this purpose, compact energy-efficient solid-state electronic systems, that enable continuous monitoring of a patient’s vital signs in a non-in-trusive manner have the potential to revolutionize health care in more ways than one!

At ISSCC 2008, in San Francisco Marriott, in February, researchers from the United Kingdom (Paper 7.2) will de-scribe a micro-power wireless sensor patch that is thin and flexible. This “electronic bandage” includes an en-vironmentally friendly battery that can be recycled. The patch also consists of sensors for monitoring glucose/pH,motion, heart rate, temperature, and pressure. The sensor measurements after local processing, are transmit-ted wirelessly to a base station, which in turn can communicate data and alerts, as necessary, to the health careand/or emergency services.

This solution, presented by the researchers from Toumaz Technology, upon becoming a commercial reality, couldmean that ‘low-cost quality health care’ need no longer be an oxymoron!



Papers: 7.4, 7.5 [AP27] TECHNOLOGY DIRECTIONS

PPRREESSSS CCOOPPYYVision-Restoring Retinal Implants Demonstrated

At ISSCC 2008, 2 presentations will describe the move of CMOS imaging technologies from consumer hand-heldappliances into actual biomedical applications. Details of the first-imager chip ever successfully implanted intoa human eye will be described, partially restoring vision to a blind patient. In such a design, pixel sensitivity andpixel size, two critical parameters, must be traded off together with some severe power restrictions. This devel-opment indicates that the electronics industry has arrived to the point where actual visual prosthetics are notmerely science projects, but are being prototyped as potential products.

Researchers from IMS Chips (Paper 7.4) will describe the development of a new pixel-circuit technology thatmimics the behavior of the human eye, and allows for the use of the imager in widely varying lighting conditions.The chip went though clinical trials in Tuebingen, Germany, and partially restored vision to blind patients. The ad-dition of a mechanism for the transmission of power to the device will make the product completely autonomousand untethered. A related capability developed by the team creates “mini-imagers” which can be used in variousapplications where access for conventional viewing is impossible, such as, “video pills” for performing diag-nostics inside the human body.

As well, using their second-generation-imager chip to be implanted beneath the retina, researchers from U of Ulm,NHI and Retina Implant (Paper 7.5) are preparing a system in which a power supply ribbon is run from the eyeunder the skin to behind the ear, where power will be wirelessly supplied, as is presently done with cochlear im-plants. This is needed since space is very limited behind the eye, limiting the integration complexity. In this sys-tem, every pixel in the sensor array contains a photo-sensor, some logic, and an output driver. Second-generationchip adds key improvements to voltage-drive circuits. The result is a design approach that can be extended asimager sensitivities continue to improve!



Papers: 7.6, 7.7 [AP27] TECHNOLOGY DIRECTIONS

PPRREESSSS CCOOPPYYNeuro-Electronic Interfacing Advances

Major advances in the ability to connect living neurons to high-performance electronics will be disclosed at theupcoming ISSCC 2008. The development of these important new technologies will support capabilities that rangefrom brain control of prosthetic limb movement, to the actual study of the brain itself. The integration and im-provements extended by generation upon generation of technology scaling for high-performance computing isnow being applied to the study of neuroscience, with profound implications on our understanding of this mostfundamental biological function.

Researchers from UC Santa Cruz, U Newcastle and National Chiao-Tung U (Paper 7.6) combine the ability torecord, process, and transmit in real-time 128 separate neural signals, all on a single chip, and at very-low power.Previously, each of these functions were performed independently. Requiring only a small rechargeable battery,this single-chip device will record neural activity, self-calibrate and sort out detected signal spikes, and thentransmit this data wirelessly for either analysis or prosthetic control.

As well, researchers from Columbia U (Paper 7.7) will describe their study of the behavior of individual neuralcells using microelectrode arrays with pixels whose size shares the same resolution as the cells themselves.Each output of the 7280 electrodes per square millimeter array, each output accesses a unique pulse waveformfrom a living brain slice at 50 nanosecond resolution. Alternatively, the team can use the array to stimulate indi-vidual cells with signals from 0.7 to 4.2V, the range needed to study biological signaling.

The electronic access to live brain slices made available with this technique will provide insights which will fi-nally open for detailed study a topic currently in the domain of science-fiction writers!



Session: 9 [AP34] RF

PPRREESSSS CCOOPPYYRiding the mm-Waves

Silicon integrated-circuit (IC) implementations of systems operating at millimeter-wave frequencies (such as,24GHz, 60GHz, 77GHz, and 94GHz) have exploded over the last several years. They provide numerous oppor-tunities and challenges for gigabit wireless communications, radar, remote sensing, imaging, and secure com-munication links, using mm-waves.

On the communications side, the ever-increasing demand for bandwidth has made mm-waves a serious con-tender for gigabit wireless communications. Such systems can be used in a variety of applications, such asshort-range distribution of broadband high-quality video and audio, as well as high-speed home and enterprisenetworking. The smaller wavelengths which characterize mm-waves make it possible to use a fusion of electro-magnetic and antenna techniques with a practically unlimited number of reliable transistors in a silicon inte-grated circuit, to create new methods for modulation and encoding of the data that allow for securecommunications and concurrent transmission of various independent data streams in various different spatialdirections. It is also possible to use the silicon CMOS technology in very-large-scale phased arrays as a low-costintegrated solution to create scalable tunable multi-band multi-beam phased arrays for a variety of applications.

At ISSCC 2008, in San Francisco in February, Session 9 explores the most recent developments in mm-wave ap-plications of silicon, and offers a broad set of solutions for communications, radar, imaging, concurrency, andsecurity needs in this quickly-emerging and exciting area of integrated-circuit design. The session starts with apresentation from U Toronto, which describes a very-high-frequency receiver with a low noise figure imple-mented in 65nm CMOS, extending the operation frequency close to 100 GHz. This development opens up newapplications in the area of mm-wave imaging and high-speed data communication. As well, a low-power mm-wave receiver is demonstrated by researchers from UC Berkeley with a robust mm-wave design strategy result-ing in close agreement between simulations and measurements. A paper from Caltech describes a novelmodulation technique based on changing the effective length and shape of on-chip antenna reflectors. This newapproach makes it possible to generate arbitrary signal constellations using a constant-envelope power ampli-fier (PA). Furthermore, it enables transmission of multiple data streams simultaneously in different directionsusing a single transmitter, or the creation of a secure communication link. Finally, another paper from UC Berke-ley demonstrates a distributed amplifier in 90nm CMOS with a world-record gain-bandwidth product (as high as660GHz) for ultra-fast local links operating at 100Gb/s.

As an old song says: “little things mean a lot”. This is particularly true for the application of mm-wave systemscreated in mm-dimensioned integrated circuits.



Papers: 10.4, 10.5, 10.6 [AP36,37] WIRELESS

PPRREESSSS CCOOPPYYNew Single-Chip Cellphones Enable Low-Cost Full-Featured

Next-Generation Mobile Communication

Cellphones are the world’s most ubiquitous consumer-electronics device, and everybody wants to get all the lat-est features without paying a dime. At one billion units per year, mobile phones now outsell virtually all other con-sumer electronic devices combined! In the dark ages of this industry (about 5 years ago), mobile phonescontained dozens of silicon chips and hundreds of discrete components, moreover, they were large, power-hun-gry, and lacking in features we take for granted today. Furthermore, today, only one-third of the world’s popula-tion owns a mobile phone. As the developing world continues to advance, mobile phones must also continue todecrease in cost and power consumption, since these performance measurements are crucial to serving theneeds of the global community allowing to the Internet starting gate.

Using the advanced techniques presented at ISSCC 2008, the mobile phones of the future will require only asingle silicon radio chip and a small handful of discrete components, yet they will incorporate dozens more fea-tures than your father’s (or your older brother’s) mobile phone: Worldwide roaming capability, 3G, WiFi andWiMax for high-speed Internet, GPS for interactive mapping and location-based services, Bluetooth for hands-free device-to-device connectivity, multi-megapixel cameras, and video camcorders for social networking serv-ices like Myspace, FM radio, broadcast TV, and on and on. But because of the extremely-high levels of integrationin the mobile chips to be presented at ISSCC 2008, the cost and power consumption of future phones will keepdecreasing while continuing to satisfy the consumers’ appetite for full-featured phones at little to no extra cost.

At ISSCC 2008 in San Francisco, researchers from Broadcom, Texas Instruments, and Infineon will describe sin-gle-chip breakthroughs for full-featured low-cost low-power mobile phones. These chips show the highest lev-els of integration ever presented, and promise to bring low-cost low-power mobile phones to the developingworld while incorporating ever-increasing features demanded by more-sophisticated consumers.



Papers: 11.1, 11.4, 11.7 [AP38,39] WIRELINE

PPRREESSSS CCOOPPYYHigh-Speed Optical Communication (and “Resource Recycling”)

Communication using light signals over optical fiber holds great promise to lower costs for all data transport overboth short and long distances. The huge bandwidth and favorable physical characteristics of optical fiber beg tobe exploited : In telecom networks, transmitting high-data-rate signals over long distances become practical; Incomputer systems, high-capacity interconnect, free from electromagnetic interference and awkward bulky cop-per cables, is enabled by parallel optics. But, of course, practical details limit cost-effective commercial solutions.

At ISSCC 2008, in February, several advances in the practical art of sending and receiving optical signals will bepresented. Inevitably, advances, such as those to be reported, will lead to exciting new cost-effective telecom serv-ices, and higher-performance computer systems improving our way of life.

In Papers [11.1 and 11.4], researchers from Ghent University and NTT will describe a burst-mode trans-imped-ance amplifier (TIA) and a burst-mode clock and data recovery (CDR) circuit, both in SiGe BiCMOS technology.The techniques to be reported allow a 10-fold increase in data-transmission speed, opening the way for the new10Gb/s passive-optical-network (PON) standard. Previous TIA circuits suffered from incorrect measurement ofburst amplitude due to limited gain in analog comparator circuits, and also due to noise. The device to be de-scribed by Ghent University uses a simple new architecture to lock the gain after a time delay to avoid theseproblems. Previous PON systems encode data in an inefficient manner, wasting 25 percent of the line capacity;Now, the newly-emerging PON standard uses a more efficient data code which, however, places more demandson the upstream burst-mode optical receiver. The device to be described by NTT uses a digital control and ADCto replace the traditional analog charge-pump to set the center frequency in a clock-recovery circuit.

In Paper [11.7], researchers from ClariPhy Communications, Irvine, CA, use DSP-based techniques to achieve10Gb/s data rate over multimode fiber, according to the 10GBased-LRM IEEE standard in a low-cost/low-powerintegrated solution. When multimode fibers are already installed, and it is cost-prohibitive to replace them withmodern high-capacity single-mode fiber; However, demand for higher-speed networks creates the need to in-crease the data rate from the current 1GB/s to 10GB/s. At higher speeds, the multimode fiber distorts the dataand traditional receivers cannot properly decode the information. But now, this new device from ClariPhy allowsmuch more complex equalization to extract the severely distorted data in a cost-efficient manner. Interestingly,one can see this as a particular example of recycling: Old resources are “cleaned up” for new use!




PPRREESSSS CCOOPPYY

Data Converters Downsize

Submicron CMOS Technology Rules in Data Converters

All new data converters to be presented at ISSCC 2008 are implemented in CMOS technologies. This year, thereis a large number of data converters designed in 65nm technology and the first 45nm CMOS converter imple-mentation will be reported.

In fact, data converters are closely following the scaling of digital-design technology to facilitate mixed-signalSoCs in the latest (densest available) CMOS technology generation. This is not straight forward: It requires over-coming the challenges of lower supply voltages, reduced transistor-device gain, and increased device leakage and1/f noise. Circuit and architecture innovation are both used to address these issues.

The technology for data converter introduced at ISSCC 2008 are summarized below:


0

2

4

6

8

10

>= 0

Te

0.18um 0.13u90n

Tech

echnology GData C

um-nm

65nm

hnology Gener


45nm

ration

or ISSCC 200apers

08 Table of ISSCC 2008 Converters Developments0.18µm CMOS 0.13µm CMOS 90nm CMOS 65nm CMOS 45nm CMOS

Paper 12.5 Paper 30.2 Paper 12.1 Paper 12.2 Paper 27.8









Papers: 12.4, 30.3, 30.8 [AP40, 80, 81] DATA CONVERTERS

PPRREESSSS CCOOPPYYData Converters at the Extremes

“Speed”, “power efficiency” and “low voltage” – these are the buzzwords in a world driven by high-speed andmobile data communications. Data converters are at the heart of the signal-processing challenge. This year, atISSCC 2008, the program highlights new milestones established in these 3 dimensions.

Extreme speed through extreme parallelism:Researchers from Nortel and STMicroelectronics (Paper 30.3) will demonstrate a 6b time-interleaved successive-approximation register (SAR) running at 24GHz sampling rate. The concept has been proven to be very power-efficient some years ago [1]. This is due to the power-saving nature of SAR where time-interleaving keeps thespeed requirements at an acceptable level. In this design, 160 SAR converters are interleaved to achieve 24GS/susing only 1.2W in 90 nm CMOS.

Extremely-low-voltage operation:Researchers from MIT (Paper 30.8) will present a development at another extreme: It is also a 6b converter, butone made applicable for wireless sensor-networks. As such, it needs to be highly-power-efficient and able to runat very-low supply voltages. In fact, the circuit operates down to 0.2V, employing a flash converter. Analog de-sign options at this voltage are limited, and depend heavily on sub-threshold-operation techniques. Redundancyis used to increase the resolution.

Extremely low power:Finally, researchers from the University of Twente and Philips (Paper 12.4) will discuss a design on extremely-low figure of merit (FoM) 4.4fJ / conversion-step. The key to such low power consumption is the avoidance ofany static biasing currents, and, again, the exploitation of the power-efficient nature of an SAR. In addition,charge-redistribution capacitors are switched via intermediate buffer capacitors, in order to reduce switchinglosses.

[1] D. Draxelmayr: “A 6b 600MHz Converter Array in 90nm CMOS”, presented at ISSCC 2004.

And so, at ISSCC 2008, in February, at the San Francisco Marriott Hotel, we will again be exposed to the verybroad spectrum of data-converter applications and corresponding design techniques.



Papers: 12.2, 27.4, 30.2, 30.3, 30.8 [AP40, 74, 80, 81] DATA CONVERTERS

PPRREESSSS CCOOPPYYData-Converter Implementation Trends

The evolving art of designing data converters is founded on a rich history of architectures and techniques developed over the years. Some of the trends that will be observed this year at ISSCC 2008, in several sessionsdevoted to converters, are:

• Interleaving: Higher degrees of interleaving enable high-speed converters [12.2, 27.4, 30.2, 30.3]

• Efficiency: The need for lower power dissipation is driving the exploration of new converter architectures.

• Digital Calibration: Increasing digital calibration is enabled by technology scaling, which makes cheap digital signal processing available to enhance converter performance.

• High-Speed ΔΣ Conversion: This technique is ubiquitous.

• Deep Submicron Technology: Increasing device density is advantageous for converter architectures that can exploit the inherent speed of technology, such as SARs and oversampled converters.

• Sub-Threshold Design: Operation at very-low voltages below the device threshold, provides maximum power efficiency and operation with an almost “dead” battery (down to 0.2V!) [30.8]

• Simple Amplifiers for Low Voltage: Simple “logic” inverters and open-loop amplification may replace op-amps in some architectures to achieve high speed and/or low-supply-voltage operation.



Papers: 12.1-12.8 [AP40, 41] DATA CONVERTERS

PPRREESSSS CCOOPPYY

High Efficiency is the Key to ADC Design

The bandwidth (BW) and the dynamic range (the signal-to-noise-and-distortion ratio, or SNDR) of an ADC arekey performance metrics for ADCs. ADC designers are challenged to achieve highest performance with lowest-possible power dissipation (P). Thus, power dissipation is the 3rd key parameter in evaluating ADC performance.In order to compare different designs, a single graph is generated by plotting P/(2xBW) [in Joules] against SNDR[in dB]. The lower, the better: This year, at ISSCC 2008, experts will describe several developments that offerbreakthrough performance for this metric.

The presentations highlighted as “ISSCC 2008 high-efficiency designs” in the graph, clearly break ground in up-to-date untouched areas. Unprecedented low power per unit bandwidth is revealed for a range different digitalresolutions.


+ ISSCC 1997-2007� High-Efficiency

Converters


Paper: 13.1 [AP42] LOW-POWER DIGITAL

PPRREESSSS CCOOPPYYx86 Goes Handheld: Breakthrough Reduces Power 5x

Your perception of a notebook PC could be about to change. It is fair to say that today’s notebooks are mobilebut certainly not handheld. One of the reasons for this lies in their power-hungry processors that dissipate 10Watts, and, therefore, require bulky batteries. These high levels of energy consumption heat up the processor.Consequently, large packages and electric fans are required in order to cool the processor.

The downside of Moore’s Law is that today’s ultrafast tiny transistors drain batteries even when they are notdoing any useful computing. Today’s PC processors are too big, too complicated, and too hot for tomorrow’shandheld and ultra-mobile devices.

But, all of this is changing! As will be reported at ISSCC 2008, Intel has developed a new very-low-power x86processor. By simplifying the design, reusing processor building blocks for more than one task, and puttinglarge parts of the processor to sleep when they are idle, this new chip can run at a 2GHz clock frequency withless than 2 Watts of power dissipation.

This latest Intel chip dissipates less power, thereby doubling battery life of handheld devices. Lower power con-sumption also removes the need for fans. Small-form-factor mobile devices are enabled by new smaller proces-sor packages. Inevitably, these technologies could lead to x86 devices integrated into mobile phones. Watchfor them soon!



Paper: 13.2 [AP42] LOW-POWER DIGITAL

PPRREESSSS CCOOPPYYAn Ultra-Low Power Cell Phone Solution in Advanced 45-nm Process

Moore’s Law is alive and kicking. Deep sub-micron process technologies allow the processor’s clock frequen-cies to soar and new functions to be added. Doubling transistor counts on a die allows integration of multipleprocessors onto one System-on-Chip (SoC) and demonstrates the next generation communication standards andmultimedia applications. In turn, these new functions open the consumer electronic space for advanced mobilecellular devices. However, because mobile phones are battery operated, include smaller transistors and newand faster functions, these high-performance, multi-processor architectures conflict with the requirement tolower power consumption for long battery lifetimes.

At ISSCC 2008, researchers from Texas Instruments (Paper 13.2) will describe a 45nm SoC with 10M gates and16Mbits of memory, and analog modules including RF-Codec. The paper highlights TI 45nm low-power ad-vanced CMOS process technology and digital and analog design platform. The SoC is an advanced cellularmodem with support for multiple standards that will provide the necessary bandwidth for a range of rich appli-cations. The SoC also integrates a high-performance multimedia, multiprocessor engine based on an ARM11 thatsupports up to 840MHz, a DSP that supports up to 480MHz, and an image signal processor that supports up to240MHz, for a lifelike entertainment experience on your handset.

TIs SmartReflex™ Performance and Power Management Technologies enables orders of magnitude power re-duction from the max power to deep sleep mode. The most sophisticated low-power techniques have been im-plemented to achieve low power. Implementing such advanced power management schemes is becoming simpleand pervasive to the SoC designer, with the introduction of advance power management automation tools andmethodology.



Paper: 14.5 [AP45] MEMORY

PPRREESSSS CCOOPPYYGraphics DRAM enters the 6Gb/s/pin Era with Single-Ended I/O

It has been long believed that differential input-output (I/O) systems, that is ones using two complementary sig-nals to convey a single bit of information, could achieve the highest speeds, simply because of its robustnessagainst noise in the channel. Because of the extra signal overhead of differential signaling, cutting-edge demandof even-higher speeds in graphics and game applications, now pushes the use of single-ended I/O. Until now,the best performance has been 4Gb/s/pin, as presented at ISSCC 2007, by Samsung.

At ISSCC 2008, in San Francisco, Samsung, in the context of the first-published GDDR5 DRAM in 60nm tech-nology, will introduce the highest-rate single-ended I/O link, operating at 6Gb/s/pin. Such GDDR5 I/O must bewell-adapted and well-optimized to such noisy memory-channel environments. Samsung will reveal how this ex-treme speed can be achieved through the use of novel design techniques such as decision-feedback equaliza-tion, adjustable clocking with a PLL for programmable bandwidth and data-bus inversion.

More details of the implementation of this new scheme will be disclosed at ISSCC 2008, at the San Francisco Mar-riott Hotel in February, 2008.




PPRREESSSS CCOOPPYYTables That Talk!

Ok, so you just bought a new cool computer for your Dad’s 60th birthday so he could play Sudoku and video con-ference with his grand kids. It came with a printer, camera, keyboard, and a display. You know that it is alsogoing to come with quite a few cables with color-coded instructions on how he could plug them all in and viola!Except, of course it is never that easy, is it? Now imagine this, when you ordered the computer it also came witha communication sheet that he can unroll and put on the table. Now, all he has to do is place the computer,printer, camera, keyboard, and the display on the communication sheet. And the communication sheet takescare of connecting everything. No wires. No color-coding. And no wait time for a customer support call. If re-searchers from Japan have their way, your Dad can probably do just that by his 65th birthday!

At ISSCC 2008, researchers from University of Tokyo and Keio University (Paper 15.4) will describe a printablecommunication sheet that consumes 107pJ/b and transporting data at 100kb/s. The cable free connectivity be-tween devices is achieved without the use of traditional wireless radio. The devices talk to each other throughthe communication sheet that facilitates meter-scale wired communication and micrometer-scale wireless ca-pacitive coupling communication. This hybrid communication system achieves the lowest energy per bit in per-sonal area wireless networks.



Papers: 16.1, 16.2 [AP48] LOW-POWER DIGITAL

PPRREESSSS CCOOPPYYAdvances in Dynamic Image Understanding

Many advanced applications that will have a profound impact on our future lifestyle rely on image understand-ing. Examples include: intelligent vehicle control, smart home surveillance, airport security, and so on. Unfor-tunately, existing hardware solutions for image understanding lacks the performance, form factor, and costeffectiveness, needed to make these functions practical. This year, at ISSCC 2008 in San Francisco, two pre-sentations (in Session 16) will demonstrate breakthrough solutions for image understanding that can be effec-tively used in our daily life.

Researches from, National Taiwan University (Paper 16.1) will describe iVisual, an intelligent visual sensor Sys-tem-on-Chip (SoC) integrating a CMOS image sensor and four high-performance low-power processors for vi-sion processing. This single-chip SoC provides impressive system throughput at the highest power efficiencyavailable to date, enabling powerful visual capture and image analysis to be done at low power and with a smallform factor.

Another solution, to be presented by researches from the Korea Advanced Institutes of Science and Technology(KAIST) (Paper 16.2), is a Network-on-Chip (NoC)-based parallel processor. This low-latency NoC employs ad-vanced architectural features such as dual-channel communication and adaptive switching, as well as circuit-levelpower saving techniques such as packet-based clock gating, to enable more accurate image understanding, ata level that mimics human brain functions at low power levels.

Clearly, with these innovations in image-understanding solutions, we are now another step closer to the futurewhere our lives are more secure, more safer, and more comfortable.



Papers: 16.6, 16.7 [AP48] LOW-POWER DIGITAL

PPRREESSSS CCOOPPYYA New Step in Lowering Microprocessor Power Consumption:Sub-threshold Design for Ultra-Low Voltage System-on-Chip

Ultra-mobile handheld Internet devices have permeated the industry over the past few years following (and lead-ing) rather explosive growth projections. These devices demand peak performance levels which, while not as ag-gressive as those needed less by traditional mobiles and laptops, require active and standby-power levels thatare extremely aggressive, with sub-1mW and 1μW levels needed, respectively, for entire ultra-mobile systems-on-chip. Supply voltage scaling has historically provided the most powerful control knob for lowering energy con-sumption. Now, going below usual low voltage levels, sub-threshold / ultra-low-voltage design is emerging asa new trend for reducing power in ultra-mobile platforms, taking the voltage-scaling paradigm to its extremelimits by scaling the voltage supply below the transistor’s high-current switching- threshold voltage.

At ISSCC 2008 researches from MIT and TI (Paper 16.7) introduce a sub-Vt 16b microcontroller, whose core logicoperates down to 300mV with only 1μA of standby supply current theme. It includes several novel sub-thresh-old circuit ideas which are integrated to achieve operation at a milestone power-performance level. As well, re-searchers from Intel (Paper 16.6) will unveil a sub-threshold video motion-estimation accelerator in 65nm CMOS,targeted for on-die acceleration of video-encoding workloads on mobile microprocessors. This chip integratesseveral novel ultra-low-voltage circuit ideas to achieve an industry-leading 411Giga-operation per second perWatt. This allows a very wide range of usage, maximizing the battery life.




PPRREESSSS CCOOPPYYBroadband Transceivers Open the Door to Cheap

Multi-Mode Mobile Terminals

The diversity and worldwide expansion of wireless communication leads to mobile terminals that comply withmultiple standards, including broadcasting, cellular, WLAN, WPAN, and so on. These applications are charac-teristically spread over a wide range of carrier frequencies. The only possibility for a low-cost implementation isone that uses wideband reconfigurable RF front-ends. Low-area implementation in a cheap CMOS technology isa must, with minimal use of inductors.

This year, at ISSCC 2008 in San Francisco, several new circuit developments will be presented that tackle the im-portant technological challenge of broadband receivers with sufficient noise and linearity performance.

The impact of CMOS high-speed performance will be demonstrated by the oversampling discrete-time mixer tobe presented by researchers from the University of Twente. It operates at a speed 8 times higher than the RF fre-quency output. Researchers from IMEC will present a novel frequency-generation technique that minimizes diearea by using only one inductor in a VCO that has dual-band operation. Finally, the use of inductors is totally aban-doned by researchers from the University of Twente who will demonstrate the smart combination of LNA, balun,and mixer in a single block.




PPRREESSSS CCOOPPYYDangerous Bacteria Identified by Microchip

Imagine a low-cost, disposable hand-held device that can be used to detect whether drinking water drawn froma well is safe from E. coli bacteria, or, rapidly detecting whether Staphylococcus aureus has contaminated aschool or hospital.

At the International Solid-State Circuits Conference this February 2008, researchers from the University of Toronto(Paper 18.4) will present a CMOS microchip that can detect dangerous bacteria in just a few minutes. The tech-nique relies on the use of a low-cost integrated circuit and bacteriophage (phage). Phages are viruses that infectand then reproduce within the host bacteria, ultimately killing them. There are a wide variety of known phageseach one specific to a particular type of bacteria. Phages are easy to produce and store, and as a result the mi-crochip presented has application in detecting a wide variety of bacterial diseases, including cholera, dysentery,listeria and some forms of pneumonia.

When a phage injects its DNA into a host bacterium, the cell wall of the bacterium is disrupted and intra-cellularionic fluid leaks out. The flow of the ionic fluid can be detected with electrodes and sensitive electronics, in a tech-nique first developed in the laboratory by Dobizi-King et al (2005). Since this phage-based technique detectsonly living cells, dead cells present after disinfection do not create false positives.

Researchers from the University of Toronto have now integrated the overall concept onto an ultra-portable mi-crochip using standard CMOS technology that costs less than one dollar and runs on batteries. The test is sim-ple as it only requires that a sample droplet be placed on the chip for evaluation. The chip is low-cost and thereforeallows the detector to be used once and disposed of. The world will now be a bit safer for a lot more people!



Papers: 19.1 - 19.7 [AP52, 53] ANALOG

PPRREESSSS CCOOPPYYDigitally Enhanced Clocking: A New Paradigm

The performance of a communication or computing system is critically dependent on the accuracy and purity ofthe required clocks. Phase-locked loops (PLLs) and oscillators are key building blocks for accurate timing, andare conventionally analog-intensive circuits. As semiconductor technology (especially CMOS) continues to scaledownward, the cost of digital gates is decreasing dramatically, but the cost of analog circuits remains the sameor even becomes relatively higher. More seriously, the performance of analog circuits is degraded with the lowersupply voltages necessitated by down-scaled technologies. Correspondingly, one sees a trend to replacing ana-log circuits with digital equivalents, and/or improving the performance of analog circuits with the help of digitalsignal processing. At ISSCC 2008, papers in Session 19 will reflect this trend, very well.

Researchers from MIT (Paper 19.1) and University of Pavia and STMicroelectronis (Paper 19.3), will describe,digital PLLs that replace all analog blocks with digital equivalents. They have achieved comparable or even-bet-ter performance than analog PLLs by employing various kinds of digital calibration techniques. Researchersfrom UC San Diego and Next Wave Wireless (Paper 19.2) and Tsinghua University (Paper 19.4), improve the qual-ity of analog PLL outputs by using digital filtering embedded in analog circuits.

Researchers from University of Twente (Paper 19.5), will deal with a technique for improving the noise charac-teristics of analog relaxation oscillators. The resulting circuit has performance near the theoretical limit. Further,researchers from Mobius Microsystems and University of Utah (Paper 19.6), will describe in a digitally-com-pensated CMOS oscillator, of such quality as to replace a crystal oscillator, which is one of the last remainingoff-chip components used in timing circuits. As a bridge of crystal and crystal-like clocking between the sug-gested two extremes above, researchers from Sirenza (Paper 19.7), will present a technique for compensatingthe variations of crystal oscillators by minimizing the switching energy associated with capacitor arrays.



Papers: 20.2, 20.4 [AP54] WIRELESS

PPRREESSSS CCOOPPYYWireless Access: “N”-Abling the Future of WLAN

The demand for ubiquitous low-cost high-rate wireless communications for applications such as video distri-bution has spurred the innovation in wireless transceiver ICs. The standard addressing this need in local area net-works (LANs) is the IEEE 802.11n which uses multiple-input/multiple-output (MIMO) technology to enhance therate-versus-range performance of the transceivers in a multi-path environment. At last year’s ISSCC, a radiowith throughput capability of over 270Mb/s was presented by researchers at Broadcom.

This year, at ISSCC 2008 in San Francisco, researchers from Atheros will report the first-published fully-integrated2×2 MIMO radio SoC, incorporating two dual-band RF transceivers, analog base-band filters, data converters,digital PHY and MAC, and a PCI Express interface. This IEEE 802.11n-draft-compliant SoC solution shows aUDP throughput of up to 216Mb/s with a small die size of 36mm2. This level of integration would allow for sig-nificant reductions in the cost of deployment of the 802.11n technology, and enables cost-sensitive and/or area-constrained applications to be able to take advantage of the benefits of this standard.

The ultimate goal of process-scalable RF functionality, with no restrictions on supply-voltage reductions andeasy co-integration with digital logic, has been a challenge for researchers for many years. But with conventionalRF circuits, it has become increasingly difficult to cope with the deceasing supply voltage, and also to take max-imum advantage of the shrinking of the transistors in advanced ever-smaller process. However, recent workuses switched-capacitor (SC) filtering techniques in radio receivers that exhibit some flexibility, but not enoughfor some applications, due to failure to meet strong interferer-attenuation requirements.

At ISSCC 2008, researchers from STMicroelectronics will present a discrete-time Wi-Fi/WiMAX receiver whichis compliant to IEEE 802.16e and 802.11b/g/n. The receiver, based on an innovative merger of SC mixer, filter,and charge-redistribution interleaved SAR ADC, is scalable and relatively insensitive to supply-voltage scaling.It is also easy to co-integrate with RF, analog, and digital functions, paving the way for future generations ofvery-highly-integrated highly-scalable transceivers.



Paper: 21.1 [AP56] Memory

PPRREESSSS CCOOPPYYCACHE-45: The First & Largest Cache with High-κ

Metal-Gate Technology at 45nm

Embedded SRAM is now breaking into 45nm technology with innovations providing high-performance and low-power operation which takes advantage of new device structures and new circuit techniques. At ISSCC 2008, de-velopers from Intel will present the first-published use of high-κ metal-gate technology in a L2-cacheimplementation on a CPU chip. They will report on the 3.8GHz performance at 1.1V of a 153Mb silicon cache,for an Intel CoreTM2 CPU chip.

Novel circuit techniques, such as dynamic forward-body biasing for SRAM stability enhancement, and the as-sistance of on-die programmable active leakage-control circuit, address the escalating issues surrounding PVTvariations, as scaling continues into the 45nm level.

Details of these innovations will be revealed at ISSCC 2008, at the San Francisco Marriott, in February, 2008.




PPRREESSSS CCOOPPYYTechnologies for Self-Correcting Processors

As process technology continues to scale downward, smaller feature-size technology exhibits increased vari-ability. At the same time, environmental operating factors such as the ambient temperature and the supply volt-age, have a stronger impact on the performance of processors. Both factors have resulted in a greater uncertaintyin the maximum performance and power consumption of processors across operating conditions and from onemanufactured die to the next.

Typically, these uncertainties are addressed by adding timing and voltage safety margins to ensure that theprocessor has sufficient headroom across all possible silicon and environmental conditions. However, for mostmanufactured die and for most operating conditions, this approach is highly conservative, and results in theprocessor operating with unnecessary margins, ones that waste area, power, and performance.

At ISSCC 2008, (in Papers 22.1 and 22.2) researchers from the University of Michigan and Intel provide the firstpublication at ISSCC of a technology referred to as “Razor”, that eliminates many of these wasteful margins byemploying a novel self-correcting method. With this self-correcting technology, the voltage or frequency mar-gins of a processor can be dynamically reduced during operation until the processor starts to register self-cor-rection events. Hence, the proposed approach introduces a paradigm shift in how processors are operated andcontrolled. The traditional approach adds conservative safety margins to ensure that the processor is guaranteedto operate correctly in the face of all possible environmental and silicon variations. In this approach, margins aredynamically tightened during the operation of the processor, until the point where the processor starts to self-correct and no unnecessary margins remain.

Researchers at the University of Michigan implements this approach in a 64bit Alpha processor prototype andperforms self-correction for upsets due to radiation strikes. Intel implements the technology in a stand-alonepipeline, while both groups introduce similar approaches, they do so with different clocking and complexitytrade-offs. Together, they demonstrate a means to significantly reduce the complexity of the approach, makingit a viable candidate for addressing process and environment variation in a fundamentally new way. These de-velopment groups report between 25 and 30% power saving using the approach.



Papers: 22.5, 22.6, 22.7 [AP64, 65] HIGH-PERFORMANCE DIGITAL

PPRREESSSS CCOOPPYYGetting a Handle on Process Variation and Degradation

As technologies continue to scale downward, and device dimensions shrink to finer and finer dimensions, theintrinsic variability of transistors continues to increase. This means that any two otherwise identically-drawntransistors will have significantly different performance. Over an entire chip of billions of transistors, this prob-lem of variability means that circuit behavior across the chip will vary dramatically. To prevent the resulting volt-age mismatches and timing errors from causing problems, designers build significant margins into their circuits,leading to extra area and cost, longer design time, and added power consumption. A related problem has to dowith the aging and degradation of devices and circuits, and the necessary margins to prevent these time-de-pendent effects from generating errors. Worse yet, designers often do not have data quantifying the actual mar-gins needed, resulting in overly-conservative designs.

At ISSCC 2008, researchers from IBM and PA Semi will feature innovations in three areas of process monitor-ing. Researchers at IBM will show a completely digital on-chip circuit that can measure local random variationin a small array of transistors: Small variations in transistor current result in different output clock frequencies,which are easily and rapidly measured. Developers at PA Semi extend this notion of digitally measuring individ-ual transistors to a digital process monitor that can track timing races, clock jitter, and leakage: This process mon-itor has been integrated into a final product. Researchers at the University of Michigan build a digital monitor totrack not only the aging of p-type transistors, whose voltage characteristics can change under stressed operat-ing conditions, but also tracks the effects of oxide degradation.

All three groups implement compact low-cost in-situ sensor circuits that translate circuit variations or degrada-tions into easily-measured digital outputs. Their statistically significant measured results are useful not only toinform future circuit and process designs but also to enable better product binning and to predict future chip fail-ures.



Papers: 24.4, 24.8 [AP68 69] ANALOG

PPRREESSSS CCOOPPYYExtending the Limits:

Power Regulators with Higher Efficiency and Wider Bandwidth

The next generation of cellular phones has extremely high data-rates. This poses a great challenge to the de-signers of clean and power-efficient power regulators needed to extend both the talk time and standby time of acellular phone, which is powered by rechargeable batteries. Presentators at ISSCC 2008 will address the im-portant topics of the efficiency of power-supply regulators operating at low-power levels, as well as improvementsin the power-hungry RF power modules in wireless-communication systems with wide bandwidth.

Researchers from the Hong Kong University of Science and Technology (Paper 24.4) will describe a new pulse-width modulator that automatically selects its operating frequency to provide highly-efficient power regulationwith light loads, while maintaining a predictable EMI spectrum to avoid interfering with sensitive RF electroniccircuits inside cellular phones. This operation provides a clean high-efficiency power supply for low-power cell-phone applications such as MP3 playback, while the major components of the cellular phone operates in thestandby mode.

Also, at ISSCC 2008, researchers from Arizona State University (Paper 24.8) will present a new architecturecombining linear and switching regulators for CDMA RF power modulation. The new power regulator has higherefficiency than conventional linear regulators, but has the wide bandwidth (up to 10MHz) needed by a highly ef-ficient and linear polar transmitter in a wide-bandwidth CDMA system. This approach has the potential to sig-nificantly increase the talk time of a CDMA cellular phone.

Details of such recent developments; and other analog power techniques for fast-transient linear regulators andsingle-inductor multiple-output converters, will be discussed at ISSCC 2008 in February at the San Francisco Marriott Hotel.



Papers: 25.1 and 25.9 [AP70,71] WIRELINE

PPRREESSSS CCOOPPYYInjection-Locking for Clock Generation and Data Recovery

Injection-locking is an emerging technique that is finding application in Wireline and Wireless systems. In thistechnique, clean low-frequency reference clock is periodically injected to clean up the high-speed clock. How-ever, the injection process itself causes large reference spurs which adversely affect the performance of systemssuch as radio front-ends and A/D converters. At ISSCC 2008, researchers from Conexant (Paper 25.2) will showhow to combine the advantages of a PLL and of a DLL to achieve a very-low phase noise of -122dBc/Hz at 200kHzoffset, and yet have a low reference spur of -48dBc. Conventionally, such performance is possible only withhigh-quality LC oscillators. But here, a ring oscillator that has a very low area and low power consumption is usedto accomplish the task. The clock generator occupies 0.048mm2 in a 90nm CMOS process, and consumes only15mW.

Also, researchers from Intel and University of Washington (Paper 25.1) will show how to extend the benefits ofinjection-locking to enable phase tuning. The injection-locked oscillator (ILO) output locks to the injected fre-quency within its lock range. However, by detuning the oscillator frequency away from the injection frequency,clock-phase shift in excess of 180˚ (1UI) is achieved. This technique simultaneously filters the jitter in the in-coming injected clock and also adjusts the phase of the output clock in order to sample the incoming data at theright instant.

These benchmark presentations should encourage the technical community to carry out further research in in-jection-locking technique for higher speed as well as for more-diverse applications.




PPRREESSSS CCOOPPYYTeraHertz (THz) CMOS Around the Corner!

After the recent CMOS colonization of the mm-wave frequency range, where 60GHz chipset transceivers forultra-high-data-rate short-range links are approaching the commercialization phase, the availability of further-scaled CMOS processes opens up new portions of the electromagnetic spectrum to novel large-scale cost-ef-fective applications; In particular, the 300GHz-to-3THz spectrum has a host of scientific, engineering, and medicalapplications. For example, the chemical signature of many practically important molecules occurs at THz fre-quency and chemical detection is of increasing interest to many applications including research and security; Aswell, THz imaging allows vision through objects, lending itself to usage in medical imaging applications such ascancer detection; Finally, THz radiation from space contains important information on life itself, including the birthof galaxies and the origin of the universe.

This year at ISSCC 2008, very significant advances in the design of key THz building blocks at THz frequency willbe presented. Universally, they are realized in standard (that is, relatively inexpensive) CMOS technologies.

A striking example of what is achievable in the field of THz frequency generation will be provided by a team in-cluding researches from the University of Florida, NXP Semiconductors, and TI-Dallas. They describe the gen-eration of a record 410GHz signal from a 205GHz differential oscillator which employs a state-of-the-art 45nm6-metal digital CMOS process. Signal detection at these frequencies is itself a major challenge, which these re-searchers have addressed by designing an on-chip patch antenna, and employing a sophisticated system (namely,Fourier-transform infrared spectroscopy).

Yet another work breaking the 300GHz barrier will be disclosed by a mixed team from UCLA and JPL. In this work,a signal at 324GHz is obtained by quadrupling a fundamental frequency of 81GHz generated by an oscillator ca-pable of delivering four interleaved signals. The output signal is collected on-chip through a customized wave-guide probe. The design has been implemented in a standard 90nm CMOS process, indicating that further speedenhancements can be reaped by its migration to more modern smaller-feature-size technologies.

Turning the focus from speed- to power-efficiency, a fully-integrated 5GHz oscillator with an unprecedented-lowpower-consumption will be reported by an Italian and Swedish team using a standard 130nm CMOS process, inthe ever-ongoing quest for power consumption reduction and complete integration in hand-held cellular appli-cations.



Paper: 28.1 [AP76] MEMORY

PPRREESSSS CCOOPPYYBreakthroughs in NAND Flash Architectures

NAND Flash memory is becoming more-and-more attractive as the ultimate data-storage solution. Memory-hungry applications are emerging every day, taking advantage of the low cost, and high density of multi-levelNAND Flash. At ISSCC 2008, researchers from Samsung will show how to take multi-level NAND design one bigstep further, into three-dimensional silicon integration. Designed in an advanced 45nm Floating-Gate CMOStechnology, and using a 2-bit-per-cell configuration, this chip is the first NAND Flash to utilize multiple-silicon-layer stacking. The design features novel solutions to problems of accessing the two stacked memory-arrays.

This memory organization results in a record spatial density, namely 0.0021µm2/bit, which is significantly smallerthan previously-reported designs.

Details of these developments will be revealed at ISSCC 2008 at the San Francisco Marriott, in February.




PPRREESSSS CCOOPPYYNew MEMS-Based Radio Enables Wireless Sensor Networks

Wireless Sensor Networks are an exciting new technology for use in health care and security products, but re-quire unattended battery operation for 3 to 5 years. One way to achieve this is through the integration of RF-MEMSwith CMOS technology.

At ISSCC 2008, researchers from CSEM (Paper 29.1) will demonstrate the integration of RF-MEMS togetherwith CMOS technology in a 2.4GHz RF transceiver achieving higher miniaturization and lower power consump-tion. This miniaturized radio has been developed to be used in wireless sensor network and medical wireless ap-plications.

This tiny, long-life wireless sensor network creates a tremendous unprecedented range of applications such as,ubiquitous health care, environmental, and security-and-safety monitoring. The miniaturization and low-powerfeatures are achieved by taking advantage of the high-Q of bulk acoustic wave (BAW) resonators for low-phasenoise and low-power. The limited frequency tuning capabilities of BAW VCO is circumvented by a new wirelesstransceiver architecture preserving the low-phase noise feature and allowing for extended tunability at the inter-mediate frequency (IF). The frequency synthesizer uses temperature-compensated and piezo-activated siliconMEMS resonators integrated together with the RF BAW resonators to get rid of the external bulky quartz crys-tal, to achieve further miniaturization.




PPRREESSSS CCOOPPYYRF & mm-Wave Power

Power amplifiers are among the most difficult-to-realize components in low-cost wireless systems. Thanks tothe latest process technologies, designers are now able to miniaturize these amplifiers and to reach extremelyhigh data-rates. As an example, the introduction of inexpensive millimeter-wave (mm-wave) systems in the60GHz frequency band, using CMOS technology will encourage applications such as wireless streaming of HDTVinside buildings.

Among the highlights of the program, the first implementation of a complete mm-wave transceiver in a standard90nm CMOS technology will be presented by researchers from NEC. As well, a CMOS power amplifier with arecord operating frequency of 77GHz will be presented by researchers from Fujitsu Laboratories. Both of theseimplementations are targeted at applications such as very-high-speed short range wireless data-links and auto-motive radars.

Sophisticated digitally controlled nonlinear power amplifier (PA) architectures are needed to significantly im-prove the PA’s power efficiency, boosting battery life and data rates. Cutting-edge envelope elimination andrestoration (EER) and outphasing systems implemented in advanced CMOS technologies will be presented byresearchers from STMicroelectronics, U Washington and Intel, and UCLA and Matsushita. Such PA techniqueswill become in a very-short term an enabling technology for highly integrated and flexible multi-media phonesrequiring software-defined radio architectures for unlimited access to all available communication systems.

In the meantime, the two fully-integrated power amplifier modules presented at ISSCC will immediately help toreduce significantly the size and cost of cell-phones for the existing 2G and 3G standards.



NOTES

ContactInformation


ANALOG (Sessions 3, 19, 24)

Bill Redman-WhiteNXP Semiconductors

Office: [email protected]

DATA CONVERTERS (Sessions 12, 27,30)

David RobertsonAnalog Devices


HIGH-PERFORMANCE DIGITAL(Sessions 4, 22)

Samuel [email protected]

IMAGERS, MEMS, MEDICAL, and DISPLAYS(Sessions 2, 8, 32)

Daniel McGrathEastman Kodak


LOW-POWER DIGITAL (Sessions 13, 16)

Wanda GassTexas Instruments


MEMORY (Sessions 14, 21, 23, 28)

Hideto HidakaRenesas Technology


RF (Sessions 9, 17, 26, 31)

John LongDelft University of Technology


TECHNOLOGY DIRECTIONS(Sessions 7, 15, 18, 29)

Anantha ChandrakasanMassachusetts Institute of Technology


WIRELESS (Sessions 6, 10, 20)

Trudy StetzlerTexas Instruments


WIRELINE (Sessions 5, 11, 25)

Franz DielacherInfineon Technologies Austria


Technical Experts


PROGRAM CHAIR, ISSCC 2008

Yoshiaki HagiharaSony Corporation

Office: +81-46-201-3401Fax: +81-46-202-6275

[email protected]

PROGRAM VICE-CHAIR, ISSCC 2008

Bill BowhillIntel

Office: 978-553-2829Fax: 978-552-2800

[email protected]

PRESS-RELATIONS CHAIR

Kenneth C. SmithUniversity of Toronto

Office: 416-418-3034Fax: 416-971-2286

[email protected]

PRESS LIASION

Diane MeltonCourtesy Associates

Office: 202-367-2456Fax: 202-973-8722

[email protected]

CONTACTS

Editor-in-Chief: Kenneth C (KC) Smith

Editorial Team: Mandana Amiri, Glenn Gulak, Shahriar Mirabassi,

Kostas Pagiamtzis, Richard Spencer

Publisher: Laura Chizuko Fujino

Publishing Team: Steve Bonney, Nancy Violette

isscc 2008 press kit

Documents